DETAILED ACTION
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claim 13 is objected to because of the following informalities:
Claim 13, line 11, “encapsulate” should be “encapsulant”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 1, the limitation “an encapsulant between the buffer material and an inner wall of a cavity in which the semiconductor substrate and stack of bonding materials are disposed” renders the claim indefinite, as a cavity defines a space within an element, and no corresponding element is specified in the claim. In light of the specification, the limitation will be interpreted as “a package substrate comprising a cavity; and an encapsulant between the buffer material and an inner wall of the cavity in which the semiconductor substrate and stack of bonding materials are disposed”. Independent claims 13 and 18 will be interpreted similarly.
Claim 10, which depends from claim 1, will be correspondingly interpreted as “wherein the semiconductor substrate is attached to the package substrate”, and claim 11 as “wherein the cavity is defined by a first surface of the package substrate that is recessed relative to a second surface, the semiconductor substrate attached to the first surface”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 5-6, 8-14, 16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hanaoka (U.S. PGPub 2016/0282609) in view of Koizumi (U.S. PGPub 2007/0029562).
Regarding claim 1, Hanaoka teaches an apparatus (Figs. 4A-4B) comprising a translucent panel (71, [0060]), a semiconductor substrate (1, [0052]), a bonding material between the translucent panel and the semiconductor substrate (61, [0060]), a buffer material extending along a lateral side of the bonding material (81, [0062]), a package substrate comprising a cavity (90/93, [0064]), and an encapsulant between the buffer material and an inner wall of the cavity in which the semiconductor substrate and the stack of bonding materials are disposed (98, [0067]).
Hanaoka does not explicitly teach wherein the bonding material is a stack of bonding materials.
Koizumi teaches a translucent panel, a substrate, and a stack of bonding materials between the translucent panel and the substrate (Fig. 3, 23B, 21, 24A/B/23A, [0059]-[0060]) and a buffer material extending along a lateral side of the bonding material (26A, [0060]).
Therefore it would have been obvious to a person having ordinary skill in the art before the effective filing date to combine the teachings of Koizumi with Hanaoka such that the bonding material is a stack of bonding materials for the purpose of simplifying manufacturing and reducing cost (Koizumi, [0053]).
Regarding claim 2, the combination of Hanaoka and Koizumi teaches wherein the buffer material and the encapsulant have different compositions (Hanaoka, [0063]-[0064], inorganic barrier, epoxy sealing resin).
Regarding claim 5, the combination of Hanaoka and Koizumi teaches wherein the buffer material extends between the translucent panel and the semiconductor substrate along the lateral side of the stack of bonding materials (Hanaoka, Figs. 4A-4B; Koizumi, Figs. 5C-5D).
Regarding claim 6, the combination of Hanaoka and Koizumi teaches wherein the buffer material is a thin film coating on the lateral side of the stack of bonding materials (Hanaoka, Figs. 4A-4B; Koizumi, Figs. 5C-5D).
Regarding claim 8, the combination of Hanaoka and Koizumi teaches wherein the buffer material extends along a perimeter of at least one of the translucent panel or the semiconductor substrate (Hanaoka, Figs. 4A-4B).
Regarding claim 9, the combination of Hanaoka and Koizumi teaches wherein the buffer material surrounds the stack of bonding materials (Hanaoka, Figs. 4A-4B).
Regarding claim 10, the combination of Hanaoka and Koizumi teaches wherein the semiconductor substrate is attached to the package substrate (Hanaoka, Fig. 4B).
Regarding claim 11, the combination of Hanaoka and Koizumi teaches wherein the cavity is defined by a first surface of the package substrate that is recessed relative to a second surface, the semiconductor substrate attached to the first surface (Hanaoka, Fig. 4B).
Regarding claim 12, the combination of Hanaoka and Koizumi teaches wherein the cavity is defined by a sidewall extending between the first surface and the second surface, the buffer material to be spaced apart from the sidewall (Hanaoka, Fig. 4B).
Regarding claim 13, Hanaoka teaches a digital micromirror device ([0005], Figs. 4A-4B, [0059]) comprising a semiconductor substrate supporting an array of micromirrors (1, [0052], [0060]), a window spaced apart from the array of micromirrors (71, [0060]), a bonding material coupling the window to the semiconductor substrate, the bonding material adjacent a perimeter of the semiconductor substrate and the window to at least partially enclose an open space between the array of micromirrors and the window (61, [0060]), a buffer material in contact with the bonding material, the buffer material on a side of the bonding material opposite the open space (81, [0062]), a package substrate comprising a cavity (90/93, [0064]), and an encapsulant between the buffer material and an inner wall of the cavity in which the semiconductor substrate and the stack of bonding materials are disposed (98, [0067]).
Hanaoka does not explicitly teach wherein the bonding material comprises layers of bonding materials, wherein the buffer material is in contact with multiple ones of the layers of bonding materials.
Koizumi teaches a window, a substrate, and a stack of bonding materials between the window and the substrate, enclosing an open space between the window and the substrate (Fig. 3, 23B, 21, 24A/B/23A, [0059]-[0060]), where a MEMS device is supported by the substrate (22, [0063]), and a buffer material in contact with multiple ones of the layers of bonding materials, the buffer material on a side of the layers of bonding materials opposite the open space (26A, [0060]).
Therefore it would have been obvious to a person having ordinary skill in the art before the effective filing date to combine the teachings of Koizumi with Hanaoka such that the bonding material comprises layers of bonding materials, wherein the buffer material is in contact with multiple ones of the layers of bonding materials for the purpose of simplifying manufacturing and reducing cost (Koizumi, [0053]).
Regarding claim 14, the combination of Hanaoka and Koizumi teaches wherein the buffer material separates the encapsulant from the layers of bonding materials (Hanaoka, Fig. 4B).
Regarding claim 16, the combination of Hanaoka and Koizumi teaches wherein a shape of an outer surface of the buffer material corresponds to a shape profile of the side of the layers of bonding materials opposite the open space (Hanaoka, Fig. 4B, Fig. 9).
Regarding claim 18, Hanaoka teaches a method comprising, bonding, via a bonding material, a translucent panel to a semiconductor substrate, the translucent panel to extend across an array of micromirrors on the semiconductor substrate (Fig. 5A, semiconductor substate 10, translucent panel 70, bonding material 60, micromirrors 50, [0074]-[0075]), depositing a buffer material to outer edges of the bonding material (Fig. 7A, [0078], 81), disposing the bonded semiconductor substate and translucent panel in a cavity of a package substrate (Fig. 8C, [0081]), and depositing, after depositing the buffer material, an encapsulant between the buffer material and an inner wall of the cavity in which the semiconductor substrate and the bonding material is disposed, wherein the buffer material separates the encapsulant from the bonding material (Fig. 4B, [0081], 98)
Hanaoka does not explicitly teach wherein the bonding material is a stack of bonding materials and depositing the buffer layer to outer edges of the layers of the bonding materials.
Koizumi teaches a window, a substrate, and a stack of bonding materials between the window and the substrate, enclosing an open space between the window and the substrate (Fig. 3, 23B, 21, 24A/B/23A, [0059]-[0060]), where a MEMS device is supported by the substrate (22, [0063]), and a buffer material in contact with multiple ones of the layers of bonding materials, the buffer material on a side of the layers of bonding materials opposite the open space (26A, [0060]).
Therefore it would have been obvious to a person having ordinary skill in the art before the effective filing date to combine the teachings of Koizumi with Hanaoka such that the bonding material is a stack of bonding materials and depositing the buffer layer to outer edges of the layers of the bonding materials for the purpose of simplifying manufacturing and reducing cost (Koizumi, [0053]).
Regarding claim 19, the combination of Hanaoka and Koizumi teaches wherein the buffer material and the encapsulant have different compositions (Hanaoka, [0063]-[0064], inorganic barrier, epoxy sealing resin).
Regarding claim 20, the combination of Hanaoka and Koizumi teaches wherein depositing the buffer material includes depositing a thin film coating along exposed portions of the outer edges of the layers of the bonding materials (Hanaoka, Figs. 4A-4B; Koizumi, Figs. 5C-5D).
Claims 3, 7, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Hanaoka (U.S. PGPub 2016/0282609) in view of Koizumi (U.S. PGPub 2007/0029562), Sun (U.S. PGPub 2010/0213621) and Chou (U.S. PGPub 2013/0119493).
Regarding claim 3, the combination of Hanaoka and Koizumi does not explicitly teach wherein the buffer material has a lower modulus of elasticity than the encapsulant.
Hanaoka and Koizumi teach where the buffer layer prevents moisture from entering the device (Hanaoka, [0010]; Koizumi, [0048]).
Sun teaches a buffer material laterally surrounding a device package which blocks moisture from entering the device, wherein the buffer material comprises silicone ([0017], Fig. 2).
Chou teaches a MEMS device, a buffer material surrounding the MEMS device, an encapsulant which is separated from the MEMS device by the buffer material, wherein the buffer material is silicone and has a lower modulus of elasticity than the encapsulant (Fig. 1D, 200, 203, 300, [0014]-[0015]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Chou and Sun with Hanaoka and Koizumi such that the buffer material has a lower modulus of elasticity than the encapsulant for the purpose of providing a buffer layer which provides moisture protection and acts as a stress buffer (Sun, [0017]; Chou, [0015]).
Regarding claim 7, the combination of Hanaoka and Koizumi does not explicitly teach wherein the buffer material comprises silicone.
Hanaoka and Koizumi teach where the buffer layer prevents moisture from entering the device (Hanaoka, [0010]; Koizumi, [0048]).
Sun teaches a buffer material laterally surrounding a device package which blocks moisture from entering the device, wherein the buffer material comprises silicone ([0017], Fig. 2).
Chou teaches a MEMS device, a buffer material surrounding the MEMS device, an encapsulant which is separated from the MEMS device by the buffer material, wherein the buffer material is silicone and has a lower modulus of elasticity than the encapsulant (Fig. 1D, 200, 203, 300, [0014]-[0015]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Chou and Sun with Hanaoka and Koizumi such that the buffer material comprises silicone for the purpose of providing a buffer layer which provides moisture protection and acts as a stress buffer (Sun, [0017]; Chou, [0015]).
Regarding claim 17, the combination of Hanaoka and Koizumi does not explicitly teach wherein the shape of an outer surface of the buffer material is different than a shape profile of the side of the layers of materials opposite the open space.
Hanaoka and Koizumi teach where the buffer layer prevents moisture from entering the device (Hanaoka, [0010]; Koizumi, [0048]).
Sun teaches a buffer material laterally surrounding a device package which blocks moisture from entering the device, wherein the buffer material comprises silicone ([0017], Fig. 2).
Chou teaches a MEMS device, a buffer material surrounding the MEMS device, an encapsulant which is separated from the MEMS device by the buffer material, wherein the buffer material is silicone and has a lower modulus of elasticity than the encapsulant, wherein a shape of an outer surface of the buffer material is different than a shape profile of the side of the layers of materials opposite the open space (Fig. 1D, 200, 203, 300, [0014]-[0015]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Chou and Sun with Hanaoka and Koizumi such that the shape of an outer surface of the buffer material is different than a shape profile of the side of the layers of materials opposite the open space for the purpose of providing a buffer layer which provides moisture protection and acts as a stress buffer (Sun, [0017]; Chou, [0015]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Hanaoka (U.S. PGPub 2016/0282609) in view of Koizumi (U.S. PGPub 2007/0029562) and Su (U.S. PGPub 2015/0210538).
Regarding claim 4, the combination of Hanaoka and Koizumi teaches wherein the semiconductor substrate is mounted to a support surface (Hanaoka, Fig. 4B) but does not explicitly teach the buffer material extending farther away from the support surface than the encapsulant extends away from the support surface.
Su teaches a semiconductor substrate bonded to a transparent panel by a bonding material, a buffer layer surrounding the bonding material (Fig. 2, 110, 130, 140, 150, [0027]-[0029]), the semiconductor substrate mounted to a support surface in a cavity of a package substrate, and an encapsulant separated from the bonded substrate and panel by the buffer layer, wherein the buffer material extending farther away from the support surface than the encapsulant extends away from the support surface (Fig. 4, 360, 390, [0036]-[0037]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Su with Hanaoka and Koizumi such that the buffer material extends farther away from the support surface than the encapsulant extends away from the support surface because the prior art teaches every element, a person of ordinary skill could have combined them as claimed and in combination each element performs the same function as it does separately, and the combination would have yielded predictable results to one of ordinary skill in the art before the time of the invention. See MPEP 2143(I)A.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Hanaoka (U.S. PGPub 2016/0282609) in view of Koizumi (U.S. PGPub 2007/0029562) and Liu (U.S. PGPub 2010/0110527).
Regarding claim 15, the combination of Hanaoka and Koizumi does not explicitly teach wherein the encapsulant fills the cavity.
Liu teaches a micromirror device bonded to a window in a cavity of a package substrate, where the bonded device and window is surrounded by an encapsulant which fills the cavity (Fig. 1A, 105, 130, 115, [0015]-[0016], [0024]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Liu with Hanaoka and Koizumi such that the encapsulant fills the cavity for the purpose of improving heat dissipation from the window (Liu, [0016]-[0017]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ALIA SABUR/Primary Examiner, Art Unit 2812