DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-3, 6-10 and 12-20 have been considered but are moot on grounds of new rejection.
Applicant's arguments filed January 2, 2026 have been fully considered but they are not persuasive. Applicant argues that Choi as modified by Kang, Chen and Yim does not disclose “a second semiconductor chip... including a substrate... connection posts connected to the rear pads of the first semiconductor chip; and an underfill resin surrounding the connection posts between the first semiconductor chip and the redistribution structure...wherein the substrate has a thermal conductivity higher than the thermal conductivity of the underfill resin.” The Examiner respectfully disagrees. Chen (Figs. 1-10 and associated text) discloses a second semiconductor chip (item 200) including a substrate (item 202, paragraphs 28, 34). Examiner notes that Chen discloses the same materials (silicon, germanium and/or a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, gallium nitride or indium phosphide, paragraphs 28, 34) for the substrate as the Applicant.
Yim (Fig. 1 and associated text) discloses connection posts (item 141) connected to the rear pads (item 131) of the first semiconductor chip (item 131); and an underfill resin (item 143, paragraph 34) surrounding the connection posts (item 141) between the first semiconductor chip (item 130) and the redistribution structure (item 101). Examiner notes that Yim discloses the same material (epoxy resin, paragraph 34) for the underfill resin as the Applicant.
Therefore, since Chen discloses the same materials (silicon, germanium and/or a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, gallium nitride or indium phosphide) for the substrate as the Applicant, and Yim discloses the same material (epoxy resin, paragraph 34) for the underfill resin as the Applicant, Choi as modified by Kang, Chen and Yim discloses wherein the substrate (item 202, Chen) has a thermal conductivity higher than the thermal conductivity of the underfill resin (item 143, epoxy resin, Yim). Examiner takes the position that Choi as modified by Kang, Chen and Yim share the same materials for the substrate and underfill resin as the Applicant, and would also share the same intrinsic characteristics in regards to the thermal conductivity of the two. This has been reiterated below in the following action on the merits.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 6-10, 12-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHOI (US 2021/0050326 A1) as evidenced by Kang et al. (Kang) (US 2019/0371731 A1) in view of Chen et al. (Chen) (US 2020/0411445 A1) in view of YIM et al. (YIM) (US 2022/0189835 A1).
In regards to claim 1, CHOI (Figs. 5-7, 15, 16, 19 and associated text) discloses a semiconductor package (Figs. 5-7,15,16, 19) comprising: a first semiconductor chip (item 200) including rear pads (item 240), front pads (item 210), and through-electrodes (item 220) electrically connecting the rear pads (item 240) and the front pads (item 210); a second semiconductor chip (item 400) on the first semiconductor chip (item 200) and including first connection pads (item 410) electrically connected to the front pads (item 210) of the first semiconductor chip (item 200) and second connection pads (outermost item 410) around the first connection pads (item 410), wherein a width of the second semiconductor chip (item 400) is greater than a width of the first semiconductor chip (item 200); a redistribution structure (item 100R) below the first semiconductor chip (item 200) and including first redistribution layers (upper patterns of item 150) electrically connected to the rear pads (item 240) of the first semiconductor chip (item 200) and second redistribution layers (lower patterns of item 150) around the first redistribution layers (upper patterns of item150); and metal posts (item 300) around the first semiconductor chip (item 200), extending between the redistribution structure (item 100R) and the second semiconductor chip (item 400), and electrically connecting the second connection pads (outermost item 410) of the second semiconductor chip (item 400) and the second redistribution layers (lower patterns of item 150) of the redistribution structure (item 100R), wherein the metal posts (item 300) include a first metal post (item 300) and a second metal post (item 300), wherein the first metal post (item 300) is disposed more closely to the first semiconductor chip than the second metal post (item 300). Examiner notes that it is well known in the art the redistribution structures can be single or multi-layered structures.
As evidenced by Kang (Fig. 9), redistribution structures (item 145) can have multiple layers (items 145a, 145b).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate various teachings/features from the multiple embodiments of CHOI for purpose of design choice.
CHOI as evidenced and/or modified by Kang does not specifically disclose a second semiconductor chip including a substrate, wherein the first metal post includes a first portion and a second portion disposed on the first portion, wherein the first portion has a first width, and wherein the second portion has a second width greater than the first width.
Chen (Figs. 1-10 and associated text) discloses a second semiconductor chip (item 200) including a substrate (item 202, paragraphs 28, 34), wherein the first metal post (item 310) includes a first portion (item 314) and a second portion (item 312) disposed on the first portion (item 314), wherein the first portion (item 314) has a first width (item W2), and wherein the second portion (item 312) has a second width (item W1) greater than the first width (item W2). Examiner notes that Chen discloses the same materials (silicon, germanium and/or a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, gallium nitride or indium phosphide) for the substrate as the Applicant.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chen for the purpose of an electrical connection.
It would have been obvious to modify the invention to include a metal post with a first portion having a first width, and a second portion having a second width greater than the first width, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
Choi as modified by Kang and Chen does not specifically disclose connection posts connected to the rear pads (item 240, Choi) of the first semiconductor chip (item 200, Choi); and an underfill resin surrounding the connection posts between the first semiconductor chip and the redistribution structure.
Yim (Fig. 1 and associated text) discloses connection posts (item 141) connected to the rear pads (item 131) of the first semiconductor chip (item 131); and an underfill resin (item 143, paragraph 34) surrounding the connection posts (item 141) between the first semiconductor chip (item 130) and the redistribution structure (item 101). Examiner notes that Yim discloses the same material (epoxy resin, paragraph 34) for the underfill resin as the Applicant.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Yim for the purpose of an electrical connection and protection, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
Examiner notes that since Chen discloses the same materials (silicon, germanium and/or a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, gallium nitride or indium phosphide) for the substrate as the Applicant, and Yim discloses the same material (epoxy resin, paragraph 34) for the underfill resin as the Applicant, Choi as modified by Kang, Chen and Yim discloses wherein the substrate (item 202, Chen) has a thermal conductivity higher than the thermal conductivity of the underfill resin (item 143, epoxy resin, Yim).
In regards to claim 2, CHOI (Figs. 5-7, 15, 16, 19 and associated text) as evidenced by Kang and modified by Chen (Figs. 1-10 and associated text) discloses wherein the second portion (item 312, Chen) of the first metal post (item 300, CHOI, item 310, Chen) contacts one of the second connection pads (outermost item 410, CHOI) of the second semiconductor chip (item 400, CHOI).
In regards to claim 3, CHOI (Figs. 3, 5-7, 15, 16, 19 and associated text) as evidenced by Kang and modified by Chen (Figs. 1-10 and associated text) discloses bump structures (item 310, CHOI) between the front pads (item 210, CHOI) of the first semiconductor chip (item 200, CHOI) and the first connection pads (item 410, CHOI) of the second semiconductor chip (item 400, CHOI); and an adhesive film (item 370, Fig. 3, CHOI) surrounding the bump structures ((item 310, CHOI) between the first semiconductor chip (item 200, CHOI) and the second semiconductor chip (item 400,CHOI), wherein the second portion (item 312, Chen) of the first metal post (item 310, Chen) overlaps the adhesive film (item 370, Fig. 3, CHOI) in a horizontal direction.
In regards to claim 6, CHOI (Figs. 3, 5-7, 15, 16, 19 and associated text) as evidenced by Kang and modified by Chen (Figs. 1-10 and associated text) discloses wherein the first portion (item 314) of the first metal post (item 310) has a first height, and the second portion (item 312) of the first metal post (item 310) has a second height less than the first height.
In regards to claim 7, CHOI (Figs. 3, 5-7, 15, 16, 19 and associated text) as evidenced by Kang and modified by Chen (Figs. 1-10 and associated text) discloses wherein the second height is greater than a distance between the first semiconductor chip (item 200) and the second semiconductor chip (item 400).
In regards to claim 8, CHOI (Figs. 3, 5-7, 15, 16, 19 and associated text) as evidenced by Kang and modified by Chen (Figs. 1-10 and associated text) and Yim does not specifically disclose wherein the first height ranges from between about 2 times to about 4 times the second height.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a second height ranging from between about 2 times to about 4 times the first height, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 9, CHOI (Figs. 3, 5-7, 15, 16, 19 and associated text) as evidenced by Kang and modified by Chen (Figs. 1-10 and associated text) discloses wherein the second width (item W1, Chen) ranges from between about 1.1 times to about 2 times the first width (item W2, paragraph 40, Chen).
In regards to claim 10, CHOI (Figs. 3, 5-7, 15, 16, 19 and associated text) discloses wherein the metal posts (item 300) at least partially overlap the second semiconductor chip (item 400) in a vertical direction.
In regards to claim 12, CHOI (Figs. 3, 5-7, 15, 16, 19 and associated text) as evidenced by Kang and modified by Chen (Figs. 1-10 and associated text) discloses a semiconductor package comprising: a first semiconductor chip (item 200) including rear pads (item 240), front pads (item 210), and through-electrodes (item 220) electrically connecting the rear pads (item 240) and the front pads (item 210); a second semiconductor chip (item 400) on the first semiconductor chip (item 200) and including as substrate (item 202, Chen, paragraphs 28, 34), first connection pads (item 410) electrically connected to the front pads (item 210) of the first semiconductor chip (item 200) and second connection pads (outermost item 410) around the first connection pads (item 410), wherein a width of the second semiconductor chip (item 400) is greater than a width of the first semiconductor chip (item 200); a redistribution structure (item 100R) below the first semiconductor chip (item 200) and including first redistribution layers (upper patterns of item 150) electrically connected to the rear pads (item 240) of the first semiconductor chip (item 200) and second redistribution layers (lower patterns of item 150) around the first redistribution layers (upper patterns of item150); and metal posts (item 300) around the first semiconductor chip (item 200), extending between the redistribution structure (item 100R) and the second semiconductor chip (item 400), and electrically connecting the second connection pads (outermost item 410) of the second semiconductor chip (item 400) and the second redistribution layers (lower patterns of item 150) of the redistribution structure (item 100R), wherein the metal posts (item 300, CHOI, item 310, Chen) include an arrangement of first metal posts (item 300, CHOI, innermost item 310, Chen) spaced apart around the first semiconductor chip (item 200, CHOI, item 200, Chen) and an arrangement of second metal posts (middle or outermost item 310, Chen) spaced apart around the arrangement of first metal posts (item 300, CHOI, innermost item 310, Chen), and wherein each of the first metal posts (item 300, CHOI, innermost item 310, Chen) includes a portion having a width (item W1, Chen) greater than a width (item W2, Chen) of each of the second metal posts (item 300, CHOI, item 310, Chen, paragraph 40).
As evidenced by Kang (Fig. 9), redistribution structures (item 145) can have multiple layers (items 145a, 145b).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate various teachings/features from the multiple embodiments of CHOI for purpose of design choice.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chen for the purpose of an electrical connection.
Choi as modified by Kang and Chen does not specifically disclose connection posts connected to the rear pads (item 240, Choi) of the first semiconductor chip (item 200, Choi); and an underfill resin surrounding the connection posts between the first semiconductor chip and the redistribution structure.
Yim (Fig. 1 and associated text) discloses connection posts (item 141) connected to the rear pads (item 131) of the first semiconductor chip (item 131); and an underfill resin (item 143, paragraph 34) surrounding the connection posts (item 141) between the first semiconductor chip (item 130) and the redistribution structure (item 101). Examiner notes that Yim discloses the same material (epoxy resin, paragraph 34) for the underfill resin as the Applicant.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Yim for the purpose of an electrical connection and protection, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
Examiner notes that since Chen discloses the same materials (silicon, germanium and/or a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, gallium nitride or indium phosphide) for the substrate as the Applicant, and Yim discloses the same material (epoxy resin, paragraph 34) for the underfill resin as the Applicant, Choi as modified by Kang, Chen and Yim discloses wherein the substrate (item 202, Chen) has a thermal conductivity higher than the thermal conductivity of the underfill resin (item 143, epoxy resin, Yim).
In regards to claim 13, CHOI (Figs. 3, 5-7, 15, 16, 19 and associated text) as evidenced by Kang and modified by Chen (Figs. 1-10 and associated text) discloses wherein upper surfaces of the first metal posts (item 300, CHOI, item 310, Chen) have a first width (items W1 or W2, Chen), and upper surfaces of the second metal posts (item 300, CHOI, item 310, Chen) have a second width (items W1 or W2, Chen) less than the first width (paragraph 40, Chen). Examiner notes that Chen discloses different widths/thicknesses and/or same thickness.
In regards to claim 14, CHOI (Figs. 3, 5-7, 15, 16, 19 and associated text) as evidenced by Kang and modified by Chen (Figs. 1-10 and associated text) discloses wherein each of the first metal posts (item 300, CHOI, item 310, Chen) includes a first portion (item 314, Chen) and a second portion (item 312, Chen) disposed on the first portion (item 314, Chen), the first portion (item 314, Chen) has a first width (item W2, Chen), and the second portion (item 312, Chen) has a second width (item W1, Chen) greater than the first width (item W2, Chen).
In regards to claim 15, CHOI (Figs. 3, 5-7, 15, 16, 19 and associated text) as evidenced by Kang and modified by Chen (Figs. 1-10 and associated text) discloses wherein the second portion (item 312, Chen) contacts one of the second connection pads (item 410, CHOI) of the second semiconductor chip (item 400, CHOI).
In regards to claim 16, CHOI (Figs. 3, 5-7, 15, 16, 19 and associated text) as evidenced by Kang and modified by Chen (Figs. 1-10 and associated text) discloses wherein the first width (item W2, Chen) ranges from between about 40 μm to about 50 μm, and the second width (item W1, Chen) ranges from between about 60 μm to about 75 μm (paragraph 40, Chen).
In regards to claim 17, CHOI (Figs. 3, 5-7, 15, 16, 19 and associated text) as evidenced by Kang and modified by Chen (Figs. 1-10 and associated text) discloses bump structures (item 310, CHOI) between the front pads (item 210, CHOI) of the first semiconductor chip (item 200, CHOI) and the first connection pads (item 410, CHOI) of the second semiconductor chip (item 400, CHOI); and an adhesive film (item 370, Fig. 3, CHOI) surrounding the bump structures ((item 310, CHOI) between the first semiconductor chip (item 200, CHOI) and the second semiconductor chip (item 400,CHOI).
In regards to claim 18, CHOI (Figs. 3, 5-7, 15, 16, 19 and associated text) as evidenced by Kang and modified by Chen (Figs. 1-10 and associated text) discloses a first semiconductor chip (item 200) including rear pads (item 240), front pads (item 210), and through-electrodes (item 220) electrically connecting the rear pads (item 240) and the front pads (item 210); a second semiconductor chip (item 400) on the first semiconductor chip (item 200) and including a substrate (item 202, Chen, paragraphs 28, 34), first connection pads (item 410) electrically connected to the front pads (item 210) of the first semiconductor chip (item 200) and second connection pads (outermost item 410) around the first connection pads (item 410), wherein a width of the second semiconductor chip (item 400) is greater than a width of the first semiconductor chip (item 200); a redistribution structure (item 100R) below the first semiconductor chip (item 200) and including first redistribution layers (upper patterns of item 150) electrically connected to the rear pads (item 240) of the first semiconductor chip (item 200) and second redistribution layers (lower patterns of item 150) around the first redistribution layers (upper patterns of item150); and metal posts (item 300) around the first semiconductor chip (item 200), extending between the redistribution structure (item 100R) and the second semiconductor chip (item 400), and electrically connecting the second connection pads (outermost item 410) of the second semiconductor chip (item 400) and the second redistribution layers (lower patterns of item 150) of the redistribution structure (item 100R), wherein the metal posts (item 300) include a first metal post (item 300, CHOI, innermost item 310, Chen) and a second metal post (item 300, CHOI, middle or outermost item 310, Chen), the first metal post (item 300, CHOI, innermost item 310, Chen) is disposed more closely to the first semiconductor chip (item 200, CHOI, item 200, Chen) than the second metal post (item 300), and at least one second metal post (item 300, CHOI, middle or outermost item 310, Chen) more distantly disposed in relation to the first semiconductor chip (item 200, CHOI, item 200, Chen), wherein the at least one first metal post (item 300, CHOI, innermost item 310, Chen) includes a first portion (item 314, Chen) and a second portion (item 312, Chen) on the first portion, and wherein a distance between the first portion (item 314, Chen) of the first metal post (item 310, Chen) and a side surface of the first semiconductor chip (item 200, CHOI, item 200, Chen) is greater than a distance between the second portion (item 312, Chen) of the first metal post (item 310, Chen) and a side surface of the first semiconductor chip (item 200, CHOI, item 200, Chen).
As evidenced by Kang (Fig. 9), redistribution structures (item 145) can have multiple layers (items 145a, 145b).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate various teachings/features from the multiple embodiments of CHOI for purpose of design choice.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chen for the purpose of an electrical connection.
Choi as modified by Kang and Chen does not specifically disclose connection posts connected to the rear pads (item 240, Choi) of the first semiconductor chip (item 200, Choi); and an underfill resin surrounding the connection posts between the first semiconductor chip and the redistribution structure.
Yim (Fig. 1 and associated text) discloses connection posts (item 141) connected to the rear pads (item 131) of the first semiconductor chip (item 131); and an underfill resin (item 143, paragraph 34) surrounding the connection posts (item 141) between the first semiconductor chip (item 130) and the redistribution structure (item 101). Examiner notes that Yim discloses the same material (epoxy resin, paragraph 34) for the underfill resin as the Applicant.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Yim for the purpose of an electrical connection and protection, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
Examiner notes that since Chen discloses the same materials (silicon, germanium and/or a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, gallium nitride or indium phosphide) for the substrate as the Applicant, and Yim discloses the same material (epoxy resin, paragraph 34) for the underfill resin as the Applicant, Choi as modified by Kang, Chen and Yim discloses wherein the substrate (item 202, Chen) has a thermal conductivity higher than the thermal conductivity of the underfill resin (item 143, epoxy resin, Yim).
In regards to claim 19, CHOI (Figs. 3, 5-7, 15, 16, 19 and associated text) as evidenced by Kang and modified by Chen (Figs. 1-10 and associated text) discloses wherein the first portion (item 314, Chen) of the first metal post (innermost item 310, Chen) has a first width (item W2, Chen), and the second portion (item 312, Chen) of the first metal post (innermost item 310, Chen) has a second width (item W1, Chen) greater than the first width (item W2, Chen).
In regards to claim 20, CHOI (Figs. 3, 5-7, 15, 16, 19 and associated text) as evidenced by Kang and modified by Chen (Figs. 1-10 and associated text) discloses wherein the second portion (item 312, Chen) of the first metal post (innermost item 310, Chen) contacts one of the second connection pads (item 410, CHOI) of the second semiconductor chip (item 400, CHOI).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 January 14, 2026
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