Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/143,056 filed on December 23, 2025.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Specification
4. The title of the invention has been amended as “Shielding Circuits and Semiconductor Devices Comprising Inductor and Electronic Component”.
Claim Rejections - 35 USC § 112
5. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
6. Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
7. The amended limitation of claim 1 recites “….first shielding structure, forming a first independent closed loop….” and “a second shielding structure, forming a second independent closed loop….” which has not shown in the elected species II (Fig. 3) and where the first shielding loop 331 and the second shielding loop 332 connected to each other with a boundary in-between, rather the amended limitation discloses in species I (Fig. 2) with the first shielding loop 231 and the second shielding loop 232 with independent closed loops, therefore, the claim 1 invokes 112, first paragraph, for new matter.
8. The amended limitation of claim 11 recites “….comprising at least two shielding structures, each shielding structure forming an independent closed loop; ….” which similarly has not shown in the elected species II (Fig. 3), rather discloses in species I (Fig. 2), therefore, the claim 11 invokes 112, first paragraph, for new matter.
Claim Rejections - 35 USC § 102
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
10. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
11. Claims 1-4, 6, 8-15, 17, 19-20 are rejected under 35 U.S.C. 102(a)(1)/ (a)(2) as¶ being anticipated by Jin et al. (US 2016/0365189 A1).
Regarding independent claim 1, Jin et al. teaches a shielding circuit, applied to a semiconductor device (Fig. 5B/6), comprising:
a first shielding structure (510 lower portion) forming a first closed loop (see the annotated figure below) and disposed adjacent to an inductor (508, para [0056]) comprised in the semiconductor device (Fig. 5B); and
a second shielding structure (510 upper portion) forming a second closed loop (see the annotated figure below) and disposed adjacent to an electronic component (para [0010]) coupled to the inductor (508).
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Regarding claim 2, Jin et al. teaches wherein (Fig. 5B/6), the first shielding structure (510 lower portion) surrounds the inductor (508).
Regarding claim 3, Jin et al. teaches wherein (Fig. 5B/6), along a vertical direction, a projection (shown in figure of claim 1) of the first shielding structure (510 lower portion) on a predetermined plane (shown in figure of claim 1) surrounds a projection (see figure in claim 1) of the inductor (508) on the predetermined plane.
Regarding claim 4, Jin et al. teaches wherein (Fig. 5B/6), a projected area of the first closed loop (see the annotated figure in claim 1) on a predetermined plane is greater than a projected area of the inductor (508) on the predetermined plane.
Regarding claim 6, Jin et al. teaches wherein (Fig. 5B/6), the first shielding structure (510 lower portion) is electrically connected to the second shielding structure (510 upper portion).
Regarding claim 8, Jin et al. teaches wherein (Fig. 5B/6), the second shielding structure (510 upper portion) surrounds the electronic component (para [0057]).
Regarding claim 9, Jin et al. teaches wherein (Fig. 5B/6), along a vertical direction, a projection of the second shielding structure (510 upper portion) on a predetermined plane surrounds a projection of the electronic component (para [0057]) on the predetermined plane.
Regarding claim 10, Jin et al. teaches wherein (Fig. 5B/6), a projected area of the second closed loop (see figure in claim 1) on a predetermined plane is greater than a projected area of the electronic component on the predetermined plane.
Regarding independent claim 11, Jin et al. teaches a semiconductor device (Fig. 5B/6), comprising:
a shielding circuit (510) comprising at least two shielding structures (510 lower, 510 upper), each shielding structure (510 lower and upper) forming a closed loop (see the annotated figure below); and
an electronic component (para [0010] coupled to an inductor (508), wherein one (510 lower) of said at least two shielding structures (510 lower/upper) is disposed adjacent to the electronic component.
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Regarding claim 12, Jin et al. teaches wherein (Fig. 5B/6), the shielding circuit (510) comprises:
a first shielding structure (510 lower portion) forming a first closed loop (see the annotated figure in claim 11) and disposed adjacent to the inductor (508); and
a second shielding structure (510 upper portion) forming a second closed loop (see the annotated figure in claim 11) and a projection of the second shielding structure on a predetermined plane along a vertical direction surrounds a projection of the electronic component on the predetermined plane.
Regarding claim 13, Jin et al. teaches wherein (Fig. 5B/6), the first shielding structure (510 lower portion) surrounds the inductor (508).
Regarding claim 14, Jin et al. teaches wherein (Fig. 5B/6), a projection of the first shielding structure (510 lower portion) on the predetermined plane surrounds a projection of the inductor (508) on the predetermined plane.
Regarding claim 15, Jin et al. teaches wherein (Fig. 5B/6), a projected area of the first closed loop (see the annotated figure in claim 1) on the predetermined plane is greater than a projected area of the inductor (508) on the predetermined plane.
Regarding claim 17, Jin et al. teaches wherein (Fig. 5B/6), the first shielding structure (510 lower portion) is electrically connected to the second shielding structure (510 upper portion).
Regarding claim 19, Jin et al. teaches wherein (Fig. 5B/6), the second shielding structure (510 upper portion) surrounds the electronic component.
Regarding claim 20, Jin et al. teaches wherein (Fig. 5B/6), a projected area of the second closed loop (see figure in claim 1) on the predetermined plane is greater than a projected area of the electronic component on the predetermined plane.
Allowable Subject Matter
12. Claims 5, 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims; if the 112 first paragraph overcome.
Claim 5 recites “wherein a projected area of the first closed loop on a predetermined plane is smaller than or equal to a projected area of the inductor on the predetermined plane”.
Claim 16 recites “wherein a projected area of the first closed loop on the predetermined plane is smaller than or equal to a projected area of the inductor on the predetermined plane”.
The cited prior art, Jin et al. (US 2016/0365189 A1), by itself or in combination or with other prior arts do not disclose the quoted limitations as stated in the section 12.
Response to Arguments
13. It has been acknowledged that the applicant amended claims 1, 11-12, per the response dated on 12/23/2025.
Applicant’s arguments in pages 7-8 of the remarks section, with respect to the amended limitations have been reviewed, however, the amended limitations of claims 1, 11 invoked 112, first paragraph, for new matter issues as explained above.
Conclusion
14. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
15. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
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16. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812