DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/05/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US. Pat: 9,331,200 B1~ hereinafter “Wang”) of record in view of Kuang et al. (US. Pat: 10,084,063 B2~ hereinafter “Kuang”) of record.
Regarding claim 1, Wang discloses (in at least figs. 3 and 4) a method for fabricating a semiconductor device (see figs. 3 and 4), comprising: forming a gate structure (14) on a substrate (12); forming a first epitaxial layer (28) adjacent to the gate structure, wherein the first epitaxial layer (28) comprises a first protrusion (see figs. 3 and 4); and forming a second epitaxial layer (30) on the first epitaxial layer (28).
Wang does not expressly disclose a bottom surface of the first epitaxial layer comprises a V-shape pointing directly downward, and the first epitaxial layer comprises: a neck portion above a top surface of the substrate; and a top portion above the neck portion, wherein a width of the neck portion is greater than width of the top portion.
However, Wang discloses (in at least figs. 1-4) a first epitaxial layer (28) has a flat bottom surface.
Kuang in the same field of fabricating a semiconductor device discloses (in at least fig. 1) a bottom surface of the first epitaxial layer (52; col. 4, lines 59-60) comprises a V-shape (col. 4, lines 65-67) pointing directly downward (see at least fig. 1), and the first epitaxial layer (52) comprises: a neck portion (see at least fig. 1) above a top surface of the substrate (10); and a top portion above the neck portion (see at least fig. 1) for the benefit of providing a semiconductor device with a more efficient electrical performance (col. 1, lines 5-8).
Kuang does not expressly disclose a width of the neck portion is greater than a width of the top portion.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device method of Wang with the V-shape and neck teachings of Kuang, wherein a width of the neck portion is greater than a width of the top portion for the benefit of providing a semiconductor device with a more efficient electrical performance (col. 1, lines 5-8).
Also, one of ordinary skill in the art would have been led to the recited V-shape bottom surface and neck width through design choice. Applicant has not disclosed that the recited V-shape bottom and neck width are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that process would possess utility using the V-shape first epitaxial layer flat bottom surface and neck width of Wang as modified by Kuang.
Regarding claim 2, Wang discloses (in at least figs. 1-4) forming a fin-shaped structure on the substrate (col. 2, lines 38-40); forming the gate structure (14); removing the fin-shaped structure to form a recess (i.e. the recess is formed on the side of item 12; see fig. 2); forming the first epitaxial layer (28) in the recess (see figs. 3 and 4).
Regarding claims 3-4 and 12, Wang discloses (in at least figs. 1-4) forming the first protrusion (i.e. the protrusion is formed on the recess portion of item 12) on one side of the first epitaxial layer (28); but is silent about forming a second protrusion on another side of the first epitaxial layer; wherein forming the first protrusion and the second protrusion at the same time.
One of ordinary skill in the art would have been led to the recited second protrusion through design choice. Applicant has not disclosed that the recited protrusion is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, and it appears prima facie that the process would possess utility using epitaxial layer arrangement of Wang. Also, one of ordinary skill in the art would consider forming the first protrusion and the second protrusion at the same time for the benefit of reducing the manufacturing steps.
Regarding claim 5, Wang discloses (in at least figs. 3 and 4) a sidewall of the first protrusion comprises a curve.
Regarding claims 6 and 14, Wang does not expressly disclose a sidewall of the first protrusion comprises a V-shape.
However, Wang discloses (in at least figs. 3 and 4) a protrusion is formed on one side of the first epitaxial layer (28).
One of ordinary skill in the art would have been led to the recited V-shape protrusion through design choice. Applicant has not disclosed that the recited V-shape is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, and it appears prima facie that the process would possess utility using the protrusion shape of Wang.
Regarding claims 7 and 15, Wang does not expressly disclose a bottom surface of the second epitaxial layer comprises a V-shape. See the reasoning of claims 6 and 4 above.
Regarding claim 8, Wang discloses (in at least figs. 1-4) the first epitaxial layer (28) and the second epitaxial layer (30) comprise same material (col. 2, lines 54-62; col. 3, lines 2-4).
Regarding claims 9 and 17,Wang does not expressly disclose the first epitaxial layer and the second epitaxial layer comprise same concentration.
However, Wang discloses (in at least col. 2, lines 56-67) “ In this embodiment, the first epitaxial layer 28, the second epitaxial layer 30, and the third epitaxial layer 32 all includes SiGeSn alloy or compounds, in which the content of Ge and Sn in the second epitaxial layer 30 is preferably higher than the content of Ge and Sn in the first epitaxial layer 28 and third epitaxial layer 32. More specifically, the content of Ge and Sn in the first epitaxial layer 28 is preferably between 15-30 atomic percentage, the content of Ge and Sn in the second epitaxial layer 30 is between 50-80 atomic percentage, and the content of Ge and Sn in the third epitaxial layer 32 is between 15-30 atomic percentage.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to consider forming the first epitaxial layer and the second epitaxial layer with the same concentration for the benefit of reducing the manufacturing steps.
Regarding claim 10, Wang discloses (in at least figs. 3 and 4) a semiconductor device, comprising: a gate structure (14) on a substrate; a first epitaxial layer (28) adjacent to the gate structure, wherein the first epitaxial layer (28) comprises a first protrusion (see figs. 3 and 4); and a second epitaxial layer (30) on the first epitaxial layer.
Wang does not expressly disclose a bottom surface of the first epitaxial layer comprises a V-shape pointing directly downward, and the first epitaxial layer comprises: a neck portion above a top surface of the substrate; and a top portion above the neck portion, wherein a width of the neck portion is greater than width of the top portion.
However, Wang discloses (in at least figs. 1-4) a first epitaxial layer (28) has a flat bottom surface.
Kuang in the same field of fabricating a semiconductor device discloses (in at least fig. 1) a bottom surface of the first epitaxial layer (52; col. 4, lines 59-60) comprises a V-shape (col. 4, lines 65-67) pointing directly downward (see at least fig. 1), and the first epitaxial layer (52) comprises: a neck portion (see at least fig. 1) above a top surface of the substrate (10); and a top portion above the neck portion (see at least fig. 1) for the benefit of providing a semiconductor device with a more efficient electrical performance (col. 1, lines 5-8).
Kuang does not expressly disclose a width of the neck portion is greater than a width of the top portion.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device method of Wang with the V-shape and neck teachings of Kuang, wherein a width of the neck portion is greater than a width of the top portion for the benefit of providing a semiconductor device with a more efficient electrical performance (col. 1, lines 5-8).
Also, one of ordinary skill in the art would have been led to the recited V-shape bottom surface and neck width through design choice. Applicant has not disclosed that the recited V-shape bottom and neck width are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that process would possess utility using the V-shape first epitaxial layer flat bottom surface and neck width of Wang as modified by Kuang.
Regarding claim 11, Wang discloses (in at least figs. 1-4) a fin-shaped structure on the substrate (12); the gate structure (14) on the fin-shaped structure; and the first epitaxial layer (28) adjacent to the gate structure (14).
Regarding claim 13, Wang discloses (in at least figs. 3 and 4) a sidewall of the first protrusion comprises a curve.
Regarding claim 16, Wang discloses (in at least figs. 1-4) the first epitaxial layer (28) and the second epitaxial layer (30) comprise same material (col. 2, lines 54-62; col. 3, lines 2-4).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELMITO BREVAL whose telephone number is (571)270-3099. The examiner can normally be reached M-Th~ 7:30-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James R. Greece can be reached at 571-272-3711. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
ELMITO BREVAL
Primary Examiner
Art Unit 2875
/ELMITO BREVAL/Primary Examiner, Art Unit 2875