DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites “”wherein metal pattern is not disposed…”. It is unclear whether the “metal pattern” is the first metal pattern or second metal pattern, or an entirely different metal pattern. The Examiner has interpreted this as a different metal pattern.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 9-14, 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Becker et al. (US 2013/0126978 A1).
Regarding claim 1, Becker teaches a semiconductor device (device in Fig. 11 of Becker), comprising:
a substrate (substrate described in [0083] of Becker) including a p-channel metal-oxide-semiconductor (PMOS) region (upper region in Fig. 11, where type2 fins are p-type, as stated in [0100] of Becker), an N-well tap forming region (lower region in Fig. 11 where the type1 fins are n-type, as stated in [0100] of Becker. The S/D of the fins are connected to the lower power rail, so the lower region is a tap forming region), and a boundary region (region between the lowest upper fins and highest lower fins as shown in Fig. 11) between the PMOS region and the N-well tap forming region;
PMOS field effect transistors (a transistor in the upper active region) on the PMOS region;
an N-well tap region (the leftmost drain region of the lower n-type fins to the lower power rail in Fig. 11) doped with N-type impurities in the N-well tap forming region;
a first metal pattern (the center upper vertical local interconnect liv in Fig. 11) connected to at least one impurity region (middle S/D regions of the upper type2 fins in Fig. 11) of the PMOS field effect transistors, wherein the first metal pattern extends so that an end of the first metal pattern is positioned on the boundary region (as shown in Fig. 11);
a second metal pattern (rightmost lower vertical local interconnect liv in Fig. 11) electrically connected to the N-well tap region (the term “electrically connected” includes other electrical elements in between, such as transistors or elements of other transistors. As such, the rightmost lower liv is “electrically connected to the N-well tap region”), wherein the second metal pattern extends so that an end of the second metal pattern is positioned on the boundary region (as shown in Fig. 11);
a first contact plug (the contact co between the center upper liv to the middle interconnect met1 in Fig. 11) on the first metal pattern;
a second contact plug (the contact co between the rightmost lower liv to the middle interconnect met1 in Fig. 11) on the second metal pattern; and
an upper wiring (middle interconnect met1) on the first and second contact plugs.
Regarding claim 2, Becker teaches all limitations of the semiconductor device of claim 1, and also teaches wherein a metal pattern (portion of the center lower vertical local interconnect liv that is above and not overlap the uppermost lower type1 fin as viewed in Fig. 11 of Becker) is not disposed in an area of the N-well tap forming region (since the portion defined above is not overlapped with the type1 fin, it is not in the n-well tap forming region) that faces the first metal pattern in an extending direction (y-direction) of the first metal pattern.
Regarding claim 3, Becker teaches all limitations of the semiconductor device of claim 1, and further comprising a third metal pattern (portion of the center lower vertical local interconnect liv that overlap the lower type1 fins as viewed in Fig. 11 of Becker) disposed in an area of the N-well tap forming region (as defined) that faces the first metal pattern in an extending direction (y-direction) of the first metal pattern, wherein the third metal pattern is electrically connected to the N-well tap region (the term “electrically connected” is interpreted as in claim 1), and is spaced apart from the first metal pattern (the two center liv’s are space apart), and wherein an end of the third metal pattern extends to the boundary region (portion of the center lower vertical local interconnect liv that is above and not overlap the uppermost lower type1 fin as viewed in Fig. 11 of Becker).
Regarding claim 4, Becker teaches all limitations of the semiconductor device of claim 1, and also teaches wherein a bottom of the first contact plug includes a first portion (lower portion of the first contact co in Fig. 11 of Becker, as defined in claim 1 above) contacting the first metal pattern and a second portion (upper portion of the first contact co) not contacting the first metal pattern.
Regarding claim 5, Becker teaches all limitations of the semiconductor device of claim 1, and also teaches wherein the first contact plug extends away from the first metal pattern towards the N-well tap forming region (as shown in Fig. 11 of Becker, the first contact co extends in both x & y directions, so it does extend in the y direction toward the N-well tap forming region).
Regarding claim 6, Becker teaches all limitations of the semiconductor device of claim 1, and also teaches wherein the first metal pattern and the second metal pattern are not aligned along a line in an extending direction of the first metal pattern (as shown in Fig. 11 of Becker, the first metal pattern and second metal pattern are offset from each other).
Regarding claim 9, Becker teaches a semiconductor device (device in Fig. 11 of Becker), comprising:
a substrate (substrate described in [0083] of Becker) including a p-channel metal-oxide-semiconductor (PMOS) region (upper region in Fig. 11, where type2 fins are p-type, as stated in [0100] of Becker), an N-well tap forming region (lower region in Fig. 11 where the type1 fins are n-type, as stated in [0100] of Becker. The S/D of the fins are connected to the lower power rail, so the lower region is a tap forming region), and a boundary region (region between the lowest upper fins and highest lower fins as shown in Fig. 11) between the PMOS region and the N-well tap forming region;
first active fins (type2 fins in Fig. 11 of Becker) extending in a first direction (x-direction) on the PMOS region;
a first gate structure (second gate electrode from the left in Fig. 11 which overlaps with the upper type2 fins) on the first active fins, the first gate structure crossing the first active fins and extending in a second direction (y direction) perpendicular to the first direction, wherein an end of the first gate structure is positioned on the boundary region (as shown in Fig. 11 of Becker);
first semiconductor structures (S/D regions on the type2 fins) on the first active fins, each of the first semiconductor structures being doped with P-type impurities (as described in [0100] of Becker) and connecting the first active fins to each other;
an N-well tap region (the leftmost drain region of the lower n-type fins to the lower power rail in Fig. 11) doped with N-type impurities in the N-well tap forming region;
second active fins (lower type1 fins in Fig. 11) extending in the first direction on the N-well tap forming region;
a second gate structure (portion of the third gate electrode from the left over the lower type1 fins in Fig. 11 which overlaps with the lower type1 fins) on the second active fins, the second gate structure crossing the second active fins and extending in the second direction, wherein an end of the second gate structure is positioned on the boundary region (as defined);
second semiconductor structures (S/D regions in type1 fins) on the second active fins, each of the second semiconductor structures being doped with N-type impurities (type1 fins are n-type, as stated in [0100] of Becker) and connecting the second active fins to each other;
a first metal pattern (the center upper vertical local interconnect liv in Fig. 11) on an upper surface (top surface of S/D regions of first fins) of at least one of the first semiconductor structures, wherein an end of the first metal pattern extends to the boundary region (as shown in Fig. 11);
a second metal pattern (rightmost lower vertical local interconnect liv in Fig. 11) on an upper surface of at least one of the second semiconductor structures, wherein an end of the second metal pattern extends to the boundary region (as shown in Fig. 11);
a first contact plug (the contact co between the center upper liv to the middle interconnect met1 in Fig. 11) on the first metal pattern;
a second contact plug (the contact co between the rightmost lower liv to the middle interconnect met1 in Fig. 11) on the second metal pattern; and
an upper wiring (middle interconnect met1) on the first and second contact plugs.
Regarding claim 10, Becker teaches all limitations of the semiconductor device of claim 9, and also teaches wherein metal pattern (as interpreted in 112b rejection above. This is a portion of the center lower vertical local interconnect liv that is above and not overlap the uppermost lower type1 fin as viewed in Fig. 11 of Becker) is not disposed in an area of the N-well tap forming region (since the portion defined above is not overlapped with the type1 fin, it is not in the n-well tap forming region) that faces the first metal pattern in the second direction.
Regarding claim 11, Becker teaches all limitations of the semiconductor device of claim 9, and further comprising a third metal pattern (portion of the center lower vertical local interconnect liv that overlap the lower type1 fins as viewed in Fig. 11 of Becker) in an area of the N-well tap forming region that faces the first metal pattern in the second direction, wherein the third metal pattern is electrically connected to the N-well tap region (the term “electrically connected” is interpreted as in claim 9), and is spaced apart from the first metal pattern (the two center liv’s are space apart), and wherein an end of the third metal pattern extends to the boundary region (portion of the center lower vertical local interconnect liv that is above and not overlap the uppermost lower type1 fin as viewed in Fig. 11 of Becker).
Regarding claim 12, Becker teaches all limitations of the semiconductor device of claim 9, and also teaches wherein each of the first and second metal patterns extends in the second direction (as shown in Fig. 11 of Becker).
Regarding claim 13, Becker teaches all limitations of the semiconductor device of claim 9, and also teaches wherein the first and second metal patterns are not aligned in a line in the second direction (as shown in Fig. 11 of Becker).
Regarding claim 14, Becker teaches all limitations of the semiconductor device of claim 9, and also teaches wherein a bottom of the first contact plug includes a first portion (lower portion of the first contact co in Fig. 11 of Becker, as defined in claim 1 above) contacting the first metal pattern and a second portion (upper portion of the first contact co) not contacting the first metal pattern.
Regarding claim 17, Becker teaches all limitations of the semiconductor device of claim 9, further comprising a third contact plug (co on the 2nd gate from the left in Fig. 11 of Becker) on the first gate structure, wherein the third contact plug is electrically connected to the first gate structure.
Regarding claim 18, Becker teaches a semiconductor device (device in Fig. 11 of Becker), comprising:
a substrate (substrate described in [0083] of Becker) including a p-channel metal-oxide-semiconductor (PMOS) region (upper region in Fig. 11, where type2 fins are p-type, as stated in [0100] of Becker), an N-well tap forming region (lower region in Fig. 11 where the type1 fins are n-type, as stated in [0100] of Becker. The S/D of the fins are connected to the lower power rail, so the lower region is a tap forming region), and a boundary region (region between the lowest upper fins and highest lower fins as shown in Fig. 11) between the PMOS region and the N-well tap forming region;
first active fins (upper type2 fins) extending in a first direction (x direction) on the PMOS region;
a first gate structure (portion of the second gate from the left that overlaps with the upper type2 fins) on the first active fins, the first gate structure crossing the first active fins and extending in a second direction (y-direction) perpendicular to the first direction, wherein an end of the first gate structure is positioned on the boundary region (as shown in Fig. 11 of Becker);
first semiconductor structures (S/D regions on the type2 fins) on the first active fins, each of the first semiconductor structures being doped with P-type impurities (as described in [0100] of Becker) and connecting the first active fins to each other;
an N-well tap region (the leftmost drain region of the lower n-type fins to the lower power rail in Fig. 11) doped with N-type impurities in the N-well tap forming region;
second active fins (lower type1 fins in Fig. 11) extending in the first direction on the N-well tap forming region;
a second gate structure (portion of the third gate electrode from the left that is over the lower type1 fins in Fig. 11) on the second active fins, the second gate structure crossing the second active fins and extending in the second direction, wherein an end of the second gate structure is positioned on the boundary region (as shown in Fig. 11);
second semiconductor structures (S/D regions in type1 fins) on the second active fins, each of the second semiconductor structures being doped with N-type impurities (type1 fins are n-type, as stated in [0100] of Becker) and connecting the second active fins to each other;
a first metal pattern (the center upper vertical local interconnect liv in Fig. 11) on an upper surface (top surface of S/D regions of first fins) of at least one of the first semiconductor structures, wherein an end of the first metal pattern extends to the boundary region (as shown in Fig. 11); and
a second metal pattern (rightmost lower vertical local interconnect liv in Fig. 11) on an upper surface of at least one of the second semiconductor structures, wherein an end of the second metal pattern extends to the boundary region (as shown in Fig. 11), wherein the first and second metal patterns are not aligned in a line in the second direction (as shown in Fig. 11).
Regarding claim 19, Becker teaches all limitations of the semiconductor device of claim 18, and further comprising: a first contact plug (the contact co between the center upper liv to the middle interconnect met1 in Fig. 11) on the first metal pattern; a second contact plug (the contact co between the rightmost lower liv to the middle interconnect met1 in Fig. 11) on the second metal pattern; and an upper wiring (middle interconnect met1) on the first and second contact plugs.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Becker, as applied to claim 1 above, and further in view of Morrow et al. (US 2018/0248012 A1).
Regarding claim 7, Becker teaches all limitations of the semiconductor device of claim 1, but does not teach wherein the first and second metal patterns include tungsten.
Morrow teaches a S/D contact structure (230 in Fig. 2o of Morrow) that is made of tungsten ([0031] of Morrow, the S/D contacts can be made of other materials such as copper, cobalt,… but tungsten is preferred due to its low diffusivity and high melting temperature).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the first and second metal patterns of Becker from tungsten, as disclosed in Morrow, due to its low diffusivity and high melt temperature.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Becker, as applied to claim 1 above, and further in view of Xie et al. (US 2017/0092764 A1).
Regarding claim 8, Becker teaches all limitations of the semiconductor device of claim 1, but does not teach wherein an upper surface of the first metal pattern includes a third portion having a first height and a fourth portion having a second height different from the first height.
Xie teaches a L-shape S/D contact pattern (112 in Fig. 5 of Xie) which has a first portion (left half of 112 in Fig. 5 of Xie) of a first height (height of top surface of left half of 112) and a second portion (right half of 112) of a second height (height of top surface of right half of 112) different from the first height.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the first metal pattern having an L-shape patterns, as disclosed by Xie, in order to minimize interference/short between the gate electrode and the S/D contacts.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Becker, as applied to claim 9 above, and further in view of Lin et al. (US 2020/0006484 A1).
Regarding claim 15, Becker teaches all limitations of the semiconductor device of claim 9, but does not teach wherein the first semiconductor structure includes silicon germanium, and the second semiconductor structure includes silicon.
Lin teaches CMOS device (100 in Fig. 1-2D of Lin). The epitaxial S/D region (210 in Fig. 2D of Lin) of the p-type FET is made of SiGe doped with boron whereas the epitaxial S/D region of the n-type FET is made of Si doped with phosphorus or arsenic (see [0050] of Lin).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the first and second semiconductor structures (S/D regions) of Becker as disclosed by Lin in order to improve performance of the device.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Becker, as applied to claim 9 above, and further in view of Xie.
Regarding claim 16, Becker teaches all limitations of the semiconductor device of claim 9, but does not teach wherein an upper surface of the first metal pattern includes a third portion having a first height and a fourth portion having a second height different from the first height.
Xie teaches a L-shape S/D contact pattern (112 in Fig. 5 of Xie) which has a first portion (left half of 112 in Fig. 5 of Xie) of a first height (height of top surface of left half of 112) and a second portion (right half of 112) of a second height (height of top surface of right half of 112) different from the first height.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the first metal pattern having an L-shape patterns, as disclosed by Xie, in order to minimize interference/short between the gate electrode and the S/D contacts.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Becker, as applied to claim 18 above, and further in view of Lin.
Regarding claim 20, Becker teaches all limitations of the semiconductor device of claim 18, but does not teach wherein the first semiconductor structure includes silicon germanium, and the second semiconductor structure includes silicon.
Lin teaches CMOS device (100 in Fig. 1-2D of Lin). The epitaxial S/D region (210 in Fig. 2D of Lin) of the p-type FET is made of SiGe doped with boron whereas the epitaxial S/D region of the n-type FET is made of Si doped with phosphorus or arsenic (see [0050] of Lin).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the first and second semiconductor structures (S/D regions) of Becker as disclosed by Lin in order to improve performance of the device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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