DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot in view of new ground of rejection because of newly added limitations into currently amended claims. Response to the amendment is as below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
5. Claim(s) 1, 8, 14 and 20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Jeong et al. (US2011/0142232)(hereafter Jeong).
Regarding claims 1, 8, 14 and 20, Jeong discloses a method, comprising:
generating a descrambling sequence (see, Fig. 5, descrambling, 550) derived from one or more many-to-one Linear Feedback Shift Registers (LFSRs) (see, Fig. 5, multiple LFSR group combined into one to generate the sequence output) based, at least in part, on two or more threads of one or more parallel processing units (PPUs) (see, Fig. 5, the parallel processing units in LFSR group as shown) operating on two or more one-to-many LFSRs (see, Fig. 5, the see, clock output to multiple LFSR groups in parallel which is one to many LFSRs) that are advanced through a number of cycles that differ across the two or more threads (see, Fig. 5, different time shifted loading vectors which is interpreted as advanced through number of cycles across different threads as multiple parallel LFSR groups are generated with the different descrambling sequence using time shifted loading vectors).
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
7. Claim(s) 2, 6, 9, 11, 16,18, 19, 21, 22, 24 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong in view of Li.
Regarding claims 2 and 16, Jeong does not disclose the method, wherein the descrambling sequence is a pseudorandom bit sequence that is a function of a user identifier of a user device having transmitted an input data sequence and of a base station identifier of a base station having received the input data sequence However, in same field of endeavor, Li teaches this limitations, see, pages 1920-1921, para 6.1, both the scrambler and descrambler XOR each input bit with a pseudo-random binary sequence to randomize the input bit stream. The scrambler XORs the 1st input bit with the 4st and 7th bits of the LFSR to obtain the output bit. The new LFSR is computed by shifting the feedback bit of the LFSR in the right direction). Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to combine the teachings of Li with the Jeong, as a whole, so as to generate the descrambling sequence as claimed, the motivation is to yield predictable results.
Regarding claim 6, the combined teachings further disclose the method, wherein a graphics processing unit (GPU) comprising the one or more PPUs is an element of a cellular network base station (see, Jeong, Fig. 6, multiple LFST in parallel, Li, pages 1912-1915, para [0001], introduction, GPU based wireless communication has increased, see, Fig. 5, the see, clock output to multiple LFSR groups in parallel which is one to many LFSRs).
Regarding claim 9, Li further teaches the processor, wherein the one or more circuits are to generate the descrambling sequence using linear feedback shift registers (LFSRs) (see, 6.1, Both the scrambler and descrambler XOR each input bit with a pseudo-random binary sequence to randomize the input bit stream. Linear feedback shift registers (LFSR) defined by the linear function serially generates the pseudo-random binary sequence (Table 4)).
Regarding claim 11, Li further teaches the processor, wherein the one or more circuits are to use the descrambling sequence by XOR-ing an output of a first linear feedback shift register (LFSR) and an output of a second linear feedback shift register (LFSR). (See, 6.1, Both the scrambler and descrambler XOR each input bit with a pseudo-random binary sequence to randomize the input bit stream. Linear feedback shift registers (LFSR) defined by the linear function serially generates the pseudo-random binary sequence (Table 4)).
Regarding claim 18, Li further teaches the computer readable medium wherein the set of instructions which if performed by the one or more processors, cause the one or more processors to allocate the two or more threads to generate the descrambling sequence (page-1920-1921, 6.1, both the scrambler and descrambler XOR each input bit with a pseudo-random binary sequence to randomize the input bit stream. The scrambler XORs the 1st input bit with the 4 and 7" bits of the LFSR to obtain the output bit. The new LFSR is computed by shifting the feedback bit of the LFSR in the right direction).
Regarding claim 19, Li further teaches the computer readable medium, wherein the set of instructions which if performed by the one or more processors, cause the one or more processors to allocate the two or more threads to generate the descrambling sequence based on a size in bits of the descrambling sequence, a data width of the allocated two or more threads, and/or a number of allocated threads being sufficient to generate in parallel the bits of the descrambling sequence. (Pages 1920-1921, 6.1, both the scrambler and descrambler XOR each input bit with a pseudo-random binary sequence to randomize the input bit stream. The scrambler XORs the 1st input bit with the 4 and 7" bits of the LFSR to obtain the output bit. The new LFSR is computed by shifting the feedback bit of the LFSR in the right direction).
Regarding claim 21, Li further teaches the system, wherein the generated descrambling sequence comprises a sequence of bits to be used in XOR to descramble input data (see, 6.1, scrambler, Both the scrambler and descrambler XOR each input bit with a pseudo-random binary sequence to randomize the input bit stream. Linear feedback shift registers (LFSR) defined by the linear function serially generates the pseudo-random binary sequence.
Regarding claim 22, LI further teaches the system, wherein the one or more processors are to cause each thread of a graphics processing unit (GPU) to calculate a different set of bits of the descrambling sequence (6.1, For the purpose to map the (de)scrambler to the GPUs, we present truncated (de)scrambler to touch the aim. The input bit stream of scrambler is divided into multiple chunks, each of which can process a short scramble operation. With regard to the descrambler, the same partition is applied to recover the bit stream. The length of each chunk is set as the length of LFSR, and labeled as L. Each thread requires L registers).
Regarding claim 24, Li further teaches the system, wherein the two or more threads are a part of a graphics processing unit (GPU) of a software-defined radio access network (RAN) interface (see, I. Introduction, SDR).
Regarding claim 25, Li further teaches the system, wherein the descrambling sequence is a pseudorandom bit sequence that is a function of a user identifier of a user device having transmitted an input data sequence and of a base station identifier of a base station having received the input data sequence (see, pages 1920-1921, para 6.1, both the scrambler and descrambler XOR each input bit with a pseudo-random binary sequence to randomize the input bit stream. The scrambler XORs the 1st input bit with the 4th and 7th bits of the LFSR to obtain the output bit. The new LFSR is computed by shifting the feedback bit of the LFSR in the right direction).
7. Claim(s) 10, 12, 13 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong in view of Lablans (US2010/0299579) (hereafter Lablans) (see IDS).
Regarding claim 10, Jeong discloses in Fig. 5, the LFSR registers and plurality of processing units (see Fig. 5), but does not disclose the processor, wherein descrambling sequence is defined by a generator polynomial and a Fibonacci linear feedback shift register (LFSR), wherein the one or more circuits are to generate the descrambling sequence using a plurality of threads of a graphics processing unit (GPU) by operating each thread of the plurality of threads to generate a descrambling segment of the descrambling sequence. However, in same field of endeavor, Lablans teaches in sending a sequence of binary or n-valued symbols one may want to repeat the sequence to detect errors. By scrambling one or both sequences one may also be able to correct errors. The standard convolutional coders are LFSR based descramblers in Fibonacci configuration. Para [0009], a method is provided for decoding with a processor a first coded sequence of p n-state symbols with p and n being integers greater or equal to 2, comprising generating the first coded sequence from an uncoded sequence of p n-state symbols by a first coder equivalent to a first n-state descrambler with a first n-state Linear Feedback Shift Register (LFSR) in Galois configuration having k shift register elements with k being an integer greater than 1, determining a start state of a shift register of a first decoder corresponding to the first coder by processing at least k symbols of the first coded sequence and at least k symbols of a second sequence related to the uncoded sequence, and decoding the first coded sequence into a first decoded sequence with the first decoder by applying the start state. Para [0092], one can use a convolutional coder in Galois configuration, using at least two coders with k shift register elements; restarting correct decoding and error correcting at least p symbols if at least one LFSR has its first tap after p shift register elements, wherein the most left shift register element is the first one. It should be clear that one may express these conditions in a polynomial form. Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to combine the teachings of Lablans with the Jeong, as a whole, so as to generate descrambling sequence defined by a generator polynomial and a Fibonacci linear feedback shift register (LFSR), the motivation is to yield predictable results.
Regarding claim 12, the combined teachings further disclose the processor of claim 8, wherein the one or more circuits are to perform the descrambling sequence using the two or more threads using a bitwise XOR on a first Fibonacci linear feedback shift register (LFSR) output and a second Fibonacci linear feedback shift register (LFSR) output (see, Lablans teaches in sending a sequence of binary or n-valued symbols one may want to repeat the sequence to detect errors. By scrambling one or both sequences one may also be able to correct errors. The standard convolutional coders are LFSR based descramblers in Fibonacci configuration. Para [0009], a method is provided for decoding with a processor a first coded sequence of p n-state symbols with p and n being integers greater or equal to 2, comprising generating the first coded sequence from an uncoded sequence of p n-state symbols by a first coder equivalent to a first n-state descrambler with a first n-state Linear Feedback Shift Register (LFSR) in Galois configuration having k shift register elements with k being an integer greater than 1, determining a start state of a shift register of a first decoder corresponding to the first coder by processing at least k symbols of the first coded sequence and at least k symbols of a second sequence related to the uncoded sequence, and decoding the first coded sequence into a first decoded sequence with the first decoder by applying the start state. Para [0092], one can use a convolutional coder in Galois configuration, using at least two coders with k shift register elements; restarting correct decoding and error correcting at least p symbols if at least one LFSR has its first tap after p shift register elements, wherein the most left shift register element is the first one. It should be clear that one may express these conditions in a polynomial form).
Regarding claim 13, the combined teachings further disclose the processor of claim 8, wherein the one or more circuits are to perform cycle advancement for linear feedback shift registers (LFSRs) (se, Lablans, teaches in sending a sequence of binary or n-valued symbols one may want to repeat the sequence to detect errors. By scrambling one or both sequences one may also be able to correct errors. The standard convolutional coders are LFSR based descramblers in Fibonacci configuration. Para [0009], a method is provided for decoding with a processor a first coded sequence of p n-state symbols with p and n being integers greater or equal to 2, comprising generating the first coded sequence from an uncoded sequence of p n-state symbols by a first coder equivalent to a first n-state descrambler with a first n-state Linear Feedback Shift Register (LFSR) in Galois configuration having k shift register elements with k being an integer greater than 1, determining a start state of a shift register of a first decoder corresponding to the first coder by processing at least k symbols of the first coded sequence and at least k symbols of a second sequence related to the uncoded sequence, and decoding the first coded sequence into a first decoded sequence with the first decoder by applying the start state. Para [0092], one can use a convolutional coder in Galois configuration, using at least two coders with k shift register elements; restarting correct decoding and error correcting at least p symbols if at least one LFSR has its first tap after p shift register elements, wherein the most left shift register element is the first one. It should be clear that one may express these conditions in a polynomial form) on a plurality of threads of a graphics processing unit (GPU) in parallel, wherein each descrambling segment of the descrambling sequence is output by at least one thread of the plurality of threads (see, Li, (see, pages 1912-1915, para [0001], introduction, GPU based wireless communication has increased).
Regarding claim 23, the combined teachings further disclose the system of claim 20, wherein the one or more processors are to derive the descrambling sequence from one or more Fibonacci linear feedback shift registers (LFSRs) that are generated using Galois LFSRs using a plurality of threads of a graphics processing unit (GPU) (se, Lablans, teaches in sending a sequence of binary or n-valued symbols one may want to repeat the sequence to detect errors. By scrambling one or both sequences one may also be able to correct errors. The standard convolutional coders are LFSR based descramblers in Fibonacci configuration. Para [0009], a method is provided for decoding with a processor a first coded sequence of p n-state symbols with p and n being integers greater or equal to 2, comprising generating the first coded sequence from an uncoded sequence of p n-state symbols by a first coder equivalent to a first n-state descrambler with a first n-state Linear Feedback Shift Register (LFSR) in Galois configuration having k shift register elements with k being an integer greater than 1, determining a start state of a shift register of a first decoder corresponding to the first coder by processing at least k symbols of the first coded sequence and at least k symbols of a second sequence related to the uncoded sequence, and decoding the first coded sequence into a first decoded sequence with the first decoder by applying the start state. Para [0092], one can use a convolutional coder in Galois configuration, using at least two coders with k shift register elements; restarting correct decoding and error correcting at least p symbols if at least one LFSR has its first tap after p shift register elements, wherein the most left shift register element is the first one. It should be clear that one may express these conditions in a polynomial form) on a plurality of threads of a graphics processing unit (GPU) in parallel, wherein each descrambling segment of the descrambling sequence is output by at least one thread of the plurality of threads (see, Li, (see, pages 1912-1915, para [0001], introduction, GPU based wireless communication has increased).
8. Claim(s) 15 is rejected under 35 U.S.C. 103 as being unpatentable over Jeong in view of Depienne (US 2009/0323784)(hereafter Depienne) (see IDS).
Regarding claim 15, Jeong does not disclose the computer readable medium of claim 14, wherein the descrambling sequence is 1024 bits, a plurality of thread hardware units comprises 32 thread hardware units, and one or more descrambling segments are 32 bits wide, and wherein a first array location and a second array location are word-length memory locations in a shared memory. However, in same field of endeavor, Depienne teaches, [0005], descrambler module. [0047], the scrambling sequence has a length of 127 bits. The representation of the input is an array of integers, out of which every 32 bits are valid information bits. §[0126]. Also, Li, page 1920, 46.1, maximum number of threads per block is 1024. Para 1924, para [0007], each thread block can support 1024 threads for parallel execution. Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to combine the teachings of Depienne with the Jeong, as a whole, so process the descrambling segments as per claimed, the motivation is to yield predictable results.
Allowable Subject Matter
9. Claims 3-5, 7 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
10. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DHAVAL V PATEL/Primary Examiner, Art Unit 2631