DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable
interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Response to Arguments
5. Applicant's arguments filed 12/05/2025 have been fully considered but they are not persuasive. Regarding claims 1 and 20, applicant argues the prior art does not teach the amended limitations, i.e. “wherein the stack structure comprises a plurality of stepwise structures on respectively corresponding to the plurality of connection regions… wherein the plurality of connection regions of the cell array structure correspondingly overlap the plurality of pass transistor regions of the peripheral circuit structure, when viewed in a plan view.”
Applicant's arguments do not comply with 37 CFR 1.111(c) because they do not clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. Further, they do not show how the amendments avoid such references or objection
Referring to Figs 4 and 12 of Baek, Seokcheon et al. (Pub No. US 20200243559 A1) (hereinafter, Baek), electrode structure ST comprise of the stepwise structure (not labelled), which are located within the connection regions CNR1/CNR2. Further, according to Fig 5 of the Applicant’s Disclosure, the stepwise or stair areas are located in connection regions CNR1/CNR2.
Referring to Figs 10 and 12 and ¶¶[0084 – 0088] of Baek the through-interconnection structures TS1 – TS4 are located vertically above pass transistors PT1 – PT4 and explicitly overlap within the stepwise structure to form a direct connection.
6. Applicant’s arguments, see Rejections Under 35 USC §§ 102 and 103, filed 12/05/2025, with respect to the rejection of claim 13 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Baek, Seokcheon et al. (Pub No. US 20200243559 A1) (hereinafter, Baek) in view of Yun, Kyunghwa et al. (Pub No. US 20200388336 A1) (hereinafter, Yun).
For above mentioned reasons, the rejection is deemed proper and considered final.
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
8. Claims 1-2, 4-6 and 9-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baek, Seokcheon et al. (Pub No. US 20200243559 A1) (hereinafter, Baek).
Baek, Fig 8: Cross-sectional view of 3D semiconductor memory device
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Re Claim 1, (Currently Amended) Baek teaches a semiconductor memory device, comprising:
a substrate (Peripheral buried insulating layer; 50; Fig 8; ¶[0066]) comprising a plurality of pass transistor regions (Regions comprising pass transistors PT1 - PT4; Fig 8);
a peripheral circuit structure (Peripheral logic structure; PS; Fig 8; ¶[0043]) comprising a plurality of pass transistors (Pass transistors; PT1 - PT4; Fig 8; ¶[0041]) on the plurality of pass transistor regions; and
Baek, Fig 3: Perspective view illustrating 3D semiconductor memory device
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a cell array structure (Cell array structure; CS; Fig 3; ¶[0043]) on the peripheral circuit structure, the cell array structure comprising a plurality of cell array regions (Cell array regions; CAR1/CAR2; Fig 4; ¶[0045]) and a plurality of connection regions (Connection regions; CNR1/CNR2; Fig 4; ¶[0045]) that are alternately arranged along a first direction (D1; Figs 4/8); (See Figure 4 below)
Baek, Fig 4: Plane view of cell array regions and cell connection regions
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wherein the cell array structure further comprises a stack structure (Cell electrode structure; CST; Fig 8; ¶[0052]) comprising a plurality of conductive patterns (Cell gate electrodes/ground selection gate electrodes; CGE/GGE1b/GGE2b; Figs 8/9; ¶[0052]) vertically stacked and correspondingly connected to the plurality of pass transistors (Connected to pass transistors via contact plugs CPLG and Horizontal semiconductor layer 100; Fig 12; ¶[0045]), (See Figure 12 below)
Baek, Fig 12: Cross-sectional view including contact plugs connected to gate electrodes
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wherein the stack structure comprises a plurality of stepwise structures (Stepped structures (not labelled); Fig 18; ¶¶[0055-0056]) respectively corresponding to (Referring to Figs 4 and 12, electrode structure ST comprise of the stepwise structure (not labelled), which are located within the connection regions CNR1/CNR2) the plurality of connection regions, (See Figure 4 above)
Baek, Fig 10: Three-dimensional view showing stepwise structures
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and wherein the plurality of connection regions of the cell array structure correspondingly overlap (Referring to Figs 10 and 12 and ¶¶[0084 – 0088] the through-interconnection structures TS1 – TS4 are located vertically above pass transistors PT1 – PT4 and explicitly overlap within the stepwise structure to form a direct connection) the plurality of pass transistor regions of the peripheral circuit structure, when viewed in the plan view (Along D3, Fig 10).
Baek, Fig 5: Plane view of pads within cell array regions and cell connection regions
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Re Claim 2, (Currently Amended) Baek teaches the semiconductor memory device of claim 1, further comprising a plurality of cell contact plugs (Cell contact plugs; CPLG; Fig 12; ¶¶[0092-0093]) provided on each of the plurality of connection regions (Connection regions; CNR1/CNR2; Fig 4; ¶[0045]),
wherein the plurality of cell contact plugs correspondingly connect (Per ¶[0092] the cell contact plugs are connected to peripheral logic circuits) the plurality of pass transistors (Pass transistors; PT1 - PT4; Fig 8; ¶[0041]) and ends of the plurality of conductive patterns (Cell gate electrodes/ground selection gate electrodes; CGE/GGE1b/GGE2b; Figs 8/9; ¶[0052]).
Re Claim 4, (Original) Baek teaches the semiconductor memory device of claim 1, wherein the plurality of stepwise structures (Stepped structures (not labelled); Fig 18; ¶¶[0055-0056]) of the stack structure (Cell electrode structure; CST; Fig 8; ¶[0052]) are at different levels (Outer stepped structure of CST protrude outward further than the inner stepped structures from the top of the substrate; Fig 6) from a top surface (Upper surface of peripheral layer 50 (below 100 in Fig 6); Figs 6/8) of the substrate (Peripheral buried insulating layer; 50; Fig 8; ¶[0066]).
Re Claim 5, (Original) Baek teaches the semiconductor memory device of claim 1, wherein the cell array structure further (Cell array structure, i.e. comprises cell electrode structure CST; CS; Figs 3/8; ¶[0043]) comprises:a plurality of vertical structures (Vertical structures; VS1/VS2; Fig 8; ¶[0044]) that penetrate the stack structure (Cell electrode structure; CST; Fig 8; ¶[0052]) on the plurality of connection regions (Connection regions; CNR1/CNR2; Fig 4; ¶[0045]); and
a plurality of bit lines (Bit lines; BL1/BL2; Fig 8; ¶[0081]) that cross the stack structure and are connected to the plurality of vertical structures,
wherein the peripheral circuit structure (Peripheral logic structure; PS; Fig 8; ¶[0043]) further comprises a plurality of page buffer circuits (Page buffers; 4; Fig 1; ¶¶[0030,0032]) connected (Page buffers 4 are connected to memory cell array 1 through bit lines; ¶[0032]) to the plurality of bit lines, and
wherein the plurality of page buffer circuits overlap portions of the plurality of cell array regions (Page buffers 4 overlap cell array regions CAR as they are comprised within the peripheral circuit region and connected to bit lines within the CAR; ¶¶[0032, 0068]).
Re Claim 6, (Original) Baek teaches the semiconductor memory device of claim 1, wherein the cell array structure (Cell array structure; CS; Fig 3; ¶[0043]) comprises:a first cell array region (Cell array region; CAR1; Fig 4; ¶[0045]) and a second cell array region (Cell array region; CAR2; Fig 4; ¶[0045]); and
a first connection region (Connection region; CNR3; Fig 4; ¶[0045]) and a second connection region (Connection regions; CNR1/CNR2; Fig 4; ¶[0045]) ,
wherein the first connection region is between (CNR3 between CAR1 and CAR2; Fig 4) the first cell array region and the second cell array region,
wherein the second cell array region is between (CAR2 between CNR3 and CNR2; Fig 4) the first connection region and the second connection region,
wherein the plurality of stepwise structures (Stepped structures (not labelled); Fig 18; ¶¶[0055-0056]) comprise a first stepwise structure (Inner stepped structures, i.e. closest to opening OP; Fig 18) and a second stepwise structure (Outer stepped structures, i.e. furthest from opening OP; Fig 18) , and
wherein the plurality of conductive patterns (Cell gate electrodes/ground selection gate electrodes; CGE/GGE1b/GGE2b; Figs 8/9; ¶[0052]) of the stack structure (Cell electrode structure; CST; Fig 8; ¶[0052]) comprise:
a plurality of first conductive patterns (CGE/GGE1b/GGE2b of the inner stepped structure; Figs 8/18) that define the first stepwise structure on the first connection region; and
a plurality of second conductive patterns (CGE/GGE1b/GGE2b of the outer stepped structure; Figs 8/18) that define the second stepwise structure on the second connection region.
Baek, Fig 11A: Plane view comprising pad regions and bridge regions
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Re Claim 9, (Original) Baek teaches the semiconductor memory device of claim 1, wherein:
each of the plurality of connection regions (Connection regions; CNR1/CNR2; Fig 4; ¶[0045]) comprises a pad region (Region comprising pads P1/P2; Fig 11A) and a bridge region (Region comprising TS2 which bridges P1 with another cell array region CAR2 (not shown) and bridges P2 with opening OP; Fig 11A) in a second direction (D2) that intersects the first direction (D1), and the plurality of stepwise structures (Stepped structures (not labelled); Fig 18; ¶¶[0055-0056]) of the stack structure (Cell electrode structure; CST; Fig 8; ¶[0052]) are correspondingly provided on (Stepped structures of Fig 8 are within CNR1 and CNR3 of Fig 11A) the pad regions of the plurality of connection regions.
Re Claim 10, (Original) Baek teaches the semiconductor memory device of claim 9, wherein:
the stack structure (Cell electrode structure; CST; Fig 8; ¶[0052]) has a first width (Width 1; See Annotated Fig 10 below) in the second direction (D2) parallel to a top surface of the substrate, and
each of the plurality of stepwise structures (Stepped structures (not labelled); Fig 18; ¶¶[0055-0056]) has a second width (Width 2; See Annotated Fig 10 below) in the second direction, and the second width is less than the first width.
Baek, Fig 10: Annotated widths of stacked structures and stepwise structures
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Re Claim 11, (Original) Baek teaches the semiconductor memory device of claim 9, wherein the stack structure (Cell electrode structure; CST; Fig 8; ¶[0052]) has substantially a same thickness (Vertical height of CST; Fig 8) on each of the plurality of cell array regions (Cell array regions; CAR1/CAR2; Fig 4; ¶[0045]).
Re Claim 12, (Original) Baek teaches the semiconductor memory device of claim 9, wherein a thickness of the stack structure (Cell electrode structure; CST; Fig 8; ¶[0052]) on the bridge regions (Region comprising TS2 which bridges P1 with another cell array region CAR2 (not shown) and bridges P2 with opening OP; Fig 11A) is substantially the same as a thickness of the stack structure on the plurality of cell array regions (Cell array regions; CAR1/CAR2; Fig 4; ¶[0045]).
Claim Rejections - 35 USC § 103
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claims 3, 13-14 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Baek, Seokcheon et al. (Pub No. US 20200243559 A1) (hereinafter, Baek), and further in view of Yun, Kyunghwa et al. (Pub No. US 20200388336 A1) (hereinafter, Yun).
Re Claim 3, (Original) Baek teaches the semiconductor memory device of claim 2, wherein the plurality of cell contact plugs (Cell contact plugs; CPLG; Fig 12; ¶¶[0092-0093]) penetrate the ends of the plurality of conductive patterns (Cell gate electrodes/ground selection gate electrodes; CGE/GGE1b/GGE2b; Figs 8/9; ¶[0052]).
However, Baek does not teach the plurality of cell contact plugs contact sidewalls of the plurality of conductive patterns.
In the same field of endeavor, Yun teaches the plurality of cell contact plugs (Contacts; CP1 to CPm/CPs; Fig 19; ¶[0079]) contact sidewalls (Sidewalls are contacted by CP1 to CPm/CPs as the Contacts penetrate through the word lines; Fig 19) of the plurality of conductive patterns (Word lines; WL1 to WLm; Fig 19; ¶[0079]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used the plurality of cell contact plugs in contact with sidewalls of the plurality of conductive patterns, as taught by Yun, for the semiconductor device of Baek. One would have been motivated to do this with a reasonable expectation of success because passing the contact plugs through the word lines creates a greater number of connections to the word lines, allowing for the number of pass transistors to decrease, therefore decreasing overall chip size, as suggested by Yun (¶[0003]).
Re Claim 13, (Currently Amended) Baek teaches a semiconductor memory device, comprising:
a substrate (Peripheral buried insulating layer; 50; Fig 8; ¶[0066]) comprising a plurality of pass transistor regions (Regions comprising pass transistors PT1 - PT4; Fig 8) and a plurality of page buffer regions (Regions comprising page buffers 4; Fig 1; ¶¶[0030,0032]);
a peripheral circuit structure (Peripheral logic structure; PS; Fig 8; ¶[0043]) comprising a plurality of peripheral circuits (Interconnection lines; 33; Fig 8; ¶[0070]) and a plurality of first bonding pads (Lower peripheral contact plugs connecting to pass transistors; 31; Fig 8; ¶[0069]) connected to the plurality of peripheral circuits, the plurality of peripheral circuits being integrated on the substrate; and
a cell array structure (Cell array structure; CS; Fig 3; ¶[0043]) comprising a plurality of second bonding pads (Upper peripheral contact plugs connecting to CST; Fig 8) coupled to the plurality of first bonding pads, the cell array structure comprising a plurality of cell array regions (Cell array regions; CAR1/CAR2; Fig 4; ¶[0045]) and a plurality of connection regions (Connection regions; CNR1/CNR2; Fig 4; ¶[0045]) alternately disposed along a first direction (D1; Figs 4/8),
wherein the plurality of peripheral circuits of the peripheral circuit structure comprises: a plurality of pass transistors (Pass transistors; PT1 - PT4; Fig 8; ¶[0041]) on the plurality of pass transistor regions; and
a plurality of page buffer circuits (Page buffers; 4; Fig 1; ¶¶[0030,0032]) on the plurality of page buffer regions,
wherein the cell array structure comprises:a stack structure (Cell electrode structure; CST; Fig 8; ¶[0052]) comprising a plurality of conductive patterns (Cell gate electrodes/ground selection gate electrodes; CGE/GGE1b/GGE2b; Figs 8/9; ¶[0052]) that are vertically stacked, the stack structure having a stepwise structure (Stepped structures (not labelled); Fig 18; ¶¶[0055-0056]) on each of the plurality of connection regions;
a plurality of vertical structures (Vertical structures; VS1/VS2; Fig 8; ¶[0044]) that penetrate the stack structure on the plurality of cell array regions;
a plurality of bit lines (Bit lines; BL1/BL2; Fig 8; ¶[0081]) that cross the stack structure and are connected to the plurality of vertical structures; and
wherein the plurality of connection regions of the cell array structure correspondingly overlap (Referring to Figs 4, 10 and 12 and ¶¶[0084 – 0088] the through-interconnection structures TS1 – TS4 located in ST are located vertically above pass transistors PT1 – PT4 and explicitly overlap within the stepwise structure to form a direct connection) the plurality of pass transistor regions of the peripheral circuit structure, when viewed in a plan view (Along D3; Fig 10), and
wherein the plurality of cell array regions of the cell array structure correspondingly overlap (Referring to Figs 2 and 12, page buffers 4 pass through bit lines per ¶[0032]) which must be in the cell array region CAR, such that the CAR comprises of word lines passing through bitlines) the plurality of page buffer regions of the peripheral circuit structure, when viewed in the plan view.
However, Baek does not teach a plurality of cell contact plugs penetrating ends of the plurality of conductive patterns and the plurality of pass transistors are correspondingly connected on the plurality of connection regions.
In the same field of endeavor, Yun teaches a plurality of cell contact plugs (Contacts; CP1 to CPm/CPs; Fig 19; ¶[0079]) penetrating ends (Sidewalls are contacted by CP1 to CPm/CPs as the Contacts penetrate through the word lines; Fig 19) of the plurality of conductive patterns (Word lines; WL1 to WLm; Fig 19; ¶[0079]) and the plurality of pass transistors (Pass transistors; TR1 – TRm; Fig 6; ¶[0040]) are correspondingly connected on the plurality of connection regions (Stair Area; SA; Fig 6; ¶[0068]). (See Yun, Fig 19 below)
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a plurality of cell contact plugs penetrating ends of the plurality of conductive patterns and the plurality of pass transistors are correspondingly connected on the plurality of connection regions, as taught by Yun, for the semiconductor device of Baek. One would have been motivated to do this with a reasonable expectation of success because passing the contact plugs through the word lines creates a greater number of connections to the word lines, allowing for the number of pass transistors to decrease, therefore decreasing overall chip size, as suggested by Yun (¶[0003]).
Yun, Fig 19: Cross-section view of contact plugs passing through conductive patterns
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Re Claim 14, (Original) Baek teaches the semiconductor memory device of claim 13, wherein the cell array structure (Cell array structure; CS; Fig 3; ¶[0043]) comprises:
a first cell array region (Cell array region; CAR1; Fig 4; ¶[0045]) and a second cell array region (Cell array region; CAR2; Fig 4; ¶[0045]);
a first connection region (Connection region; CNR3; Fig 4; ¶[0045]) between the first cell array region and the second cell array region; and
a second connection region (Connection regions; CNR1/CNR2; Fig 4; ¶[0045]) spaced apart from the first connection region,
wherein the plurality of conductive patterns (Cell gate electrodes/ground selection gate electrodes; CGE/GGE1b/GGE2b; Figs 8/9; ¶[0052]) of the stack structure (Cell electrode structure; CST; Fig 8; ¶[0052]) comprise: a plurality of first conductive patterns (CGE/GGE1b/GGE2b of the inner stepped structure; Figs 8/18) that define a first stepwise structure (Inner stepped structures, i.e. closest to opening OP; Fig 18) on the first connection region; and
a plurality of second conductive patterns (CGE/GGE1b/GGE2b of the outer stepped structure; Figs 8/18) that define a second stepwise structure (Outer stepped structures, i.e. furthest from opening OP; Fig 18) on the second connection region, and
wherein the plurality of pass transistors (Pass transistors; PT1 - PT4; Fig 8; ¶[0041]) comprise:a plurality of first pass transistors (Pass transistors; SPT2/PT2/PT4; Fig 8; ¶[0040]) on the first connection region and connected to the plurality of first conductive patterns; and
a plurality of second pass transistors (Pass transistors; SPT1/PT1/PT3; Fig 8; ¶[0040]) on the second connection region and connected to the plurality of second conductive patterns.
Re Claim 16, (Original) Baek teaches the semiconductor memory device of claim 13, wherein the plurality of cell contact plugs (Cell contact plugs; CPLG; Fig 12; ¶¶[0092-0093]) penetrate the ends of the plurality of conductive patterns (Cell gate electrodes/ground selection gate electrodes; CGE/GGE1b/GGE2b; Figs 8/9; ¶[0052]).
However, Baek does not teach the plurality of cell contact plugs contact with sidewalls of the plurality of conductive patterns.
In the same field of endeavor, Yun teaches the plurality of cell contact plugs (Contacts; CP1 to CPm/CPs; Fig 19; ¶[0079]) contact sidewalls (Sidewalls are contacted by CP1 to CPm/CPs as the Contacts penetrate through the word lines; Fig 19) of the plurality of conductive patterns (Word lines; WL1 to WLm; Fig 19; ¶[0079]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used the plurality of cell contact plugs in contact with sidewalls of the plurality of conductive patterns, as taught by Yun, for the semiconductor device of Baek. One would have been motivated to do this with a reasonable expectation of success because passing the contact plugs through the word lines creates a greater number of connections to the word lines, allowing for the number of pass transistors to decrease, therefore decreasing overall chip size, as suggested by Yun (¶[0003]).
Re Claim 17, (Original) Baek does not teach the semiconductor memory device of claim 13, wherein the plurality of cell contact plugs have a substantially same vertical length on the plurality of connection regions.
In the same field of endeavor, Yun teaches the semiconductor memory device of claim 13, wherein the plurality of cell contact plugs (Contacts; CP1 to CPm/CPs; Fig 19; ¶[0079]) have a substantially same vertical length (Second height; H2; Fig 19; ¶[0079]) on the plurality of connection regions (Stair Area; SA; Fig 19; ¶[0068]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a plurality of cell contact plugs which have a substantially same vertical length on the plurality of connection regions, as taught by Yun, for the semiconductor device of Baek. One would have been motivated to do this with a reasonable expectation of success because the number of pass transistors decreases, due to the contact plugs extending to high density of word lines, therefore decreasing overall chip size, as suggested by Yun (¶¶[0003, 0079-0080]).
Re Claim 18, (Original) Baek teaches the semiconductor memory device of claim 13, wherein:
the stack structure (Cell electrode structure; CST; Fig 8; ¶[0052]) has a first width (Width 1; See Annotated Fig 10) in the second direction (D2) parallel to a top surface of the substrate, and
each of the plurality of stepwise structures (Stepped structures (not labelled); Fig 18; ¶¶[0055-0056]) has a second width (Width 2; See Annotated Fig 10) in the second direction, and the second width is less than the first width.
Re Claim 19, (Currently Amended) Baek teaches the semiconductor memory device of claim 13, wherein:
each of the plurality of connection regions (Connection regions; CNR1/CNR2; Fig 4; ¶[0045]) comprises a pad region (Region comprising pads P1/P2; Fig 11A) and a bridge region (Region comprising TS2 which bridges P1 with another cell array region CAR2 (not shown) and bridges P2 with opening OP; Fig 11A) in a second direction (D2) that intersects the first direction (D1), and
the stack structure (Cell electrode structure; CST; Fig 8; ¶[0052]) has substantially a same thickness (Vertical height of CST; Fig 8) on the plurality of cell array regions (Cell array regions; CAR1/CAR2; Fig 4; ¶[0045]) and the bridge regions of each of the plurality of connection regions.
11. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Baek, Seokcheon et al. (Pub No. US 20200243559 A1) (hereinafter, Baek) in view of Yun, Kyunghwa et al. (Pub No. US 20200388336 A1) (hereinafter, Yun) as applied to claim 14, and further in view of Eom, Dae Sung (Pub No. US 20240015966 A1) (hereinafter, Eom).
Re Claim 15, (Original) Baek in view of Yun does not teach the semiconductor memory device of claim 14, wherein the first stepwise structure is at a different vertical level than the second stepwise structure.
In the same field of endeavor, Eom teaches the semiconductor memory device of claim 14, the first stepwise structure (First stepped sidewalls; SW1; Fig 9A; ¶[0063]) is at a different vertical level (Different levels in the z-direction; Fig 9A; ¶[0063]) than the second stepwise structure (Second stepped sidewalls; SW2; Fig 9A; ¶[0063]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used the first stepwise structure and the second stepwise structure at different vertical levels, as taught by Eom, for the semiconductor device of Baek in view of Yun. One would have been motivated to do this with a reasonable expectation of success because stepwise structures arranged at different vertical levels allows for additional space of gate electrodes in order to compensate for the increasing number of memory cells needed in three-dimensional memory devices, as suggested by Eom (¶[0004]).
13. Claims 7-8 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Baek, Seokcheon et al. (Pub No. US 20200243559 A1) (hereinafter, Baek) as applied to claim 6 above, and further in view of Eom, Dae Sung (Pub No. US 20240015966 A1) (hereinafter, Eom).
Eom, Fig 9A: Three-dimensional view of stepwise structures at different vertical levels
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Re Claim 7, (Original) Baek does not teach the semiconductor memory device of claim 6, wherein the first stepwise structure and the second stepwise structure are at different vertical levels.
In the same field of endeavor, Eom teaches the semiconductor memory device of claim 6, wherein the first stepwise structure (First stepped sidewalls; SW1; Fig 9A; ¶[0063]) and the second stepwise structure (Second stepped sidewalls; SW2; Fig 9A; ¶[0063]) are at different vertical levels (Different levels in the z-direction; Fig 9A; ¶[0063]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used the first stepwise structure and the second stepwise structure at different vertical levels, as taught by Eom, for the semiconductor device of Baek. One would have been motivated to do this with a reasonable expectation of success because stepwise structures arranged at different vertical levels allows for additional space of gate electrodes in order to compensate for the increasing number of memory cells needed in three-dimensional memory devices, as suggested by Eom (¶[0004]).
Re Claim 8, (Currently Amended) Baek teaches the semiconductor memory device of claim 6,
wherein the plurality of pass transistor regions (Regions comprising pass transistors PT1 - PT4; Fig 8) comprise: a first pass transistor region (Region comprising pass transistors PT2/PT4; Fig 8) that overlaps the first connection region (Connection region; CNR3; Fig 4; ¶[0045]) ; and
a second pass transistor region (Region comprising of pass transistors PT1/PT2; Fig 8) that overlaps the second connection region (Connection regions; CNR1/CNR2; Fig 4; ¶[0045]), and
wherein the plurality of pass transistors (Pass transistors; PT1 - PT4; Fig 8; ¶[0041]) comprise:
a plurality of first pass transistors (Pass transistors; SPT2/PT2/PT4; Fig 8; ¶[0040]) connected to the plurality of first conductive patterns (CGE/GGE1b/GGE2b of the inner stepped structure; Figs 8/18) on the first pass transistor region; and
a plurality of second pass transistors (Pass transistors; SPT1/PT1/PT3; Fig 8; ¶[0040]) connected to the plurality of second conductive patterns (CGE/GGE1b/GGE2b of the outer stepped structure; Figs 8/18) on the second pass transistor region.
Re Claim 20, (Currently Amended) Baek teaches an electronic system, comprising:
a semiconductor memory device comprising a substrate (Peripheral buried insulating layer; 50; Fig 8; ¶[0066]) that comprises a plurality of pass transistor regions (Regions comprising pass transistors PT1 - PT4; Fig 8),
a peripheral circuit structure (Peripheral logic structure; PS; Fig 8; ¶[0043]) that comprises a plurality of pass transistors (Pass transistors; PT1 - PT4; Fig 8; ¶[0041]) on the plurality of pass transistor regions, and
a cell array structure (Cell array structure; CS; Fig 3; ¶[0043]) on the peripheral circuit structure, the cell array structure comprising a plurality of cell array regions (Cell array regions; CAR1/CAR2; Fig 4; ¶[0045]) and a plurality of connection regions (Connection regions; CNR1/CNR2; Fig 4; ¶[0045]) that are alternately disposed along one direction (First direction; D1; Fig 4); and
wherein the cell array structure (Cell array structure; CS; Fig 3; ¶[0043]) comprises a stack structure (Cell electrode structure; CST; Fig 8; ¶[0052]) comprising a plurality of vertically stacked conductive patterns (Cell gate electrodes/ground selection gate electrodes; CGE/GGE1b/GGE2b; Figs 8/9; ¶[0052]) that are correspondingly connected to the plurality of pass transistors (Pass transistors; PT1 - PT4; Fig 8; ¶[0041]),
wherein the stack structure comprises a plurality of stepwise structures (Stepped structures (not labelled); Fig 18; ¶¶[0055-0056]) respectively corresponding to (Referring to Figs 4 and 12, electrode structure ST comprise of the stepwise structure (not labelled), which are located within the connection regions CNR1/CNR2) plurality of connection regions (Connection regions; CNR1/CNR2; Fig 4; ¶[0045]), and
wherein the plurality of connection regions of the cell array structure correspondingly overlap (Referring to Figs 10 and 12 and ¶¶[0084 – 0088] the through-interconnection structures TS1 – TS4 are located vertically above pass transistors PT1 – PT4 and explicitly overlap within the stepwise structure to form a direct connection) the plurality of pass transistor regions of the peripheral circuit structure, when viewed in a plan view (Along D3; Fig 10).
However, Baek does not teach a controller electrically connected through an input/output pad to the semiconductor memory device, the controller controlling the semiconductor memory device.
In the same field of endeavor, Eom teaches a controller (Memory controller; ¶[0032]) electrically connected through an input/output pad (Input/output circuit; 21; Fig 1; ¶[0032]) to the semiconductor memory device (Semiconductor memory device; 50; Fig 1; ¶[0032]), the controller controlling the semiconductor memory device.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a controller electrically connected through an input/output pad to the semiconductor memory device, the controller controlling the semiconductor memory device, as taught by Eom, for the semiconductor device of Baek. One would have been motivated to do this with a reasonable expectation of success because a memory controller may be combined with a memory device to create a memory system, such as a memory card or Solid State Disk to store digital data into electronic devices, as suggested by Eom (¶¶[0144, 0146]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[1] Oh, Sung Lae et al. (Pub No. US 20210384160 A1) discloses a memory device including a first memory block defined in a first wafer; and a second memory block defined in a second wafer that is disposed in a vertical direction with respect to the first wafer. A size of the first memory block is smaller than a size of the second memory block.
[2] Kim, Chang-Bum et al. (Pub No. US 20180294277 A1) discloses a three-dimensional semiconductor memory device includes a cell string vertically extending from a top surface of a substrate and having first and second cell transistors, first and second word lines connected to gate electrodes of the first and second cell transistors respectively, a first pass transistor connecting the first word line to a row decoder, and a second pass transistor connecting the second word line to the row decoder. The first pass transistor includes a plurality of first sub-transistors connected in parallel between the first word line and the row decoder.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/T.E.D./
Examiner
Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817