DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-6 and 13-17, in the reply filed on February 20, 2026 is acknowledged. Claims 7-12 have been cancelled by the Applicant.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 and 13-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Akira et al. (Akira) (JP 2020013955 A1) in view of Smits et al. (Smits) (US 2015/0294951 A1).
In regard to claim 1, Akira (paragraphs 43-54, Figs. 9-11 and associated text and items) discloses a method, comprising: attaching a semiconductor integrated circuit die (item 3) to an upper surface of a die-attachment portion of a substrate (items TD, TAB) that further includes an electrically conductive lead (items TD,TG, TS, KE1, KE2) having an upper surface coplanar with the upper surface of the die-attachment portion (item TAB); transferring a mass of electrically conductive material (items 2b, 7) onto the upper surface of the electrically conductive lead (items TD,TG, TS, TSb, KE1, KE2) to form a gap-filling spacer (gap between item 5 and lead frame TD plus TG plus TS plus KE1 plus KE2 plus TAB occupied by items 2b plus 7); and mounting a bottom surface of an electrically conductive flat clip (item 5) onto the semiconductor integrated circuit die (item 3) and the gap-filling spacer (gap shown but not labeled) using a solder paste material (items 7, 8); wherein the semiconductor integrated circuit die (item 3) is sandwiched between the die-attachment portion of the substrate (items TD, TAB) and the electrically conductive flat clip (item 5); wherein the electrically conductive flat clip (item 5) has a distal portion extending away from the semiconductor integrated circuit die (item 3); and wherein the gap-filling spacer (gap between item 5 and lead frame TD plus TG plus TS plus KE1 plus KE2 plus TAB occupied by items 2b plus 7) is sandwiched between the electrically conductive lead (items TSb, KE1, KE2) and the distal portion of the electrically conductive flat clip (item 5), but does not specifically disclose transferring a mass of electrically conductive material onto the upper surface of the electrically conductive lead by use of Laser Induced Forward Transfer (LIFT) processing.
Smits (claim 1, paragraphs 7-13, 23-35, Figs. 1, 2A, 2B and associated text) discloses a method of transferring solder and/or conductive adhesive for bonding using Laser Induced Forward Transfer, LIFT processing.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Smits for the purpose of providing a high resolution method of depositing solder or conductive adhesive.
In regard to claim 2, Akira (paragraphs 43-54, Figs. 9-11 and associated text and items) as modified by Smits (claim 1, paragraphs 7-13, 23-35, Figs. 1, 2A, 2B and associated text) discloses wherein the mass of electrically conductive material (items 7, 2b, Akira, item 40, Smits) is made of copper or silver (paragraphs, 39, 50, Smit).
In regard to claim 3, Akira (paragraphs 43-54, Figs. 9-11 and associated text and items) as modified by Smits (claim 1, paragraphs 7-13, 23-35, Figs. 1, 2A, 2B and associated text) discloses wherein transferring comprises performing a plurality of transfers of masses of gap-filling material (items 7, 2b, Akira, item 40, Smits) using a corresponding plurality of LIFT processing steps.
In regard to claim 4, Akira (paragraphs 43-54, Figs. 9-11 and associated text and items) as modified by Smits discloses wherein the bottom surface of the electrically conductive flat clip (item 5) mounted onto the semiconductor integrated circuit die (item 3) and the bottom surface of the electrically conductive flat clip (item 5) mounted onto the gap-filling spacer (gap between item 5 and lead frame TD plus TG plus TS plus KE1 plus KE2 plus TAB occupied by items 2b plus 7) are (horizontally and/or vertically) coplanar.
In regard to claim 13, Akira (paragraphs 43-54, Figs. 9-11 and associated text and items) as modified by Smits discloses wherein transferring the mass of electrically conductive material (items 7, 2b) onto the upper surface of the electrically conductive lead (items TD,TG, TS, TSb, KE1, KE2) is performed before attaching the semiconductor integrated circuit die (item 3) to the upper surface of the die-attachment portion of a substrate (items TD, TAB).
In regard to claim 14, Akira (paragraphs 43-54, Figs. 9-11 and associated text and items) discloses a method, comprising: providing a planar substrate (lead frame substrate, items TD plus TG plus TS plus KE1 plus KE2 plus TAB) including a die-attachment portion (items TD, TAB) and an electrically conductive lead (items TD,TG, TS, TSb, KE1, KE2); transferring a mass of gap-filling material (items 7, 2b) onto said electrically conductive lead of the planar substrate (lead frame substrate, items TD plus TG plus TS plus KE1 plus KE2 plus TAB); after said transferring, then mounting a semiconductor die (item 3) onto the die-attachment portion (items TD, TAB) of the planar substrate (lead frame substrate, items TD plus TG plus TS plus KE1 plus KE2 plus TAB); dispensing an attachment material (items 8, 2a) onto the semiconductor die (item 3) and the mass of gap-filling material (items 7, 2b); and mounting, using the attachment material (items 8, 2a), a planar electrically conductive clip (item 5) to the semiconductor die (item 3) and the mass of gap-filling material (items 7, 2b), said planar electrically conductive clip (item 5) including a distal portion extending away from the semiconductor die (item 3) and over the mass of gap- filling material (items 7, 2b) at the electrically conductive lead (item TSb); wherein said mass of gap-filling material (items 7, 2b) has a thickness to fill a gap between the planar electrically conductive clip (item 5) and the electrically conductive lead (item TSb), but does not specifically disclose transferring, by Laser Induced Forward Transfer (LIFT) processing, a mass of gap-filling material onto said electrically conductive lead of the planar substrate.
Smits (claim 1, paragraphs 7-13, 23-35, Figs. 1, 2A, 2B and associated text) discloses a method of transferring solder and/or conductive adhesive for bonding using Laser Induced Forward Transfer, LIFT processing.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Smits for the purpose of providing a high resolution method of depositing solder or conductive adhesive.
In regard to claim 15, Akira (paragraphs 43-54, Figs. 9-11 and associated text and items) as modified by Smits (claim 1, paragraphs 7-13, 23-35, Figs. 1, 2A, 2B and associated text) discloses wherein the mass of gap-filling material (items 7, 2b, Akira, item 40, Smits) is a mass of electrically conductive material.
In regard to claim 16, Akira (paragraphs 43-54, Figs. 9-11 and associated text and items) as modified by Smits (claim 1, paragraphs 7-13, 23-35, Figs. 1, 2A, 2B and associated text) discloses wherein the mass of electrically conductive material (items 7, 2b, Akira, item 40, Smits) is made of copper or silver.
In regard to claim 17, Akira (paragraphs 43-54, Figs. 9-11 and associated text and items) as modified by Smits (claim 1, paragraphs 7-13, 23-35, Figs. 1, 2A, 2B and associated text) discloses wherein transferring comprises performing a plurality of transfers of masses of gap-filling material (items 7, 2b, Akira, item 40, Smits) using a corresponding plurality of LIFT processing steps.
Claim(s) 5, 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Akira et al. (Akira) (JP 2020013955 A1) in view of Smits et al. (Smits) (US 2015/0294951 A1) as applied to claims 1-4 and 1-17 above, and further in view of Chaowasakoo et al. (Chaowasakoo) (US 2020/0144162 A1).
In regard to claim 5, Akira as modified by Smits does not specifically disclose forming a notch in the electrically conductive flat clip between the bottom surface of the electrically conductive flat clip mounted onto the semiconductor integrated circuit die and the bottom surface of the electrically conductive flat clip mounted onto the gap-filling spacer.
Chaowasakoo (paragraph 49, Fig. 4 and associated text) discloses forming a notch (item 183) in the electrically conductive flat clip (item 181) between the bottom surface of the electrically conductive flat clip (item 181) mounted onto the semiconductor integrated circuit die (item 130) and the bottom surface of the electrically conductive flat clip (item 181) mounted onto the gap-filling spacer (item 155).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chaowasakoo, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regard to claim 6, Chaowasakoo (paragraph 49, Fig. 4 and associated text) discloses wherein mounting comprises aligning the notch (item 183) with an edge of the semiconductor integrated circuit die (item 130).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Okada et al. (Okada) (JP 2019186321 A) could have been used as primary reference in place of Akira, which was provided by the Applicant. Please see written opinion. Sterken (EP 3933902 A1) discloses using Laser Induced Forward Transfer, LIFT processing.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 March 27, 2026
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