DETAILED ACTION
This Office Action is in response to the applicant's amendment filed March 12th, 2026. In virtue of this communication, claims 1-16 are currently presented in the instant application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claims 12-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites the limitation "the first metal layer" in line 17. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, this limitation is understood to be --a first metal layer--. Claims 13-16 are also rejected as they depend from claim 12.
Claim 16 recites the limitation “a first metal layer” in line 2. It is unclear whether this is supposed to refer to the “a first metal layer” of claim 12 or to set forth a new and different metal layer. For the purposes of examination, this limitation is understood to be --the first metal layer--.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 5, 11, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsuzawa et al. (US 2020/0176354 A1; hereinafter Matsuzawa).
With respect to claim 1, Matsuzawa teaches a power module 10 in at least Figs. 18-20 with Figs. 1-17 teaching overlapping subject matter, comprising:
semiconductor chips (2u, 2d) (see Figs. 13, 18, and paragraphs 53-55, 61, 93, 95);
an insulating circuit board (5 on top in Fig. 18) including an insulating layer 51 and a first metal layer (52 below 51) disposed on a first surface of the insulating layer 5 (see Figs. 18, 19 and paragraphs 53-55, 64, 65, 109-111); and
lead frames 3e disposed between the semiconductor chips (2u, 2d) and the insulating circuit board 5 (see Fig. 18 and paragraphs 53-55, 62, 63, 94, 95),
wherein the lead frames 3e include:
a first lead frame (3e on left in Fig. 18) including a first terminal portion 31 and a first extension portion (where 3e contacts 5 on left in Fig. 18) extending from the first terminal portion 31 onto the insulating circuit board 5 to overlap with at least one of the semiconductor chips 2u on a plane (see Figs. 10-12, 14, 18, and paragraphs 53-55, 62, 63, 70, 94-97, 110, 111; also see Fig. 18 annotated below); and
a second lead frame (3e on right in Fig. 18) including a second terminal portion 31 and a second extension portion (where 3e contacts 5 on right in Fig. 18) extending from the second terminal portion 31 onto the insulating circuit board 5 to overlap with the at least one of remaining semiconductor chips 2d on the plane (see Figs. 10-12, 14, 18, and paragraphs 53-55, 62, 63, 70, 94-97, 110, 111; also see Fig. 18 annotated below),
wherein the first lead frame (3e on left in Fig. 18) and the second lead frame (3e on right in Fig. 18) are disposed to be spaced apart from each other on the same plane defined by the first metal layer (52 below 51) of the insulating circuit board (5 on top in Fig. 18) (see Figs. 18, 19, and paragraphs 62, 63, 95, 97, 111; also see Fig. 18 annotated below).
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With respect to claim 2, Matsuzawa teaches the power module of claim 1, further including: second metal layers (12 between 2u/2d and 3e) respectively connecting the at least one of the semiconductor chips 2u and the first lead frame (3e on left in Fig. 18), and the at least of the remaining semiconductor chips 2d and the second lead frame (3e on right in Fig. 18) (see Fig. 18 and paragraphs 63, 72, 74, 94, 110; also see Fig. 18 annotated above).
With respect to claim 5, Matsuzawa teaches the power module of claim 1, wherein each of the lead frames 3e has a thickness greater than a thickness of the first metal layer (52 below 51) (see Fig. 18 and paragraphs 53-55, 62-65).
With respect to claim 11, Matsuzawa teaches the power module of claim 1, wherein the insulating circuit board (5 on top in Fig. 18) further includes a heat sink plate (52 over 51) disposed on a second surface opposite to the first surface of the insulating layer 51 (see Fig. 18 and paragraphs 64-66).
With respect to claim 12 (and in view of the 112 rejection). Matsuzawa teaches a manufacturing method of a power module 10 in Figs. 18-20 with Figs. 1-17 teaching overlapping subject matter, the method comprising:
preparing semiconductor chips (2u, 2d), an insulating circuit board (5 on top in Fig. 18), lead frames 3e, and second metal layers (12 between 2u/2d and 3e) (see Figs. 7-18, and paragraphs 53-55, 62, 63, 93);
stacking and bonding the lead frames 3e on the insulating circuit board (5 on top in Fig. 18) (see Figs. 7-18, and paragraphs 66, 68, 73);
stacking and bonding the second metal layers 12 on some of the lead frames 3e overlapping with the semiconductor chips (2u, 2d) on a plane (see Figs. 7-18, and paragraphs 63, 72, 101); and
stacking and bonding the semiconductor chips (2u, 2d) on the second metal layers 12 (see Figs. 7-18 and paragraphs 63, 72, 101),
wherein the lead frames 3e include:
a first lead frame (3e on left in Fig. 18) including a first terminal portion 31 and a first extension portion (where 3e contacts 5 on left in Fig. 18) extending from the first terminal portion 31 onto the insulating circuit board 5 to overlap with at least one of the semiconductor chips 2u on a plane (see Figs. 10-12, 14, 18, and paragraphs 53-55, 62, 63, 70, 94-97, 110, 111; also see Fig. 18 annotated below); and
a second lead frame (3e on right in Fig. 18) including a second terminal portion 31 and a second extension portion (where 3e contacts 5 on right in Fig. 18) extending from the second terminal portion 31 onto the insulating circuit board 5 to overlap with the at least one of remaining semiconductor chips 2d on the plane (see Figs. 10-12, 14, 18, and paragraphs 53-55, 62, 63, 70, 94-97, 110, 111; also see Fig. 18 annotated below), and
wherein the first lead frame (3e on left in Fig. 18) and the second lead frame (3e on right in Fig. 18) are disposed on the same plane defined by a first metal layer (52 below 51) of the insulating circuit board (5 on top in Fig. 18) (see Figs. 18, 19, and paragraphs 62, 63, 95, 97, 111; also see Fig. 18 annotated below).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Matsuzawa et al. (US 2020/0176354 A1; hereinafter Matsuzawa) in view of Tsuchimochi (US 2019/0103340 A1).
With respect to claim 3, Matsuzawa discloses the power module of claim 2.
Matsuzawa does not disclose wherein a thermal expansion coefficient of each of the second metal layers is greater than a thermal expansion coefficient of each of the semiconductor chips and smaller than a thermal expansion coefficient of each of the lead frames. It is noted that the semiconductor chips are MOSFETs or IGBTs, the second metal layer is made of copper, and the lead frames are made of copper (see paragraph 61 and 62).
Tsuchimochi discloses a power module in at least Figs. 1-4 wherein a thermal expansion coefficient of each of second metal layers (24, 44) is greater than a thermal expansion coefficient of each of semiconductor chips and smaller than a thermal expansion coefficient of each of lead frames (see Figs. 1-4 and paragraphs 24, 25, 39, 44, 57; Copper-molybdenum spacer has such properties. Also see paragraph 64 of applicant’s original specification; same material same properties MPEP 2112.01).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a thermal expansion coefficient of each of the second metal layers of Matsuzawa would be greater than a thermal expansion coefficient of each of the semiconductor chips and smaller than a thermal expansion coefficient of each of the lead frames as taught by Tsuchimochi because such a configuration suppresses an imbalance in thermal expansion occurring between regions in vicinities of the respective semiconductor elements and thereby also suppresses occurrence of local stress or distortion due to the thermal expansion (see Tsuchimochi: paragraphs 24, 25).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Matsuzawa et al. (US 2020/0176354 A1; hereinafter Matsuzawa) in view of Rahimo et al. (US 2023/0223331; hereinafter Rahimo).
With respect to claim 4, Matsuzawa discloses the power module of claim 2.
Matsuzawa does not disclose wherein each of the second metal layers has a larger planar area than each of the semiconductor chips.
Rahimo discloses a power module in at least Figs. 3-5 wherein each of second metal layers 2 has a larger planar area than each of semiconductor chips 7 (see Figs. 3-5 and paragraphs 19, 38).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that in the power module of Matsuzawa each of the second metal layers would have a larger planar area than each of the semiconductor chips as taught by Rahimo so as to provide improved thermal conductivity and reliability (see Rahimo: paragraph 19).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Matsuzawa et al. (US 2020/0176354 A1; hereinafter Matsuzawa) in view of Bergmann et al. (US 2023/0056722 A1; hereinafter Bergmann).
With respect to claim 13, Matsuzawa discloses the manufacturing method of claim 12, wherein the stacking and bonding the lead frames 3e includes applying a metal bonding material 14 to a region where the insulating circuit board (5 on top in Fig. 18) and the lead frames 3e overlap on the plane, and face-to-face bonding (see Figs. 7-18, and paragraphs 66, 68, 74, 73).
Matsuzawa does not explicitly disclose bonding through pressurization and heat treatment.
Bergmann discloses a manufacturing method of a power module further comprising bonding through pressurization and heat treatment (see paragraph 22 and note sintering. Also see paragraph 85 of instant application and note sintering; same process).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the face-to-face bonding of Matsuzawa would be through pressurization and heat treatment as taught by Bergmann because such bonding (sintering) is well known in the art the selection of which would have flown naturally to one of ordinary skill in the art as necessitated by the specific requirements of a given application (see MPEP 2144 I).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Matsuzawa et al. (US 2020/0176354 A1; hereinafter Matsuzawa) in view of Kuromitsu et al. (US 2014/0192486 A1; hereinafter Kuromitsu).
With respect to claim 16, Matsuzawa teaches the manufacturing method of claim 12, wherein the insulating circuit board (5 on top in Fig. 18) includes an insulating layer 51, the first metal layer (52 below 51) disposed on a first surface of the insulating layer 51, and a heat sink plate (52 over 51) disposed on a second surface opposite to the first surface of the insulating layer 51, and wherein when the insulating layer 51 is made of a ceramic material, the insulating circuit board (5 on top in Fig. 18) is implemented as an active metal brazed (AMB) substrate produced by brazing (see Fig. 18 and paragraphs 64, 65).
Matsuzawa does not explicitly disclose wherein the first metal layer and the heat sink plate are made of a copper (Cu) material.
Kuromitsu discloses a manufacturing method of a power module in at least Fig. 19 wherein a first metal layer 423 and a heat sink plate 422 are made of a copper (Cu) material (see Fig. 19 and paragraphs 184-186, 190-195).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first metal layer and the heat sink plate of Matsuzawa would be made of a copper (Cu) material as copper is a well-known metal and heat sink material and it has been held by the courts that selection of a prior art material on the basis of its suitability for its intended purpose is within the level of ordinary skill (see MPEP 2144.07).
Allowable Subject Matter
Claims 6-10, 14, and 15 (bending the correction to the 112 rejection) are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art does not disclose or fairly suggest:
wherein the lead frames further include: a third lead frame including a third terminal portion and a third extension portion extending from the third terminal portion to be located between the first lead frame and the second lead frame without overlapping with the semiconductor chips on the plane, as called for in claim 6 (claims 7-10 depend from claim 6);
wherein the preparing includes preparing additional substrates, and further includes stacking and bonding the additional substrates on a region of the lead frames that does not overlap with the semiconductor chips but overlaps with a portion of an edge portion of the insulating circuit board on the plane, as called for in claim 14;
wherein the preparing includes preparing connecting portions, and further includes connecting any one of the semiconductor chips and one of the lead frames that do not overlap with the any one of the semiconductor chips on the plane with one of the connecting portions, as called for in claim 15.
Response to Arguments
Applicant's arguments filed March 12, 2026 have been fully considered but they are not persuasive.
With respect to claims 1 and 12, the applicant argues that the examiner equates the lead frames 3e and 3c of Matsuzawa to the first and second lead frames of the presently claimed invention. And, that in the presently claimed invention, the first lead frame 131-1 and the second lead frame 131-2 are disposed on the same plane defined by the first metal layer 122 of the insulating circuit board 120. The examiner respectfully disagrees.
As outlined in the rejection above and in the previous non-final rejection dated December 12th, 2025, the first lead frame corresponds to 3e on the left in Fig. 18 of Matsuzawa and the second lead frame corresponds to 3e on the right in Fig. 18. The lead frame 3c was not cited in any rejection. The examiner agrees that lead frames 3e and 3c of Matsuzawa are not disposed on the same plane defined by the first metal layer as claimed. But, as rejected, the first lead frame (3e on left in Fig. 18) and the second lead frame (3e on right in Fig. 18) are disposed on the same plane defined by a first metal layer (52 below 51 in Fig. 18) of the insulating circuit board (5 on top in Fig. 18) (see Figs. 18, 19, and paragraphs 62, 63, 95, 97, 111; also see Fig. 18 annotated above). Therefore, independent claims 1 and 12 and their dependents remain rejected.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORDAN M KLEIN whose telephone number is (571)270-7544. The examiner can normally be reached 9:00 am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.M.K/Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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