DETAILED ACTION
This action is responsive to the Request for Continued Examination filed February 14, 2026. Claims 1-20 are pending. Claims 1, 12, and 14 have been amended. Claim 6 and 15 have been cancelled Claims 14-20 have been withdrawn from further consideration. Claims 1, and 12 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 14, 2026 has been entered.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statements (IDS) filed on
February 14, 2026, and March 30, 2026. These IDSs have been considered. However, it is noted that these IDS contain many references (such as prior Office actions for related applications among others), which appear to be only marginally relevant or cumulative to the prior art already of record. Applicant is reminded of the duty under 37 CFR 1.56 to submit only information material to patentability. Submission of large number of clearly irrelevant references is not encouraged and may hinder efficient examination. Applicant is invited to identify any particular references believed to be especially material to the examination of the claims in Applicant's application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-8, and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (“Novel 3D NOR FLASH with Single-Crystal Silicone Channel”; “Huang”) in view of Young et al. (US 20220123003; “Young”) as supported by Yan et al. (US 20200258897)
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Regarding independent claim 1, Huang discloses a memory block, comprising:
a memory array, comprising: (Abst; "A novel 3D memory array").
a plurality of memory cells distributed in a three-dimensional array (Fig. 1);
wherein the memory array comprises a plurality of memory subarray layers stacked sequentially along a height direction, and each memory subarray layer comprises a drain region semiconductor layer, a channel semiconductor layer, and a source region semiconductor layer stacked along the height direction (Fig. 2(f) where it illustrates the layers of a sub-array memory stack. Also see col. 1; "It should be mentioned that although only two-layers of vertical flash devices were experimentally demonstrated in this work, our 3D NOR flash has the potential to be stacked with dozens or even hundreds of layers. And the continuous stacking will not degrade the read current, so fast-read still can be realized." It is noted that with the additional stacking indicated, the Huang's oxide isolation layer would necessarily be between every two adjacent memory sub-array layers and analogous to the isolation layer 14a of Fig. 4 in the instant application.);
in each memory subarray layer, the drain region semiconductor layer comprises a plurality of drain region semiconductor strips distributed along a row direction, the channel semiconductor layer comprises a plurality of channel semiconductor strips distributed along the row direction, and the source region semiconductor layer comprises a plurality of source region semiconductor strips distributed along the row direction (Fig. 2a, 2f);
each drain region semiconductor strip, each channel semiconductor strip, and each source region semiconductor strip extend along a column direction (Fig. 2. It is noted that this limitation appears to merely define the drain, channel, source layer group as existing in the Y direction of the X-Y plane illustrated in Huang);
a plurality of gate strips distributed along the column direction are arranged on each side of each column drain region semiconductor strip, channel semiconductor strip, and source region semiconductor strip, each gate strip extending along the height direction (Fig. 1a, where it illustrates the geometry of a 3x3 array of gates within the 3D memory block. It is noted that the topology of the individual transistors, indicating the equivalent of 'strips' in the instant application is evinced);
in the plurality of memory subarray layers, the plurality of drain region semiconductor strips, the plurality of channel semiconductor strips, and the plurality of source region semiconductor strips, that are disposed in a same column, are defined as a column of the semiconductor strip structures (Fig. 1a. As noted above, the term "column" is defined in the instant application as the Y direction in Fig. 2a which is structurally analogous to Huang's stacked memory device);
and a plurality of drain/source connection terminal arrays (Fig. 1(a) where it illustrates the terminal arrays coupled to BL1 and BL0 for example);
wherein each of the plurality of drain/source connection terminal arrays is arranged at a predetermined interval in the column direction (Fig. 2(d) where it illustrates the stepped contact terminals at a predetermined interval in the column direction);
each drain/source connection terminal array comprises a plurality of drain/source connection terminal subarrays arranged along the row direction, and each drain/source connection terminal subarray comprises a plurality of drain/source connection terminals (Fig. 1(a) where it illustrates the contact terminals of BL0 and BL1 in the row direction);
each drain/source connection terminal is connected to a corresponding drain/source region semiconductor strip of a corresponding column of the semiconductor strip structures, wherein the corresponding drain/source region semiconductor strip is a corresponding drain region semiconductor strip or a corresponding source region semiconductor strip (Fig. 2(d) where it illustrates the tungsten contact terminals of the drain and source);
wherein in each column of the semiconductor strip structures, a same drain/source region semiconductor strip is connected to several of the plurality of drain/source connection terminals of several of the plurality of drain/source connection terminal subarrays of several of the plurality of drain/source connection terminal arrays (Fig. 1(a) where it illustrates the drain/source terminals of BL1 for example being connected to the other adjacent columns of the sub-array).
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Huang discloses the drain/source terminals of the subarrays but is silent with respect to alignment variations to optimize routing margin for layout patterning. It is noted that the two alternative limitations joined by "or" are recited: (1) aligned in the column direction; or (2) staggered in the column direction. Because the claim is satisfied by either alternative, it is sufficient to address only one species. However, for completeness, both alternatives are addressed below.
However, Young teaches wherein the plurality of drain/source connection terminal subarrays, distributed in the row direction, of each drain/source connection terminal array are aligned with each other in the column direction (Fig. 1A. See also para. 14; " The 3D memory array 100 includes a plurality of vertically stacked source lines 105 adjacent to a plurality of vertically stacked bit lines 107");
OR each adjacent two of the plurality of drain/source connection terminal subarrays, distributed in the row direction, of each drain/source connection terminal array are staggered with each other in the column direction (Fig. 1B. See also para. 22; "the word lines 109 of memory cells 125 in adjacent columns 1403 of the memory array 100 may be offset from one another having a staggered pattern from one column 1403 to the next column 1403." It is noted that if the columns are offset in a staggered pattern, the drain/source connections on the end would necessarily also be staggered. Support for the concept of staggered connection terminals for the sub-arrays taught by Young is as demonstrated in Fig. 3 of Yan and is well-known in the art.)
Huang and Young (as supported by Yan) are from the same field of endeavor as applicant’s invention directed to 3D non-volatile NOR arrays. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the drain/source connection terminals of Huang’s 3D NOR structure either to be aligned in the column direction or to be staggered in the column direction as taught by Young and supported by Yan. Doing so would enable more efficient routing to multi-tiered 3D stacked semiconductor memory sub-arrays improving device density, improving alignment margins for patterning the contacts.
Regarding claim 2, Huang and Young combined disclose the limitations of claim 1.
Huang is silent with respect to terminal sub-arrays.
However, Young teaches wherein, each drain/source connection terminal subarray corresponds to two adjacent columns of the semiconductor strip structures, and comprises a first drain/source connection terminal group and a second drain/source connection terminal group (Fig. 1A where it illustrates a group of source terminals on one column, and a group of drain terminals on adjacent columns forming a sub-array of terminals);
wherein the first drain/source connection terminal group comprises a plurality of first drain/source connection terminals, each configured to be connected to a corresponding drain/source region semiconductor strip of one of the two adjacent columns of the semiconductor strip structures; the second drain/source connection terminal group comprises a plurality of second drain/source connection terminals, each configured to be connected to a corresponding drain/source region semiconductor strip of the other of the two adjacent columns of the semiconductor strip structures (Fig. 1A. See also para. 13; "FIG. 1A illustrates a portion of the memory array 100 in a three-dimensional view, in accordance with some embodiments", "The memory array 100 includes a plurality of memory cells 125, which may be arranged in a grid of rows and columns". It is noted therefore, that a second terminal sub-array group would necessarily be the next adjacent two columns of the grid).
Regarding claim 3 and 4, Huang and Young combined disclose the limitations of claim 2.
As applied, Young further discloses wherein,
each drain/source connection terminal array comprises a plurality of first-type drain/source connection terminal subarrays and a plurality of second-type drain/source connection terminal subarrays alternately distributed along the row direction (or same column as per claim 4) (Fig. 1A where it illustrates three drain terminals and three source terminals as part of a terminal sub-array as a "first-type". It is noted that since the array 100 elements are arranged as a grid, any other array element 100 would necessarily be a "second-type");
wherein the first drain/source connection terminal group of each first-type drain/source connection terminal subarray is configured to be connected to a plurality of the drain/source region semiconductor strips in a low zone of one of the two adjacent columns of the semiconductor strip structures (para. 13; "The memory cells 125 may further stacked vertically to provide a three dimensional memory array, thereby increasing device density." It is noted that the term "low zone" in the instant application appears to be directed at Fig. 46 which indicates that it is the bottom stack (F1) of memory cells. Therefore the "first type" terminal sub-array in Young's bottom element would be in a "low zone");
the second drain/source connection terminal group of each first-type drain/source connection terminal subarray is configured to be connected to a plurality of the drain/source region semiconductor strips in a low zone of the other of the two adjacent columns of the semiconductor strip structures (para. 13; "The memory array 100 includes a plurality of memory cells 125, which may be arranged in a grid of rows and columns". It is noted that the second terminal sub-array group next to the first group on the bottom would also be in the "low zone");
wherein the first drain/source connection terminal group of each second-type drain/source connection terminal subarray is configured to be connected to a plurality of the drain/source region semiconductor strips in a high zone of one of the two adjacent columns of the semiconductor strip structures (para. 13; "The memory cells 125 may further stacked vertically to provide a three dimensional memory array, thereby increasing device density." It is noted that the term "high zone" in the instant application appears to be directed at Fig. 46 which indicates that it is the top stack (F2) of memory cells. Therefore the "first type" terminal sub-array in Young's top element would be in a "high zone");
the second drain/source connection terminal group of each second-type drain/source connection terminal subarray is configured to be connected to a plurality of the drain/source region semiconductor strips in a high zone of the other of the two adjacent columns of the semiconductor strip structures (para. 13; "The memory array 100 includes a plurality of memory cells 125, which may be arranged in a grid of rows and columns". It is noted that the second terminal sub-array group next to the first group on the top would also be in the "high zone").
It is noted that claim 3 appears to be directed to alternating the terminal sub-arrays along the Y-axis whereas claim 4 appears to be directed to alternating the terminal sub-arrays along the X-axis. Combined, claims 3 and 4 combined are interpreted as forming a “checkerboard” pattern of terminal sub-arrays.
Regarding claim 5, Huang and Young combined disclose the limitations of claim 1.
As applied, Huang further discloses wherein the memory block satisfies at least one of:
the drain/source region semiconductor strips of each column of the semiconductor strip structures are respectively connected to several of the plurality of drain/source connection terminals of two adjacent drain/source connection end subarrays in the row direction; (Fig. 1(a) where it illustrates drain terminals BL0 and BL1 and source terminal SL connecting to adjacent drain/source connections on either side (i.e. row direction)).
and the drain/source region semiconductor strips of each column of the semiconductor strip structures are respectively connected to several of the plurality of drain/source connection ends of two adjacent drain/source connection end subarrays in the column direction (It is noted that the row direction connection as above is satisfied).
Regarding claim 7, Huang and Young combined disclose the limitations of claim 1.
As applied, Young further discloses wherein the plurality of gate strips in adjacent two columns are staggered in the row direction (para. 22; "the word lines 109 of memory cells 125 in adjacent columns 1403 of the memory array 100 may be offset from one another having a staggered pattern from one column 1403 to the next column 1403." It is noted that if the columns are offset in a staggered pattern, the rows are also staggered and the drain/source connections on the end would necessarily also be staggered);
or the plurality of gate strips in adjacent two columns are aligned in the row direction (Fig. 1B where it illustrates the gate strips to be aligned in the row direction).
Regarding claim 8, Huang and Young combined disclose the limitations of claim 1.
As applied, Young further discloses wherein a plurality of isolation walls distributed along the column direction are arranged on each of two sides of each column of the semiconductor strip structures (Fig. 1A:117. See also para 57; "The array spacers 117 and the gate isolation plugs 115 are formed of dielectric materials");
each isolation wall extends along the height direction to a substrate to separate at least parts of two corresponding adjacent columns of the semiconductor strip structures (Fig. 1A where it shows the spacers extending in the height direction and separating the array columns).
Regarding claim 10, Huang and Young combined disclose the limitations of claim 1.
As applied, Young further discloses wherein, the plurality of drain/source semiconductor strips are distributed in a step-like manner from top to bottom in positions of the plurality of drain/source connection terminal subarrays in each column of semiconductor strip structures (Fig. 1A: SL & BL);
Young is silent with respect to insulating layers arranged on the drain/source strips.
However, Huang teaches an insulating layer is arranged on the plurality of the drain/source region semiconductor strips that are step-like, and a filling material is arranged on the insulating layer (Fig. 2(c) where it illustrates an oxide spacer and Fig. 2(d) filling material (tungsten));
the filling material comprises a polysilicon filling material (Fig. 2(d)).
Huang does not expressly indicate the “filling” material as polycrystalline silicon.
However, Huang discloses tungsten plugs forming the “filling” material.
In the field of 3D memory device manufacturing, it is well understood that there are many possible electrically conducting materials which may be used to form connecting layers of which polycrystalline silicon (polysilicon) and tungsten are both common material variants exhibiting similar deposition and conduction suitability as filling layers.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement a connecting layer using tungsten instead of polysilicon, because tungsten and polysilicon are obvious variants due to their analogous material characteristics with respect to memory device manufacturing.
Regarding claim 11, Huang and Young combined disclose the limitations of claim 1.
As applied, Huang further discloses wherein
each drain region semiconductor strip, channel semiconductor strip, and source region semiconductor strip comprises a body structure and a plurality of protrusions arranged and spaced on two sides of the body structure (Fig. 2(b) where it illustrates the drain source and channel (body), each strip layer protruding beyond the contact holes);
each protrusion extends in the column direction from the body structure toward a corresponding gate strip in a direction deviating from the body structure (Fig. 2(e) and 2(f) where the protrusions extend to the gate strip in the column direction and the gate strip is perpendicular (deviating) from the channel (body)).
Regarding independent claim 12, Huang discloses a memory block, comprising:
a memory array, comprising (Abst; "A novel 3D memory array"):
a plurality of memory cells distributed in a three-dimensional array (Fig. 1);
wherein the memory array comprises a plurality of memory subarray layers stacked sequentially along a height direction, and each memory subarray layer comprises a drain region semiconductor layer, a channel semiconductor layer, and a source region semiconductor layer stacked along the height direction (Fig. 2(f) where it illustrates the layers of a sub-array memory stack. Also see col. 1; "It should be mentioned that although only two-layers of vertical flash devices were experimentally demonstrated in this work, our 3D NOR flash has the potential to be stacked with dozens or even hundreds of layers. And the continuous stacking will not degrade the read current, so fast-read still can be realized." It is noted that with the additional stacking indicated, the Huang's oxide isolation layer would necessarily be between every two adjacent memory sub-array layers and analogous to the isolation layer 14a of Fig. 4 in the instant application.);
in each memory subarray layer, the drain region semiconductor layer comprises a plurality of drain region semiconductor strips distributed along a row direction, the channel semiconductor layer comprises a plurality of channel semiconductor strips distributed along the row direction, and the source region semiconductor layer comprises a plurality of source region semiconductor strips distributed along the row direction (Fig. 2a, 2f);
each drain region semiconductor strip, each channel semiconductor strip, and each source region semiconductor strip extend along a column direction (Fig. 2. It is noted that this limitation appears to merely define the drain, channel, source layer group as existing in the Y direction of the X-Y plane illustrated in Huang);
a plurality of gate strips distributed along the column direction are arranged on each side of each column drain region semiconductor strip, channel semiconductor strip, and source region semiconductor strip, each gate strip extending along the height direction (Fig. 1a, where it illustrates the geometry of a 3x3 array of gates within the 3D memory block. It is noted that the topology of the individual transistors, indicating the equivalent of 'strips' in the instant application is evinced);
in the plurality of memory subarray layers, the plurality of drain region semiconductor strips, the plurality of channel semiconductor strips, and the plurality of source region semiconductor strips, that are disposed in a same column, are defined as a column of the semiconductor strip structures (Fig. 1a. As noted above, the term "column" is defined in the instant application as the Y direction in Fig. 2a which is structurally analogous to Huang's stacked memory device);
and a drain/source connection terminal array, comprising a plurality of drain/source connection terminal subarrays (Fig. 1(a) where it illustrates the terminal arrays coupled to BL1 and BL0 for example);
wherein each drain/source connection terminal subarray comprises a plurality of drain/source connection terminals arranged along the row direction; (Fig. 1(a) where it illustrates the contact terminals of BL0 and BL1 in the row direction).
each drain/source connection terminal is connected to a corresponding drain/source region semiconductor strip of a corresponding column of the semiconductor strip structures (Fig. 2(d) where it illustrates the tungsten contact terminals of the drain and source),
wherein the corresponding drain/source region semiconductor strip is a corresponding drain region semiconductor strip or a corresponding source region semiconductor strip (Fig. 1(a) where it illustrates the drain/source terminals of BL1 for example being connected to the other adjacent columns of the sub-array).
Huang discloses the drain/source terminals of the subarrays but is silent with respect to alignment variations to optimize routing margin for layout patterning. It is noted that the two alternative limitations joined by "or" are recited: (1) aligned in the column direction; or (2) staggered in the column direction. Because the claim is satisfied by either alternative, it is sufficient to address only one species. However, for completeness, both alternatives are addressed below.
However, Young teaches wherein the plurality of drain/source connection terminal subarrays, distributed in the row direction, of each drain/source connection terminal array are aligned with each other in the column direction (Fig. 1A. See also para. 14; " The 3D memory array 100 includes a plurality of vertically stacked source lines 105 adjacent to a plurality of vertically stacked bit lines 107");
OR each adjacent two of the plurality of drain/source connection terminal subarrays, distributed in the row direction, of each drain/source connection terminal array are staggered with each other in the column direction (Fig. 1B. See also para. 22; "the word lines 109 of memory cells 125 in adjacent columns 1403 of the memory array 100 may be offset from one another having a staggered pattern from one column 1403 to the next column 1403." It is noted that if the columns are offset in a staggered pattern, the drain/source connections on the end would necessarily also be staggered. Support for the concept of staggered connection terminals for the sub-arrays taught by Young is as demonstrated in Fig. 3 of Yan and is well-known in the art.)
Huang and Young (as supported by Yan) are from the same field of endeavor as applicant’s invention directed to 3D non-volatile NOR arrays. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the drain/source connection terminals of Huang’s 3D NOR structure either to be aligned in the column direction or to be staggered in the column direction as taught by Young and supported by Yan. Doing so would enable more efficient routing to multi-tiered 3D stacked semiconductor memory sub-arrays improving device density, improving alignment margins for patterning the contacts.
Claims 9 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (“Novel 3D NOR FLASH with Single-Crystal Silicone Channel”; “Huang”) in view of Young et al. (US 20220123003; “Young”) as supported by Yan et al. (US 20200258897), and further in view of Matsumoto et al. (US 20200251490; “Matsumoto”).
Regarding claim 9, Huang and Young in combination disclose the limitations of claim 2.
Huang and Young are silent with respect to drain/source connection terminals sharing the same hole.
However, Matsumoto teaches wherein the first drain/source connection terminal group and the second drain/source connection terminal group in each drain/source region connection terminal subarray share a same drain/source hole (Fig. 7 where it illustrates a lower connection area hole STL and an upper connection area hole STU. It is noted that this limitation appears to be directed to Fig. 54 and spec. para. 335 of the instant application. For examination purposes, the term "drain/source hole" is interpreted to mean the "staircase" area void where the drain and source contacts are placed for a given sub-array tier of memory cells. This is a well understood technique in the art for stacked 3D semiconductor devices to overcome the problem of limited verticality of etch profiles in reaching deep sub-tier levels).
Huang and Young combined and Matsumoto are from the same field of endeavor as applicant’s invention directed to 3D semiconductor devices. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Huang and Young’s array terminals with the teachings of Matsumoto’s stacked pillar terminals on a stair step structure to position the terminals on different tiers of the device. Doing so would improve manufacturability and contactability of the terminals using conventional semiconductor fabrication techniques.
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Regarding claim 13, Huang and Young disclose the limitations of claim 12.
Huang and Young are silent with respect to positioning of the terminal arrays with respect to the explicit orientation of the sub-array.
However, Matsumoto teaches the drain/source connection terminal array is arranged at a non-edge position of the corresponding column of the semiconductor strip structures in the column direction (Fig. 7 where it illustrates a lower connection area hole STL but the connection terminals do not extend to the edge of the structure).
Huang, Young and Matsumoto are from the same field of endeavor as applicant’s invention directed to 3D semiconductor devices. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Huang’s NOR array with the teachings of Matsumoto’s stacked pillar terminals on a stair step structure to position the terminals away from the edge of the device. Doing so would improve manufacturability and data reliability by avoiding material variability issues near semiconductor boundaries.
Response to Arguments
Applicant's arguments filed February 14, 2026, have been fully considered but they are not persuasive because, while the applicant's contention on pg. 14 Remarks that the amendments to independent claim 1 and 12 (which narrowed the claim scope) are not disclosed by the previously applied references, new facts of the applied prior art combined with the new features resulting in a new supporting reference, remains unpatentable under a new ground of rejection.
Applicant contends that the anticipation rejection of independent claims 1 and 12 is improper because the previously applied prior art fails to teach the feature of various alignments of the drain/source terminals (put forth as distinguishing technical feature A) and also does not teach a semiconductor strip structure (put forth as distinguishing technical feature B).
To support their argument, applicant asserts four reasons:
Huang does not demonstrate the various alignments of the drain/source contacts. As noted in the rejection for independent claims 1 and 12 above, it is noted that since the various alignment configurations are presented in the alternative, only one must be demonstrated to satisfy the claim. However, a new fact pattern from a previously applied reference along with an additional supporting reference have been applied to the rejection rendering this argument moot.
Young fails to make up the deficiency.Young's figure 1A clearly illustrates the source/drain terminals in the aligned configuration. Only one of the alternative configurations is needed to satisfy the claim, and as such, Young reads on the limitation.
Huang fails to disclose the feature of semiconductor strips.Applicant concludes that Huang's plane(s) are not shown as divided into several strips and therefore no intervals along the row direction are disclosed. Fundamentally, it is observed that the claimed invention is an apparatus with a defined 3D structure that forms the topology of transistor NOR pairs as illustrated in FIG. 13 of the instant application. Part of that topology necessarily includes various physical isolation structures as evinced by the resultant specific connectivity of the transistors as seen in FIG. 13 which form said NOR pairs. An explicit example of one of the isolation structures in the instant application are the isolation walls (3) as shown in Fig. 4. However, while it is agreed that the illustration depicted as Fig. 1(a) of Huang does not show explicit isolation structures between the "rows" of stacked transistor NOR pairs, the representative schematic disclosed as Fig. 1(b) (which is exactly the same fundamental building block topology as the instant application) implicitly identifies it as necessarily part of the structure. Additionally, the specific forming of the isolation structures are drawn to a non-elected invention being that of the manufacturing of the apparatus, and therefore not within the scope of the claimed limitations. Having therefore established that there is, in fact, isolation between the transistors, Huang reads on the limitation.
The apparatus of Huang is not manufactured with the same processes as disclosed in the instant application. It is noted that the method of manufacturing the apparatus is not within the scope of the elected invention and therefore does not distinguish from the applied prior art.
For at least these reasons, the rejections of independent claims 1 and 12 are deemed proper and maintained.
Conclusion
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/James S. Wells/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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