DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/22/2022 is being considered by the examiner.
Drawings
The drawings submitted on 12/22/2022 is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 9, 11-17, 19, 20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Mann et al. (US 20190355730 A1).
Regarding claim 1, Mann discloses a multi-layer integrated circuit (IC) structure comprising:
a cell comprising a cell boundary defined by a plurality of transistor-gate pitch (TGP) regions (61-63) annotated below and an in-line contact region (around 70); ([0030], [0037], Fig. 3A) wherein
the plurality of TGP regions (61-63) comprises a reduced-area TGP region (61, annotated below) and non-reduced-area TGP regions (63, annotated below); and wherein
the reduced-area TGP region (61) is less than each of the non-reduced-area TGP regions (63); (Fig. 1 and 3A) and
an in-line contact (70) within the in-line contact region (around 70) and operable to electrically couple to a source or drain (S/D) region (18/20 and 50/52) within the in-line contact region (around 70 annotated below). (Fig. 3A)
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Regarding claim 2, Mann discloses the IC structure of claim 1 further comprising a vertical transport field effect transistor (VTFET). ([0005], Fig. 3A)
Regarding claim 3, Mann discloses the IC structure of claim 2 wherein the S/D region (18/20 and 50/52) comprises a bottom S/D region (18 and 20) of the VTFET (61-63) having a first portion (annotated below) in the reduced-area TGP region (61) and a second portion (annotated below) in the in-line contact region (around 70). (Fig. 3A)
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Regarding claim 4, Mann discloses the IC structure of claim 2, wherein the in-line contact region (around 70) is adjacent to an end region (left) of the VTFET in the reduced-area TGP region (61). (Fig. 3A)
Regarding claim 5, Mann discloses the IC structure of claim 1, wherein the in-line contact region (around 70) is adjacent at least one of the non-reduced-area TGP regions (63). (Fig. 3A)
Regarding claim 6, Mann discloses the IC structure of claim 1, wherein the in-line contact (70) comprises a width dimension that is less than about one TGP (61). (Fig. 3A)
Regarding claim 7, Mann discloses the IC structure of claim 2, wherein the VTFET (61-63) is electrically connect to a backside power supply (VSS). ([0034], Fig. 3A)
Regarding claim 9, Mann discloses the IC structure of claim 1 further comprising a first fin (11) in the reduced-area TGP region (61) and a second fin (13) in at least one of the non-reduced-area TGP regions (63), wherein a length dimension of the first fin (11) is less than a length dimension of the second fin (13). (Fig. 1 and 3A)
Regarding claim 11, Mann discloses a multi-layer integrated circuit (IC) structure comprising:
a cell comprising a cell boundary defined by a plurality of transistor-gate pitch (TGP) regions (61-63) annotated below and an in-line contact region (around 70); ([0030], [0037], Fig. 3A) wherein
the plurality of TGP regions (61-63) comprises a reduced-area TGP region (61, annotated below) and non-reduced-area TGP regions (63, annotated below); and wherein
the reduced-area TGP region (61) is less than each of the non-reduced-area TGP regions (63); (Fig. 1 and 3A) and
an in-line contact (70) within the in-line contact region (around 70) and operable to electrically couple a power supply (VSS) to a source or drain (S/D) region (18/20 and 50/52) within the cell and outside the in-line contact region (around 70, annotated below). (Fig. 3A)
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Regarding claim 12, Mann discloses the IC structure of claim 11 further comprising a vertical transport field effect transistor (VTFET). ([0005], Fig. 3A)
Regarding claim 13, Mann discloses the IC structure of claim 12 wherein the S/D region (18/20 and 50/52) comprise a top S/D region (50 and 52) of the VTFET (61-63), wherein top S/D region (50 and 52) is within the cell (80), outside the in-line contact region (around 70), and connected by a contact (per [0033]) to the in-line contact region (around 70). (Fig. 3A)
Regarding claim 14, Mann discloses the IC structure of claim 13, wherein the top S/D region (50 and 52) of the VTFET (61-63) is within at least one of the non-reduced-area TGP regions (63). (Fig. 3A)
Regarding claim 15, Mann discloses the IC structure of claim 11, wherein the in-line contact region (around 70) is adjacent the reduced-area TGP region (61). (Fig. 3A)
Regarding claim 16, Mann discloses the IC structure of claim 11, wherein the in-line contact region (around 70) is adjacent at least one of the non-reduced-area TGP regions (63). (Fig. 3A)
Regarding claim 17, Mann discloses the IC structure of claim 11 further comprising a first fin (11) in the reduced-area TGP region (61) and a second fin (13) in at least one of the non-reduced-area TGP regions (63), wherein a length dimension of the first fin (11) is less than a length dimension of the second fin (13). (Fig. 1 and 3A)
Regarding claim 19, Mann discloses the IC structure of claim 11, wherein the in-line contact (70) comprises a width dimension that is less than about one TGP (61). (Fig. 3A)
Regarding claim 20, Mann discloses a method of forming a multi-layer integrated circuit (IC) structure comprising:
forming a cell comprising a cell boundary defined by a plurality of transistor-gate pitch (TGP) regions (61-63) annotated below and an in-line contact region (around 70); ([0030], [0037], Fig. 3A) wherein
the plurality of TGP regions (61-63) comprises a reduced-area TGP region (61, annotated below) and non-reduced-area TGP regions (63, annotated below); and wherein
the reduced-area TGP region (61) is less than each of the non-reduced-area TGP regions (63); (Fig. 1 and 3A) and
forming an in-line contact (70) within the in-line contact region (around 70) and operable to electrically couple to a source or drain (S/D) region (18/20 and 50/52) within the in-line contact region (around 70, annotated below). (Fig. 3A)
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Mann et al. (US 20190355730 A1) as applied to claim 2 above, and further in view of Anderson et al. (US 9859898 B1).
Regarding claim 8, Mann discloses the IC structure of claim 2. Mann does not disclose wherein the in-line contact is operable to pass an output signal from the VTFET.
However, Anderson discloses:
the in-line contact (Vdd) is operable to pass an output signal from the VTFET (VFET). (col. 4, lns. 34-49)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Mann and Anderson for the in-line contact is operable to pass an output signal from the VTFET in order to “to achieve a reduced FET device footprint without compromising necessary FET device performance characteristics.” (Anderson, col. 1, lns. 26-28)
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Mann et al. (US 20190355730 A1) as applied to claim 1 above, and further in view of Kang et al. (US 20240204107 A1).
Regarding claim 10, Mann discloses the IC structure of claim 1. Mann does not disclose wherein the in-line contact is electrically connected to a metal wiring layer above the in-line contact.
However, Kang discloses:
the in-line contact (PRVA) is electrically connected to a metal wiring layer (195) above the in-line contact (PRVA). ([0140], Fig. 2)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Mann and Kang for the in-line contact is electrically connected to a metal wiring layer above the in-line contact in order because” there is a desire for research for reducing the capacitance between contacts in the semiconductor device and ensuring electrical stability.” (Kang, [0005]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Mann et al. (US 20190355730 A1) as applied to claim 1 above, and further in view of Chien et al. (US 20200402979 A1).
Regarding claim 18, Mann discloses the IC structure of claim 11. Mann does not explicitly disclose wherein the power supply comprises a backside power supply.
However, Chien discloses:
“The base layer 12 and interconnect layer 14 are often called a front-end structure and a backend structure, respectively, because they are the respective “front end of line” (FEOL) and “back end of line” (BEOL) in the semiconductor fabrication process” (per [0024], Fig. 1) which leads the examiner to believe the power supply (VSS) in Mann Fig. 3A is formed as part of the back structure (also since the Figs. appear to progress in manufacturing from Fig. 1A, the examiner thinks the addition of the power supply in Fig. 3A is the one of the last steps for the backside of the structure.)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Mann and Chien for the power supply comprises a backside power supply in order to “to optimize delay or power in various circuits and devices” (Chien, [0020])
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897