DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 05/11/2026 have been fully considered but they are not persuasive.
Regarding Applicants argument, “Mann paragraph [0037] describes local interconnects 70 and 72 that couple bottom source and drain regions to gates. These disclosures identify individual transistors, fins, gates, source and drain regions, and local interconnects. They do not identify VTFETs 61 through 63 as transistor-gate pitch regions. This distinction matters because a transistor and a transistor- gate pitch region are not the same claimed structure.” The examiner wants to further clarify that the claim calls out a “transistor gate pitch region” and per the examiner’s annotations of Mann’s Fig. 3A, the VTFETS 64-67 have gates 40-47 with spacing between them (where the examiner annotated in the action below) and used the labeling of the VTFETS as “transistor gate pitch regions” for which the spacing is in the region of the VTFETS. A better annotation using Fig. 3B is included below to further clarify the examiners claim mapping to Fig. 3A:
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Regarding the Applicants argument, “transistor-gate pitch region is tied to a pitch relationship between gates of adjacent transistors. Thus, the Examiner's mapping treats individual Mann transistors as though they were the claimed transistor-gate pitch regions, without identifying any disclosure in Mann that defines those alleged regions by transistor-gate pitch.” The examiner further clarifies that the pitch is the spacing between adjacent transistors however, the examiners labeled VTFETS in the rejection below as the gate pitch region i.e. where the gate pitch is located but not the gate pitch itself.
Regarding Applicants argument, “Mann does not identify VTFET 61, VTFET 62, or VTFET 63 as a transistor-gate pitch region, does not describe those VTFETs as defining a cell boundary, and does not disclose a plurality of transistor-gate pitch regions that includes one reduced-area TGP region and multiple non-reduced-area TGP regions. Mann also does not disclose that any alleged reduced-area TGP region is less than each alleged non-reduced-area TGP region.” The examiner wants to address every point of this argument individually. First, Mann discloses in [0002], “An SRAM device includes an array of bit cells in which each bit cell retains a single bit of data during operation. Each SRAM bit cell may include a pair of cross-coupled inverters and a pair of access transistors connecting the inverters to complementary bit lines. The two access transistors are controlled by word lines, which are used to select the SRAM cell for read or write operations.” Based on this disclosure the examiner is led to believe that all SRAMS have more than one cell with a cell boundary. Next, Mann’s Fig. 3A and 3B (annotated above) are multiple cross sections of Fig. 1 and show multiple “non-reduced gate pitch regions in Fig. 3A and 3B and at least 1 “reduced transistor gate pitch region”. Also, “the term “less” is unclear so the examiner is using an interpretation that a spacing between the gates of the adjacent VTFETS as the width of the “reduced transistor gate pitch region” (where the examiner labels in Fig. 3B above) is less than a width or the “non-reduced transistor gate pitch labeled in Fig. 3A and 3B above. Note that in Paragraph [0022] “A two-port SRAM that may be formed using the fins 10-17 has a two contacted (poly) pitch (2CPP) structure relating to the arrangement of the subsequently-formed gates in association with the fins 10-17” and in [0025], “ Each of the gates 40-47 surrounds all sides of a respective one of the fins 10-17 in a gate-all-around (GAA) arrangement.” This disclosure leads the examiner to believe that the layout of the fins and gates are in a pitched arrangement of 2CPP and therefore discloses these transistors as having a pitch between them. The rejection still holds.
Regarding applicants’ arguments,” Mann paragraphs [0030] and [0037] identify gates and local interconnects, but they do not disclose a pitch region measured or defined from a point on one transistor gate to a corresponding point on an adjacent transistor gate. The cited portions of Mann therefore do not provide the structural disclosure required by the claims.” And “The cited figures do not remedy the defect. An annotated figure can illustrate the Examiner's theory, but it cannot supply a missing disclosure from Mann.” The examiner disagrees because MPEP 2125, “Drawings and pictures can anticipate claims if they clearly show the structure which is claimed. In re Mraz, 455 F.2d 1069, 173 USPQ 25 (CCPA 1972).”
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “the reduced-area TGP region is less than each of the non-reduced-area TGP regions” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 9, 11-17, 19, 20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Mann et al. (US 20190355730 A1).
Regarding claim 1, Mann discloses a multi-layer integrated circuit (IC) structure comprising:
a cell comprising a cell boundary defined by a plurality of transistor-gate pitch (TGP) regions (61-63) and an in-line contact region (around 70); ([0030], [0037], Fig. 3A) wherein
the plurality of TGP regions (61-63) comprises a reduced-area TGP region (61) and non-reduced-area TGP regions (63); and wherein
the reduced-area TGP region (61) is less than each of the non-reduced-area TGP regions (63); (Fig. 1 and 3A) and
an in-line contact (70) within the in-line contact region (around 70) and operable to electrically couple to a source or drain (S/D) region (18/20 and 50/52) within the in-line contact region (around 70). (Fig. 3A)
Regarding claim 2, Mann discloses the IC structure of claim 1 wherein each TGP region (annotated in Fig. 3A and 3B above in the response to arguments) of the plurality of TGP regions is defined by a gate-to-gate pitch measured from a point on a gate of a first transistor to a corresponding point on a gate of a second transistor adjacent to the first transistor ([0022] and [0025], Fig. 3A)
Regarding claim 3, Mann discloses the IC structure of claim 1, further comprising a vertical field effect transistor (VTFET), (per [0005]) wherein the S/D region (18/20 and 50/52) comprises a bottom S/D region (18 and 20) of the VTFET (61-63) having a first portion in the reduced-area TGP region (61) and a second portion in the in-line contact region (around 70). (Fig. 3A)
Regarding claim 4, Mann discloses the IC structure of claim 2, wherein the in-line contact region (around 70) is adjacent to an end region (left) of the VTFET in the reduced-area TGP region (61). (Fig. 3A)
Regarding claim 5, Mann discloses the IC structure of claim 1, wherein the in-line contact region (around 70) is adjacent at least one of the non-reduced-area TGP regions (63). (Fig. 3A)
Regarding claim 6, Mann discloses the IC structure of claim 1, wherein the in-line contact (70) comprises a width dimension that is less than about one TGP (61). (Fig. 3A)
Regarding claim 7, Mann discloses the IC structure of claim 2, wherein the VTFET (61-63) is electrically connect to a backside power supply (VSS). ([0034], Fig. 3A)
Regarding claim 9, Mann discloses the IC structure of claim 1 further comprising a first fin (11) in the reduced-area TGP region (61) and a second fin (13) in at least one of the non-reduced-area TGP regions (63), wherein a length dimension of the first fin (11) is less than a length dimension of the second fin (13). (Fig. 1 and 3A)
Regarding claim 11, Mann discloses a multi-layer integrated circuit (IC) structure comprising:
a cell comprising a cell boundary defined by a plurality of transistor-gate pitch (TGP) regions (61-63) and an in-line contact region (around 70); ([0030], [0037], Fig. 3A) wherein
the plurality of TGP regions (61-63) comprises a reduced-area TGP region (61) and non-reduced-area TGP regions (63); and wherein
the reduced-area TGP region (61) is less than each of the non-reduced-area TGP regions (63); (Fig. 1 and 3A) and
an in-line contact (70) within the in-line contact region (around 70) and operable to electrically couple a power supply (VSS) to a source or drain (S/D) region (18/20 and 50/52) within the cell and outside the in-line contact region (around 70). (Fig. 3A)
Regarding claim 12, Mann discloses the IC structure of claim 11, wherein each TGP region (annotated in Fig. 3A and 3B above in the response to argument section) of the plurality of TGP regions is defined by a gate-to-gate pitch measured from a point on a gate of a first transistor to a corresponding point on a gate of a second transistor adjacent to the first transistor ([0022] and [0025], Fig. 3A and 3B)
Regarding claim 13, Mann discloses the IC structure of claim 11, further comprising a vertical transport field effect transistor (VTFET), (per [0005]) wherein the S/D region (18/20 and 50/52) comprise a top S/D region (50 and 52) of the VTFET (61-63), wherein top S/D region (50 and 52) is within the cell (80), outside the in-line contact region (around 70), and connected by a contact (per [0033]) to the in-line contact region (around 70). (Fig. 3A)
Regarding claim 14, Mann discloses the IC structure of claim 13, wherein the top S/D region (50 and 52) of the VTFET (61-63) is within at least one of the non-reduced-area TGP regions (63). (Fig. 3A)
Regarding claim 15, Mann discloses the IC structure of claim 11, wherein the in-line contact region (around 70) is adjacent the reduced-area TGP region (61). (Fig. 3A)
Regarding claim 16, Mann discloses the IC structure of claim 11, wherein the in-line contact region (around 70) is adjacent at least one of the non-reduced-area TGP regions (63). (Fig. 3A)
Regarding claim 17, Mann discloses the IC structure of claim 11 further comprising a first fin (11) in the reduced-area TGP region (61) and a second fin (13) in at least one of the non-reduced-area TGP regions (63), wherein a length dimension of the first fin (11) is less than a length dimension of the second fin (13). (Fig. 1 and 3A)
Regarding claim 19, Mann discloses the IC structure of claim 11, wherein the in-line contact (70) comprises a width dimension that is less than about one TGP (61). (Fig. 3A)
Regarding claim 20, Mann discloses a method of forming a multi-layer integrated circuit (IC) structure comprising:
forming a cell comprising a cell boundary defined by a plurality of transistor-gate pitch (TGP) regions (61-63) and an in-line contact region (around 70); ([0030], [0037], Fig. 3A) wherein
the plurality of TGP regions (61-63) comprises a reduced-area TGP region (61) and non-reduced-area TGP regions (63); and wherein
the reduced-area TGP region (61) is less than each of the non-reduced-area TGP regions (63); (Fig. 1 and 3A) and
forming an in-line contact (70) within the in-line contact region (around 70) and operable to electrically couple to a source or drain (S/D) region (18/20 and 50/52) within the in-line contact region (around 70). (Fig. 3A)
Regarding claim 21, Mann discloses the method of claim 20, wherein each TGP region of the plurality of TGP regions is defined by a pitch from a point on a gate of a first transistor to a corresponding point on a gate of a second transistor adjacent to the first transistor. (Fig. 3B)
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Mann et al. (US 20190355730 A1) as applied to claim 2 above, and further in view of Anderson et al. (US 9859898 B1).
Regarding claim 8, Mann discloses the IC structure of claim 2. Mann does not disclose wherein the in-line contact is operable to pass an output signal from the VTFET.
However, Anderson discloses:
the in-line contact (Vdd) is operable to pass an output signal from the VTFET (VFET). (col. 4, lns. 34-49)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Mann and Anderson for the in-line contact is operable to pass an output signal from the VTFET in order to “to achieve a reduced FET device footprint without compromising necessary FET device performance characteristics.” (Anderson, col. 1, lns. 26-28)
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Mann et al. (US 20190355730 A1) as applied to claim 1 above, and further in view of Kang et al. (US 20240204107 A1).
Regarding claim 10, Mann discloses the IC structure of claim 1. Mann does not disclose wherein the in-line contact is electrically connected to a metal wiring layer above the in-line contact.
However, Kang discloses:
the in-line contact (PRVA) is electrically connected to a metal wiring layer (195) above the in-line contact (PRVA). ([0140], Fig. 2)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Mann and Kang for the in-line contact is electrically connected to a metal wiring layer above the in-line contact in order because” there is a desire for research for reducing the capacitance between contacts in the semiconductor device and ensuring electrical stability.” (Kang, [0005]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Mann et al. (US 20190355730 A1) as applied to claim 1 above, and further in view of Chien et al. (US 20200402979 A1).
Regarding claim 18, Mann discloses the IC structure of claim 11,wherein
the in-line contact (72) comprises a width dimension that is less than about one TGP. (Fig. 3B)
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Mann does not explicitly disclose
wherein the power supply comprises a backside power supply
However, Chien discloses:
“The base layer 12 and interconnect layer 14 are often called a front-end structure and a backend structure, respectively, because they are the respective “front end of line” (FEOL) and “back end of line” (BEOL) in the semiconductor fabrication process” (per [0024], Fig. 1) which leads the examiner to believe the power supply (VSS) in Mann Fig. 3A is formed as part of the back structure (also since the Figs. appear to progress in manufacturing from Fig. 1A, the examiner thinks the addition of the power supply in Fig. 3A is the one of the last steps for the backside of the structure.)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Mann and Chien for the power supply comprises a backside power supply in order to “to optimize delay or power in various circuits and devices” (Chien, [0020])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Anderson et al. (US 20170244412 A1) discloses, “ In other words, VTFETs can potentially provide electronic devices comprising logic circuits with improved circuit density. Such logic circuits can be characterized by a lower-number CPP (cell gate pitch)” in [0007] and similar to claims 2, 12 and 21 of the present application, “gate pitch can be defined to be equal to: (distance between uncontacted gates)/2. More specifically, a pitch can be determined by adding the space between two features to the width of one of the features, creating an allowable “pitch” in [0029] and therefore having significant relevance to some of the claims as they currently read.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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