DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s amendment filed on 01/21/26 is acknowledged and papers submitted have been placed in the records.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-40 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Independent claims 1, 19 and 32 each recites “wherein the first logic die and the first RDL structure are formed by wafer-level processes, and a size/pitch of routings of the first RDL structure is smaller than a size/pitch of routings of the second substrate.” (emphasis added). The support of the quoted limitation is unclear in view of the original disclosure. First, it is unclear what the expression “a size/pitch” really means. Is it “a size or pitch” or is it “a size and pitch”? It was used only once in the specification in [0019] of the PGPub of this application and it is was not to compare the size/pitch of routings the first RDL structure and the size/pitch of routings of the second substrate as recited in the amended claims. Further, it is unclear where a comparison between the size/pitch of routings the first RDL structure and the size/pitch of routings of the second substrate as recited in the amended claims, is made in the original disclosure with an explicit and unambiguous support based on the drawings. Furthermore, only the routings (318&320; see [0027] of the PGPub of this application) of the first RDL structure (316) is defined, so, it is unclear what are the routings of the second substrate and how their size/pitch compare to the size/pitch of the second substrate. Finally, the pitches described are P1 (pitch between TV interconnects 314; see [0032] of the PGPub of this application for example) and P2 (pitch between solder connector 442; see [0032] of the PGPub of this application for example), but those pitches do not appear to have anything to do with the pitches claimed and their comparison thereof.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 5-6, 8-13, 15-16, 32 and 36-39 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2021/0098380, previously used).
a. Re claim 1, Chen et al. disclose a semiconductor package assembly, comprising: a fan-out package 200 (see fig. 23 and related text as well as remaining of disclosure for more details), comprising: a first redistribution layer (RDL) structure 222 (see fig. 16, [0061]-[0068]) having a top surface and a bottom surface; a first logic die (logic die 50; see [0014]) having first pads 46 (fig. 1, [0018]) thereon, wherein the first pads are in contact with the top surface of the first RDL structure; through via (TV) interconnects 216 ([0055]) surrounding the first logic die and electrically connected to the first RDL structure; and first conductive structures 238 ([0069]) in contact with the bottom surface of the first RDL structure; a memory package 350 ([0077]) stacked on the fan-out package, comprising: a first substrate 302&304&306&308 (fig. 21, [0078]-[0082]) having a top surface and a bottom surface; a memory die 310A mounted on the top surface of the first substrate; and second conductive structures 252 (figs. 20-21, [0075]) on the bottom surface of the first substrate, wherein the memory die is electrically connected to the first logic die using the second conductive structures, the TV interconnects and the first RDL structure (explicit on fig. 23 and related text); and a second substrate 450 ([0089]-[0095]) provided for the fan-out package stack thereon, wherein the second substrate is electrically connected to the first logic die using the first conductive structures (explicit on fig. 23 and related text), wherein “the first logic die and the first RDL structure are formed by wafer-level processes” (see product-by-process remarks below for the quoted limitation), and a size/pitch (i.e. a size or pitch) of routings of the first RDL structure is smaller than a size/pitch (i.e. a size or pitch) of routings of the second substrate (this is explicit on fig. 23 wherein in the first RDL structure 222, a horizontal pitch between the exposed adjacent connecting portions of the upper routing layers directly connecting to the corresponding connections pillars 46 of device 50 or connecting pillars 130 of device 100 is smaller than a pitch between adjacent routings layers 404 of the second substrate).
The Examiner notes that the process limitations of “the first logic die and the first RDL structure are formed by wafer-level processes” found in product claim(s) 1 invoke the product-by-process doctrine. Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps (MPEP § 2113). For example, anticipation of claim 1 does not require the first logic die and the first RDL structure to be formed by wafer-level processes (the claim as standing does not recite any structural distinction with the package assembly of Chen et al. ‘380).
b. Re claim 3, the second conductive structures are disposed directly above the corresponding TV interconnects, respectively (explicit on fig. 23).
c. Re claim 5, the memory die is electrically connected to the first substrate using bonding wires (explicit on fig. 23).
d. Re claim 6, the fan-out package comprises: a first molding compound 220 (fig. 19, [0059]) surrounding the first logic die, being in contact with the top surface of the first RDL structure, wherein the TV interconnects pass through the first molding compound.
e. Re claim 8, a first lateral dimension of the fan-out package is less than a second dimension of the second substrate in a cross-sectional view (explicit on fig. 23).
f. Re claim 9, the fan-out package comprises: a second logic die (logic device 100; [0024], [0057]) disposed on the top surface of the first RDL structure and beside the first logic die.
g. Re claim 10, the second logic die is electrically connected to the first logic die using the first RDL structure (explicit on fig. 23).
h. Re claim 11, the fan-out package comprises: a second redistribution layer (RDL) structure 206 (fig. 21, [0050]) disposed on the first logic die and the TV interconnects and opposite the first RDL structure, wherein the second RDL structure is electrically connected to the TV interconnects.
i. Re claim 12, the semiconductor package assembly as claimed in claim 1, further comprises: a second molding compound 408 ([0093]) filling a gap between the fan-out package and the second substrate and surrounding the first conductive structures.
j. Re claim 13, the semiconductor package assembly as claimed in claim 1, further comprising: a third molding compound (underfill disclosed in [0086] as filled between packages 200 and 350) filling a gap between the fan-out package and the memory package and surrounding the second conductive structures.
k. Re claim 15, the semiconductor package assembly as claimed in claim 1, further comprises: a first underfill 408 filling a gap between the fan-out package and the second substrate and surrounding the first conductive structures.
l. Re claim 16, the semiconductor package assembly as claimed in claim 1, further comprises: a second underfill (underfill disclosed in [0086] as filled between packages 200 and 350) filling a gap between the fan-out package and the memory package and surrounding the second conductive structures.
m. Re claim 32, Chen et al. disclose a semiconductor package assembly, comprising (see claim 1 rejection above as to which section to read for each identified element): a fan-out package 200 (fig. 23 and related text), comprising: a first redistribution layer (RDL) structure 222 having a top surface and a bottom surface; a first logic die (logic die 50) having first pads 46 close to the top surface of the first RDL structure and electrically connected to the first RDL structure; through via (TV) interconnects 216 surrounding the first logic die and electrically connected to the first logic die using the first RDL structure; and first conductive structures 238 on the bottom surface of the first RDL structure; a memory package 350 stacked on the fan-out package, comprising: a first substrate 302&304&306&308 having a top surface and a bottom surface; a memory die 310A mounted on the top surface of the first substrate; and second conductive structures 252 on the bottom surface of the first substrate, wherein the memory die is electrically connected to the first logic die using the first RDL structure (explicit on fig. 23); and a second substrate 450 stacked on the fan-out package and opposite the memory package, wherein the second substrate is electrically connected to the memory package using the fan-out package (explicit on fig. 23), wherein a first lateral dimension of the fan-out package is less than or equal to a second dimension of the second substrate in a cross-sectional view (explicit on fig. 23), wherein “the first logic die and the first RDL structure are formed by wafer-level processes” (see product-by-process remarks in claim 1 rejection above for the quoted limitation product-by-process limitation), and a size/pitch (i.e. a size or pitch) of routings of the first RDL structure is smaller than a size/pitch (i.e. a size or pitch) of routings of the second substrate (this is explicit on fig. 23 wherein in the first RDL structure 222, a horizontal pitch between the exposed adjacent connecting portions of the upper routing layers directly connecting to the corresponding connections pillars 46 of device 50 or connecting pillars 130 of device 100, the said pitch being a pitch of said upper routing layers, is smaller than a pitch between adjacent routings layers 404 of the second substrate).
n. Re claim 36, the fan-out package comprises: a second logic die (logic die 100) disposed on the top surface of the first RDL structure and between the first logic die and the TV interconnects, wherein the second logic die is electrically connected to the first logic die using the first RDL structure (explicit on fig. 23).
o. Re claim 37, Chen et al. disclose the semiconductor package assembly as claimed in claim 31, wherein the fan-out package comprises: a second redistribution layer (RDL) structure 206 between the second conductive structures and the first logic die, wherein the second RDL structure is electrically connected to the TV interconnects (explicit on fig. 23).
p. Re claim 38, the semiconductor package assembly as claimed in claim 32, further comprises: a second molding compound 408 filling a first gap between the fan-out package and the second substrate or a second gap between the fan-out package and the memory package.
q. Re claim 39, the semiconductor package assembly as claimed in claim 32, further comprises: an underfill 408 filling a first gap between the fan-out package and the second substrate or a second gap between the fan-out package and the memory package.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 7, 17-20, 24-27, 29-31, 33 and 40 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2021/0098380).
a. Re claim 2, Chen et al. disclose all the limitations of claim 1 as stated above including that the memory die is electrically connected to the second substrate using the second conductive structures, the TV interconnects, the first RDL structure and the first conductive structures (explicit on fig. 23), except explicitly using the first logic die also. But as can be seen on fig. 22, the first logic die is connected a least in part on connection paths that go from bumps 250 to memory die 310A, thus from second substrate 450 to memory die 310A. It is noted that as a logic die, die 50 would implicitly relay signals from board 450 to memory package 350 as necessary. As such, and noting that the rationale to modify or combine the prior art does not have to be expressly stated in the prior art but may be expressly or impliedly contained in the prior art or it may be reasoned from knowledge generally available to one of ordinary skill in the art, established scientific principles, or legal precedent established by prior case law (see MPEP 2144.I), further noting that the desire to enhance commercial opportunities by improving a product or process is universal and even common-sensical (see MPEP 2144.II), and finally noting from MPEP 2141.03 that “A person of ordinary skill in the art is also a person of ordinary creativity, not an automaton” and that a “hypothetical ‘person having ordinary skill in the art’ to which the claimed subject matter pertains would, of necessity have the capability of understanding the scientific and engineering principles applicable to the pertinent art.”, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided logic die 50 to be electrically connected to board 450 and memory package 350 in order to relay signal between the said board 450 and the memory dies of the memory package as required by design and/or electrical performance of package 300. The modification would have resulted in the first logic die being also used (in combination with the second conductive structures, the TV interconnects, the first RDL structure and the first conductive structures) in electrically connecting the memory die with the second substrate.
b. Re claim 7, Chen et al. disclose all the limitations of claim 1 as stated above except explicitly that a first thickness of the first RDL structure is less than a second thickness of the second substrate. However, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided via a non-inventive change in size (see MPEP 2144.04.IV), either the first RDL to be thinner than substrate 450 in order to reduce the overall weight of package 300 (see MPEP 2144.I&II), or provided the second substrate 450 to be thicker than the first RDL in order to provide for a mechanically robust package 300 (see MPEP 2144.I&II).
c. Re claim 17, Chen et al. disclose all the limitations of claim 1 as stated above including that the semiconductor package assembly as claimed in claim 1, further comprises: a first electronic component (one of the passive devices disclosed in [0094] as being bonded to pads 404) mounted on the second substrate, except explicitly that the first electronic component is beside the fan-out package, wherein the first electronic component is electrically connected to the fan-out package using the second substrate. However, and noting that the rationale to modify or combine the prior art does not have to be expressly stated in the prior art but may be expressly or impliedly contained in the prior art or it may be reasoned from knowledge generally available to one of ordinary skill in the art, established scientific principles, or legal precedent established by prior case law (see MPEP 2144.I), further noting that the desire to enhance commercial opportunities by improving a product or process is universal and even common-sensical (see MPEP 2144.II), and finally noting from MPEP 2141.03 that “A person of ordinary skill in the art is also a person of ordinary creativity, not an automaton” and that a “hypothetical ‘person having ordinary skill in the art’ to which the claimed subject matter pertains would, of necessity have the capability of understanding the scientific and engineering principles applicable to the pertinent art.”, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided the second substrate wide enough so as to connect the first electronic component to the second substrate beside the fan-out package so as not to interfere with each other mounting on the second substrate, and also to have provided the first electronic component to be electrically connected to the fan-out package using the second substrate by necessity in a configuration wherein such an electrical connection is required by design and/or electrical performance of package 300.
d. Re claim 18, Chen et al. disclose all the limitations of claim 1 as stated above including the semiconductor package assembly as claimed in claim 17, further comprising: a second electronic component (another one of the passive devices disclosed in [0094]), except explicitly for the second electronic component stacked on the first electronic component, wherein the second electronic component is electrically connected to the fan-out package using the second substrate. However, and taking into account the profile of a skilled in the art as defined in claim 17 rejection above, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided the second electronic component staked on the first electronic component in order to save space laterally by not making the second substrate 450 laterally bigger wherein such a choice is merely an obvious choice of mounting the first and second electronic components side-by-side or stacked (see MPEP 2143.E). Additionally, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided the second electronic component electrically connected to the fan-out package using the second substrate by necessity in a configuration wherein such an electrical connection is required by design and/or electrical performance of package 300.
e. Re claim 19, Chen et al. disclose a semiconductor package assembly, comprising (see claim 1 rejection above as to which section to read for each identified element): a fan-out package 200 (fig. 23 and related text), comprising: a first redistribution layer (RDL) structure 222 having a top surface and a bottom surface; a first logic die (logic die 50) having first pads 46 close to the top surface of the first RDL structure and electrically connected to the first RDL structure; through via (TV) interconnects 216 surrounding the first logic die and electrically connected to the first logic die using the first RDL structure, wherein the TV interconnects are arranged by a first pitch (distance between them or between their center axis on fig. 23 for example); and first conductive structures 238 on the bottom surface of the first RDL structure; a memory package 350 stacked on the fan-out package, comprising: a first substrate 302&304&306&308 having a top surface and a bottom surface; a memory die 310A mounted on the top surface of the first substrate; and second conductive structures 252 on the bottom surface of the first substrate and arranged by a second pitch (distance between them or between their center axis on fig. 23 for example) shorter than or equal to the first pitch (explicit on fig. 23); and a second substrate 450 stack on the fan-out package and opposite the memory package, wherein “the first logic die and the first RDL structure are formed by wafer-level processes” (see product-by-process remarks in claim 1 rejection above for the quoted product-by-process limitation), and a size/pitch (i.e. a size or pitch) of routings of the first RDL structure is smaller than a size/pitch (i.e. a size or pitch) of routings of the second substrate (this is explicit on fig. 23 wherein in the first RDL structure 222, a horizontal pitch between the exposed adjacent connecting portions of the upper routing layers directly connecting to the corresponding connections pillars 46 of device 50 or connecting pillars 130 of device 100, the said pitch being a pitch of said upper routing layers, is smaller than a pitch between adjacent routings layers 404 of the second substrate). But Chen et al. do not appear to explicitly disclose that the second substrate is electrically connected to the memory package using the first logic die.
But as can be seen on fig. 22, the first logic die 50 is connected a least in part on connection paths that go from bumps 250 to memory die 310A, thus from second substrate 450 to memory die 310A. It is noted that as a logic die, die 50 would implicitly relay signals from board 450 to memory package 350 as necessary. As such, and noting that the rationale to modify or combine the prior art does not have to be expressly stated in the prior art but may be expressly or impliedly contained in the prior art or it may be reasoned from knowledge generally available to one of ordinary skill in the art, established scientific principles, or legal precedent established by prior case law (see MPEP 2144.I), further noting that the desire to enhance commercial opportunities by improving a product or process is universal and even common-sensical (see MPEP 2144.II), and finally noting from MPEP 2141.03 that “A person of ordinary skill in the art is also a person of ordinary creativity, not an automaton” and that a “hypothetical ‘person having ordinary skill in the art’ to which the claimed subject matter pertains would, of necessity have the capability of understanding the scientific and engineering principles applicable to the pertinent art.”, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided logic die 50 to be electrically connected to board 450 and memory package 350 in order to relay signal between the said board 450 and the memory dies of the memory package as required by design and/or electrical performance of package 300. The modification would have resulted in the second substrate being electrically connected to the memory package using the first logic die.
f. Re claim 20, the memory die is electrically connected to the first logic die using the second conductive structures, the TV interconnects and the first RDL structure (explicit on fig. 23).
g. Re claim 24, the fan-out package comprises: a second logic die (logic device 100; [0024], [0057]) disposed on the top surface of the first RDL structure and between the first logic die and the TV interconnects, wherein the second logic die is electrically connected to the first logic die using the first RDL structure (explicit on fig. 23).
h. Re claim 25, the fan-out package comprises: a second redistribution layer (RDL) structure 206 between the second conductive structures and the first logic die, wherein the second RDL structure is electrically connected to the TV interconnects (explicit on fig. 23).
i. Re claim 26, the semiconductor package assembly as claimed in claim 19, further comprises: a second molding compound 408 filling a gap between the fan-out package and the second substrate and surrounding the first conductive structures.
j. Re claim 27, the semiconductor package assembly as claimed in claim 19, further comprises: a third molding compound (underfill disclosed in [0086] as filled between packages 200 and 350) filling a gap between the fan-out package and the memory package and surrounding the second conductive structures.
k. Re claim 29, the semiconductor package assembly as claimed in claim 19, further comprises: a first underfill 408 filling a gap between the fan-out package and the second substrate and surrounding the first conductive structures.
l. Re claim 30, the semiconductor package assembly as claimed in claim 19, further comprises: a second underfill (underfill disclosed in [0086] as filled between packages 200 and 350) filling a gap between the fan-out package and the memory package and surrounding the second conductive structures.
m. Re claim 31, see claim 17 rejection above.
n. Re claim 33, Chen et al. disclose all the limitations of claim 32 as stated above including that the memory die is electrically connected to the second substrate using the first RDL structure (explicit on fig. 23), except explicitly that for using also the first logic die (in combination with the first RDL) to electrically connect the memory die and the second substrate. But as can be seen on fig. 22, the first logic die 50 is connected a least in part on connection paths that go from bumps 250 to memory die 310A, thus from second substrate 450 to memory die 310A. It is noted that as a logic die, die 50 would implicitly relay signals from board 450 to memory package 350 as necessary. As such, and noting that the rationale to modify or combine the prior art does not have to be expressly stated in the prior art but may be expressly or impliedly contained in the prior art or it may be reasoned from knowledge generally available to one of ordinary skill in the art, established scientific principles, or legal precedent established by prior case law (see MPEP 2144.I), further noting that the desire to enhance commercial opportunities by improving a product or process is universal and even common-sensical (see MPEP 2144.II), and finally noting from MPEP 2141.03 that “A person of ordinary skill in the art is also a person of ordinary creativity, not an automaton” and that a “hypothetical ‘person having ordinary skill in the art’ to which the claimed subject matter pertains would, of necessity have the capability of understanding the scientific and engineering principles applicable to the pertinent art.”, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided logic die 50 to be electrically connected to board 450 and memory package 350 in order to relay signal between the said board 450 and the memory dies of the memory package as required by design and/or electrical performance of package 300. The modification would have resulted in the second substrate being electrically connected to the memory die using the first logic die and the first RDL.
o. Re claim 40, see claim 17 rejection above wherein the same rationale applies, noting that Chen et al. disclose all the limitations of claim 32 as stated above.
Claim(s) 14, 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2021/0098380) in view of Lee (US 2012/0248439).
a. Re claim 14, Chen et al. disclose all the limitations of claim 1 as stated above except explicitly for the semiconductor package assembly as claimed in claim 1, further comprising: a fourth molding compound disposed on the second substrate and surrounding the fan-out package. However, Lee discloses providing a molding compound 150 (see at least fig. 1A and related text) to seal and protect stacked package components 10&110 on a circuit board 100. As such, it would have been obvious to one skilled in the art to have provided the semiconductor package assembly as claimed in claim 1, further comprising a fourth molding compound disposed on the second substrate and surrounding at least the fan-out package in order to seal and protect the said fan-out package.
b. Re claim 28, see claim 14 rejection above wherein the same rationale applies, noting that Chen et al. disclose all the limitations of claim 19 as stated above.
Claim(s) 4, 21-23 and 34-35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2021/0098380) in view of Yang et al. (US 2016/0099231).
a. Re claim 4, Chen et al. disclose all the limitations of claim 1 as stated above including that the first logic die has a front (bottom) surface and a back (top) surface, the first pads are located close to the front surface of the first logic die (explicit on fig. 23), except explicitly that the back surface of the first logic die is exposed from a top surface of the fan-out package.
However, Yang et al. disclose a package similar to the one of Chen et al. and wherein a back surface 302a of a logic die 302 (see fig. 2 and related text; see [0021]-[0022], [0035]-[0040]) is exposed from a top surface of a fan-out package 300b.
A such, and noting from [0050] of Chen et al. that the redistribution structure 206 is optional (i.e. can be omitted if desired), it would have been obvious to one skilled in the art before the effective filing date of the invention to have omitted the redistribution layer as desired in order to either reduce cost or reduced signal delays (see MPEP 2144.I&II and 2143.E&G) and such that the back surface of the logic devices 50&100 would be flushed with a top surface of encapsulant 220 and exposed from said encapsulant as in Yang et al. (surface 302a is flushed with, and exposed from encapsulant 312 top surface), noting that such a configuration would have also resulted in better heat dissipation by the exposed back surfaces of logic devices 50&100 (see MPEP 2144.I&II). The modification would have resulted in the back surface of the first logic die being exposed from a top surface of the fan-out package.
b. Re claim 21, see claim 4 rejection above wherein the same rationale applies, noting that Chen et al. disclose all the limitations of claim 19 as stated above.
c. Re claim 22, the modification as per claim 21 rejection above would have resulted in opposite ends of the TV interconnect being aligned (i.e. flushed or coplanar with) with the front surface and the back surface of the first logic die.
d. Re claim 23, the fan-out package comprises: a first molding compound 220 (fig. 19) disposed on the top surface of the first RDL structure and surrounding the first logic die and the TV interconnects, wherein the back surface of the first logic die is exposed from the molding compound (see claim 21 rejection).
e. Re claim 34, Chen et al. disclose all the limitations of claim 32 as stated above including that the first logic die has a back (top) surface away from the first RDL structure and a first, bottom, end of the TV interconnect is aligned (i.e. coplanar or flushed with) the front (bottom) surface of the logic die (see fig. 23), except explicitly that that the back surface is exposed from a top surface of the fan-out package, wherein an opposite end to the first end of the TV interconnect is aligned (i.e. coplanar or flushed with) with the back surface of the first logic die. However, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided the back surface of the logic die to be exposed from a top surface of the fan-out package for the same reasons invoked in claim 4 rejection above. The modification would have resulted in having the opposite end to the first end of the TV interconnect being aligned (i.e. coplanar or flushed with) with the back surface of the first logic die, and thus the semiconductor package assembly as claimed in claim 32, wherein the first logic die has a back surface away from the first RDL structure and exposed from a top surface of the fan-out package, wherein opposite ends of the TV interconnect are aligned with a front surface and the back surface of the first logic die.
f. Re claim 35, the fan-out package comprises: a first molding compound 220 (fig. 19) in contact with the top surface of the first RDL structure and surrounding the first logic die and the TV interconnects, wherein the back surface of the first logic die is exposed from the molding compound (see claim 34 rejection above).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-40 have been considered but are moot because they do not apply to the rationale in the new ground of rejection in view of Applicants’ amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PENIEL M GUMEDZOE whose telephone number is (571)270-3041. The examiner can normally be reached M-F: 9:00AM - 5:30PM.
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/PENIEL M GUMEDZOE/Primary Examiner, Art Unit 2899