DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-3,5-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, because the specification, while being enabling for wherein the at least one nanowire is a p-type nanowire and wherein the nanoflake is a n-type nanoflake or vice versa, does not reasonably provide enablement for a generic doping and the device being anti-ambipolar. The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to arbitrary anti-ambipolar the invention commensurate in scope with these claims. Wang et al. Mixed-Dimensional Anti-ambipolar Phototransistors Based on 1D GaAsSb/2D MoS2 Heterojunctions. The inventors of the instant of application state: The anti-ambipolar behavior can be deemed as deriving from the field-effect transistor (FET) channel composed of p-type and n-type semiconductors in series. Thus, applicant has not enabled the entire scope of doping profiles for the nanowire and the flake to provide an anti-ambipolar device. As claimed the flake could have the same doping as the nanowire which is not enabled.
Claims 1-3,5-6 and 8-16 and 18-21 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Applicant does not have support for a generic substrate and the device being a gate tunable applicant based on figure 2a appears to be using the silicon of the SiO2 as the gate. This is the only disclosure of a gate though the gate is referenced in outcomes of figures 6 applicant does not depict or disclose another gate structure.
As to claim 19 , Applicant does not have support for generic Van der Waals materials Applicant only discloses MoS2.
Claims 7 and 17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
While it appears the Si substrate is the back gate the Silicon layer would need to be doped since undoped Silicon are non-conductive and operate as dielectric. Thus, applicant does not have support for an undoped Silicon layer and a gate tunable anti-ambipolar transistor.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3,5-6,8-16, 18-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The omitted elements are: The claims are drawn to a gate tunable … however there is not gate claimed in the structure.
Claim 7 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Applicant fails to link the gate to the Si/SiO2 structure based on figure 2A it appears applicant is using the substrate silicon (doped silicon) as a back gate however applicant does not link this to the already recited gate.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) s 1-3,5-21 are is/are rejected under 35 U.S.C. 102a1 as being anticipated by Wang et al.
Wang et al appears to have overlapping inventors but contains several individuals that are not listed as inventors specifically SenPo Yip who is a professor at Kyushu University and Chuntai Liu who does not appear to be a student. While In re Katz, 687 F.2d 450 (C.C.P.A. 1982) set forth that declaration can overcome a rejection where the co-authors are students working under the direction of the inventor this does not apply to non-students or individuals not solely beholden to the inventors. In this instance SenPo Yip and Chantai Liu are professors at different universities thus there is no implied relationship between these individuals and the inventors.
a. As to claim 1, Wang teaches A gate-tunable anti-ambipolar phototransistor based on a mixed-dimensional heterojunction device, comprising: at least one substrate layer; at least one nanowire positioned on a portion of the at least one substrate layer, wherein the at least one nanowire is at least one of ternary and quaternary; at least one first contact positioned over at least a portion of the at least one substrate layer and at least a portion of the at least one nanowire; a nanoflake positioned on at least a portion of the at least one substrate layer and at least a portion of the at least one nanowire; and at least one second contact positioned on at least a portion of the at least one substrate layer and at least a portion of the nanoflake (see figure abstract figure and figure 4). The substrate is used as the gate figure 4
b. As to claim 2, Wang teaches GaAsSB a III-V material.
c. As to claim 3, Wang teach n and p doping to form the anti-ambipolar .
d. As to claim 5, Wang teaches wherein the at least one nanowire is positioned beneath the at least one first contact and the nanoflake (see disclosure and figure 4).
e. As to claim 6, Wang teaches wherein the at least one nanowire is positioned on the at least one first contact and the nanoflake (figure 4)
f. As to claim 7-8 Wang teaches a Si/SiO2 layer for the substrate and even thought thermally grown is product by process Wang teaches thermally grown (method section).
g. As to claim 9 Wang teaches wherein the at least one nanowire directly contacts the at least one first contact (figure 4).
h. As to claim 10 Wang teaches wherein at least a first portion of the nanoflake directly contacts the at least one nanowire and at least a second portion of the nanoflake directly contacts the second contact (figure 4).
i. As to claim 11, Wang teaches A method of gate-tunable anti-ambipolar phototransitor based on a mixed-dimensional heterojunction device comprising: obtaining a substrate(method section Nanowire Synthesis) ;obtaining a prepared nanowire (method section); transferring the nanowire onto the substrate (device fabrication section), wherein the nanowire is at least one of ternary and quaternary (Nanowire Synsthesis);depositing a first contact over the substrate and at least a portion of the nanowire (see Ni contact formation Device fabrication);forming nanoflake over a portion of the substrate and a portion of the nanowire (see PDMS exfoliation of MOS2);and depositing a second contact over the substrate and at least a portion of the nanoflake (Au deposition step).
j. As to claim 12, Wang teaches wherein the nanowire is transferred using a dry transfer technique (see nanowire transfer step in device fabrication).
k. As to claim 13, Wang teaches deposited using photolithography and e-beam evaporation (see device fabrication steps using e-beam and photolithography).
l. As to claim 14, Wang teaches wherein the nanoflake is formed by mechanically exfoliating by polydimethylsiloxane (PDMS transfer of MoS2 flake).
m. As to claim 15, Wang teaches wherein the nanoflake is transferred onto the portion of the nanowire (see device fabrication).
n. As to claim 16, Wang teaches wherein the second contact is formed deposited by electron beam lithography and thermal evaporation (Au contact formation).
o. As to claim 17, Wang teaches wherein the substrate comprises: a Si wafer; and a SiO2 layer positioned on the Si wafer (figure 4).
p. As to claim 18 Wang teaches GaAsSb a III-V material.
q. As to claim 19 Wang teaches MoS2 (see abstract.
r. As to claims 20-21 Wang teaches wherein the at least one nanowire is a p-type nanowire and wherein the nanoflake is a n-type nanoflake. Wang states :The device configuration can be regarded as the combination of three functional parts in a series-resistance mode: an n-type MoS2 FET, a GaAsSb/MoS2 p–n diode, and a p-type GaAsSb FET (Figure 2d).
Response to Arguments
Applicant’s arguments with respect to the claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW L REAMES whose telephone number is (571)272-2408. The examiner can normally be reached M-Th 6:00 am-4:00 pm EST.
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/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/Primary Examiner, Art Unit 2896