Prosecution Insights
Last updated: May 29, 2026
Application No. 18/146,326

DIRECTLY BONDED FRAME WAFERS

Final Rejection §103
Filed
Dec 23, 2022
Priority
Dec 27, 2021 — provisional 63/294,031
Examiner
CULLEN, PATRICK LAWRENCE
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Adeia Semiconductor Bonding Technologies Inc.
OA Round
2 (Final)
87%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
13 granted / 15 resolved
+18.7% vs TC avg
Strong +25% interview lift
Without
With
+25.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
18 currently pending
Career history
66
Total Applications
across all art units

Statute-Specific Performance

§103
96.0%
+56.0% vs TC avg
§102
2.7%
-37.3% vs TC avg
§112
1.3%
-38.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 15 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 Claim(s) 17-25 and 28-36 are rejected under 35 U.S.C. 103 as being unpatentable over Mok (PGPub No. 20210287977). Regarding claim 17, Mok teaches a bonded structure frame element comprising: a frame element comprising: an opening extending from a first side of the frame element to a second side opposite the first side (Fig. 6 points to a component carrier (frame element) comprising a central outer hole 15, also referred to as a component hole 19 (opening).); a bulk portion (Id. points to a glass core 2 (bulk portion).); a first bonding layer disposed on a first surface of the bulk portion and at least partially defining the first side of the frame element (Id. points to a first further electrically insulating layer structure 8 (first bonding layer).); a second bonding layer on a second surface of the bulk portion and at least partially defining the second side of the frame element opposite the first side (Id. points to a second further electrically insulating layer structure 17 (second bonding layer).), wherein the opening extends through the first bonding layer, the bulk portion, and the second bonding layer (Id. points to a central outer hole 15, also referred to as a component hole 19 (opening).), wherein the bulk portion comprises a first sidewall of the opening, the first sidewall comprising a first etch signature indicative of a first etch process in a first direction from the first side of the frame element towards the second side of the frame element, and wherein the first bonding layer comprises a second sidewall of the opening, the second sidewall comprising a second etch signature indicative of a second etch process in the first direction (Fig. 6 and [0102] point to a hole 15/19 (opening) formed by dry and/or wet etching methods, resulting in a sidewall formed along the first further electrically insulating layer structure 8 (first bonding layer; second sidewall) and a sidewall formed along the top half of the glass core 2 (bulk portion; first sidewall).); and a first element bonded to the first side of the frame element without an intervening adhesive ([0136] points to an alternative embodiment of the component carrier such that at least one component 13 (first element) may be surface mounted on said component carrier.). Regarding claim 18, Mok teaches wherein the second bonding layer comprises a third sidewall of the opening, the third sidewall comprising a third etch signature indicative of a third etch process in the first direction (Fig. 6 and [0102] point to a hole 15/19 (opening) formed by dry and/or wet etching methods, resulting in a sidewall formed along the second further electrically insulating layer structure 17 (second bonding layer; third sidewall).). Regarding claim 19, Mok teaches a second element directly bonded to the second side of the frame element without an intervening adhesive, the bonded structure comprising a cavity at least partially defined by the opening, wherein the first element is directly bonded to the frame element without an intervening adhesive ([0136] points to an alternative embodiment of the component carrier such that at least one component 13 (second element) may be surface mounted on said component carrier. It is considered obvious that the second component/element would be mounted on a surface of the carrier opposite to the first element in order to limit the interference between each component/element.). Regarding claim 20, Mok teaches one or more devices mounted to or formed with at least one of the first and second elements, the one or more devices extending into or exposed to the cavity (Fig. 6 and [0136] point to a component carrier comprising a hole 15/19 (cavity) and at least one component 13 (one or more devices) being surface mounted on and/or embedded in the component carrier.). Regarding claim 21, Mok teaches wherein the one or more devices comprises an integrated device die ([0136] points to the at least one component 13 (one or more devices) being selected from a group including an electronic chip and a logic chip.). Regarding claim 22, Mok teaches wherein a third conductive contact feature of the first element is directly bonded to a first conductive contact feature of the frame element without an adhesive (Fig. 6 and [0136] point to a component carrier comprising a first further electrically conductive layer structure 9 (first conductive contact feature) and at least one component 13 (first element) being surface mounted on and/or embedded in the component carrier. It is considered obvious that said component/element would include at least one conductive contact feature (third conductive contact feature) which, when surface mounted to the carrier, would directly bond to structure 9 in order to allow for communication with any other devices that may be mounted onto the opposite surface of said carrier.). Regarding claim 23, Mok teaches wherein a fourth conductive contact feature of the second element is directly bonded to a second conductive contact feature of the frame element (Fig. 6 and [0136] point to a component carrier comprising a second further electrically conductive layer structure 18 (second conductive contact feature) and at least one component 13 (first element) being surface mounted on and/or embedded in the component carrier. It is considered obvious that said component/element would include at least one conductive contact feature (fourth conductive contact feature) which, when surface mounted to the carrier, would directly bond to structure 18 in order to allow for communication with any other devices that may be mounted onto the opposite surface of said carrier.). Regarding claim 24, Mok teaches wherein the first bonding layer of the frame element is directly bonded to a third bonding layer of the first element (Fig. 6 and [0136] point to a first further electrically insulating layer structure 8 (first bonding layer) and at least one component 13 (first element) being surface mounted on and/or embedded in the component carrier. It is considered obvious that said component/element would include a bonding layer (third bonding layer) which, when surface mounted to the component carrier, would directly bond to structure 8 in order to maximize adhesion to the carrier and by extension improve physical stability.). Regarding claim 25, Mok teaches wherein the second bonding layer of the frame element is directly bonded to a fourth bonding layer of the second element (Fig. 6 and [0136] point to a second further electrically insulating layer structure 17 (second bonding layer) and at least one component 13 (first element) being surface mounted on and/or embedded in the component carrier. It is considered obvious that said component/element would include a bonding layer (fourth bonding layer) which, when surface mounted to the component carrier, would directly bond to structure 17 in order to maximize adhesion to the carrier and by extension improve physical stability.). Regarding claim 28, Mok teaches wherein the second and third sidewalls are tapered in a same orientation (Fig. 6 points to a hole 15/19 defined by a sidewall formed along the first further electrically insulating layer structure 8 (second sidewall) and a sidewall formed along the second further electrically insulating layer structure 17 (third sidewall). The disclosure does not appear to lend any criticality or significance to each sidewall’s tapered orientation and, as such, is deemed a matter of choice that a person of ordinary skill in the art would have found obvious. Absent persuasive evidence that a particular configuration is significant, said configuration is deemed a matter of choice which a person of ordinary skill in the art would have found obvious. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966); see also MPEP 2144.04(IV)(B).). Regarding claim 29, Mok teaches wherein the second bonding layer comprises a third sidewall of the opening, the third sidewall comprising a third etch signature indicative of a third etch process in a second direction from the second side of the frame element towards the first side of the frame element (Fig. 6 and [0102] point to a hole 15/19 (opening) formed by dry and/or wet etching methods, resulting in a sidewall formed along the second further electrically insulating layer structure 17 (second bonding layer; third sidewall).). Regarding claim 30, Mok teaches wherein the bulk portion comprises a fourth sidewall of the opening, the fourth sidewall comprising a fourth etch signature indicative of a fourth etch process in the second direction (Fig. 6 and [0102] point to a hole 15/19 (opening) formed by dry and/or wet etching methods, resulting in a sidewall formed along the bottom half of the glass core 2 (bulk portion; fourth sidewall).). Regarding claim 31, Mok teaches wherein the second and third sidewalls are tapered in an opposite orientation (Fig. 6 points to a hole 15/19 defined by a sidewall formed along the first further electrically insulating layer structure 8 (second sidewall) and a sidewall formed along the second further electrically insulating layer structure 17 (third sidewall).). The disclosure does not appear to lend any criticality or significance to each sidewall’s tapered orientation and, as such, is deemed a matter of choice that a person of ordinary skill in the art would have found obvious. Absent persuasive evidence that a particular configuration is significant, said configuration is deemed a matter of choice which a person of ordinary skill in the art would have found obvious. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966); see also MPEP 2144.04(IV)(B).). Regarding claim 32, Mok teaches wherein the second and third sidewalls are laterally misaligned in a third direction that is transverse to the first direction (Fig. 6 points to a hole 15/19 defined by a sidewall formed along the first further electrically insulating layer structure 8 (second sidewall) and a sidewall formed along the second further electrically insulating layer structure 17 (third sidewall).). It is considered obvious that the second and third sidewalls would be laterally misaligned to some degree due to the impossibility of having non-misalignment during manufacturing along with a lack of detail regarding what kind of “alignment” is specifically being sought out by the claimed invention.). Regarding claim 33, Mok teaches wherein any of the first and second etch signatures comprises respective striations in corresponding first and second sidewalls (Fig. 6 and [0102] point to a hole 15/19 (opening) formed by dry and/or wet etching methods (first and second etch signatures), resulting in a sidewall formed along the first further electrically insulating layer structure 8 (second sidewall) and a sidewall formed along the top half of the glass core 2 (first sidewall). It is considered obvious that each of the sidewalls would comprise respective striations due to the nature of dry and/or wet etching methods.). Regarding claim 34, Mok teaches wherein any of the first and second etch signatures comprises respective tapering angles in corresponding first and second sidewalls (Fig. 6 and [0102] point to a hole 15/19 (opening) formed by dry and/or wet etching methods (first and second etch signatures), resulting in a sidewall formed along the first further electrically insulating layer structure 8 (second sidewall) and a sidewall formed along the top half of the glass core 2 (first sidewall). It is considered obvious that each of the sidewalls would comprise respective tapering angles due to the nature of dry and/or wet etching methods.).). Regarding claim 35, Mok teaches wherein the bulk portion comprises a semiconductor material (Fig. 6 points to glass core 2.). Regarding claim 36, Mok teaches wherein the first bonding layer comprises a first nonconductive material with a first conductive contact feature at least partially embedded in the first nonconductive material (Fig. 6 points to the first further electrically insulating layer structure 8 (first bonding layer) and the first further electrically conductive layer structure 9 (first conductive contact feature).). Claim(s) 26 is rejected under 35 U.S.C. 103 as being unpatentable over Mok in further view of Yoo (PGPub No. 20210366876). Regarding claim 26, Yoo teaches a vent hole extending from the cavity to outside environs (Fig. 1 points to a package substrate 100 comprising a cavity CV and a first vent hole VH1.). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Mok and Yoo such that a vent hole is formed to connect the cavity with the outside in order to allow for fluid communication with the cavity, which would improve heat dissipation. Claim(s) 27 is rejected under 35 U.S.C. 103 as being unpatentable over Mok et al. in further view of Chen (PGPub No. 20200395306). Regarding claim 27, Chen teaches wherein a width of the opening is in a range of 0.5 mm to 30 mm (Fig. 3B and [0054] point to a substrate 302 comprising a cavity 305 (opening) with lateral dimensions (width) ranging between about 0.5 mm and about 50 mm. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Mok et al. and Chen, such that the width of the cavity/opening is in a range of 0.5 mm to 30 mm in order to have a cavity/opening with lateral dimensions substantially similar to that of the semiconductor devices or dies that are later formed. Response to Arguments Applicant’s arguments, see Remarks, filed 01/02/2026, with respect to the objection(s) of claims 18 and 29 have been fully considered and are persuasive. The objection(s) of said claims have been withdrawn. Applicant's arguments filed 01/02/2026 regarding claim 17 (and by extension all dependent claims) have been fully considered but they are not persuasive. Specifically, Applicant argues that reference Mok fails to disclose or teach 1) a first bonding layer disposed on a first surface of the bulk portion and at least partially defining the first side of the frame element; a second bonding layer on a second surface of the bulk portion and at least partially defining the second side of the frame element opposite the first side, and 2) a first element bonded to the first side of the frame element without an intervening adhesive. Regarding the first argument, Examiner argues that Applicant has provided an argument that is narrower than what it actually supported. Specifically, Applicant argues that the electrically insulating layer structures 8 and 17 cannot correspond, respectively, to the first and second bonding layers of the claimed invention, as any bonding is impeded by the electrically conductive layer structures 9 and 18 (see Figs.5-6 and [0106] of Mok). However, Examiner argues that claim 17 never discloses a specific level of bonding attributed to the first and second bonding layers or any mention of impedance. As shown in Figs. 5-6 of Mok, the electrically conductive layer structures 9 and 18 only extend partially over the electrically insulating layer structures 8 and 17, such that there are clearly remaining portions of said insulating structures left exposed. Thus, Applicant’s argument is considered unpersuasive and fails to overcome the previous rejection. Regarding the second argument, Examiner argues that Applicant has provided a conclusory statement with no supporting evidence. Specifically, Applicant argues that a skilled artisan would understand that neither surface mounting nor embedding of the component as taught in [0136] of Mok would mean the same as “bonding […] without an intervening adhesive”. Firstly, Applicant provides no support for this statement and is simply stating how a skilled artisan would interpret Mok without explanation. Second, Examiner argues that neither the term “surface mounting” nor “embedding” carry no such connotation, and that multiple techniques exist where a component is mounted/embedded without an intervening adhesive. Thus, Applicant’s argument is considered unpersuasive and fails to overcome the previous rejection. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Patrick L Cullen whose telephone number is (703)756-1221. The examiner can normally be reached Monday - Friday, 8:30AM - 5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at (571)270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICK CULLEN/ Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Dec 23, 2022
Application Filed
Oct 01, 2025
Non-Final Rejection mailed — §103
Jan 02, 2026
Response Filed
Apr 24, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
87%
Grant Probability
99%
With Interview (+25.0%)
3y 5m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 15 resolved cases by this examiner. Grant probability derived from career allowance rate.

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