DETAILED ACTION
This action is responsive to the Amendments filed May 20, 2026. Claims 1-12, 21, 24, and 26-27 are pending. Claims 1 and 3 have been amended. Claim 1 is independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
Applicant's amendment to the title of the invention is acknowledged and accepted. The objection to the title has been withdrawn.
Claim Rejections - 35 USC § 112 – Indefiniteness
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12, 21, 24, and 26-27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding independent claim 1, the claim as currently amended recites (emphasis added):
“wherein each drain-region semiconductor strip, each channel semiconductor strip, and each source-region semiconductor strip comprise a body structure and a plurality of protrusions, respectively, the body structure extends along the column direction and is in the shape of a strip, the plurality of protrusions are distributed on both sides of the body structure in two columns, each of two columns comprises a plurality of protrusions spaced apart, and each of the plurality of protrusion extends from the body structure in the row direction toward a corresponding gate strip in a direction deviating from the body structure; and a surface of each of the gate strips near the drain-region semiconductor strip, the channel semiconductor strip, and the source-region semiconductor strip is a curved concave surface.”
The claim is indefinite for the following reasons:
It is unclear what structural features distinguish a “protrusion” from the overall shape of the semiconductor strip. The drawings (particularly Figs. 4 and 11) appear to show continuous rounded or cylindrical structures labeled 15a/15b. A person of ordinary skill in the art cannot determine with reasonable certainty whether a continuous rounded ridge or fin on each side of a central body meets the “plurality of protrusions… spaced apart” limitation, or whether discrete, discontinuous protruding elements are required.
The requirement that the protrusions be “distributed on both sides of the body structure in two columns” is unclear in view of the drawings. Fig. 7, which is cited as illustrating the claimed structure, shows roundedness on only one side of the illustrated feature; the opposite side appears essentially flat. It is therefore unclear whether the claim requires bilateral protrusions with matching concave gate surfaces on both sides, or whether a one-sided rounded interface is sufficient.
The relationship between the recited “curved concave surface” of the gate strips and the protrusions is ambiguous. It is unclear whether each individual protrusion must have a dedicated concave segment on the corresponding gate strip, or whether a generally concave gate surface facing a rounded strip satisfies the language.
The specification (para. 103 – 106) describes semiconductor strips that include a body structure and protrusions that may have an arc or columnar-semicircular convex surface, and further describes a corresponding curved concave gate surface. Nevertheless, when the claim language is read in the light of the specification and the drawings (particularly Figs. 4, 7, and 11), a person of ordinary skill in the art cannot determine with reasonable certainty the metes and bounds of the recited “body structure and a plurality of protrusions… distributed on both sides… spaced apart” and “curved concave surface” limitations, for the reasons set forth above.
For the purpose of applying prior art under MPEP § 2173.06, the examiner interprets the "body structure and plurality of protrusions… distributed on both sides… spaced apart" and "curved concave surface" language as requiring a non-planar, curved interface between the semiconductor strips and the gate strips that increases the effective gate-channel interface area. This interpretation is consistent with the stated purpose of the limitation in the specification (para. 105) and with the overall appearance of the structures shown in Figs. 4, 7, and 11.
Claims 2–12, 21, 24, and 26–27 depend from claim 1 and are likewise indefinite.
Regarding claim 3, the claim recites, in relevant part, the limitation (emphasis added):
"performing a row-selection operation on an odd word line of one row of the word lines in the memory block to select one row of the first memory cells… or performing a row-selection operation on an even word line of one row of the word lines in the memory block to select one row of the second memory cells…”
Claim 3 currently depends directly from claim 1. Claim 1 does not introduce or define the terms “odd word line,” “even word line,” “first memory cells,” or “second memory cells.” These terms are defined only in claim 2.
Previously, claim 3 depended from claim 2, which provided the necessary antecedent basis. By amending claim 3 to depend directly from claim 1, Applicant removed that antecedent basis.
Consequently, claim 3 lacks antecedent basis for the emphasized terms. Claims 5, 6, and 10 depend from claim 3 and inherit the same indefiniteness.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 4, 21, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (Novel 3D NOR FLASH with Single-Crystal Silicon Channel; “Huang” - of Record) in view of Lee et al. (US 20020080653; “Lee” – of Record), and further in view of Shen (US 20220254803).
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Regarding independent claim 1, notwithstanding the rejection for indefiniteness above, Huang discloses a control method of a memory block, comprising:
wherein the memory block comprises at least three memory subarray layers stacked sequentially along a height direction (Fig. 2a, 2f);
the at least a portion of the selected row of the memory cells comprises at least a portion of the memory cells of each of the memory subarray layers arranged in the selected row (Fig. 1a, 1b, where it illustrates the topology of a row with a word line connecting two transistors through a select transistor); and
each of the memory subarray layers comprises a drain-region semiconductor layer, a channel semiconductor layer, and a source-region semiconductor layer stacked along the height direction (Fig. 2f);
in each of the memory subarray layers, the drain-region semiconductor layer comprises at least three drain-region semiconductor strips, the channel semiconductor layer comprises at least three channel semiconductor strips, and the source-region semiconductor layer comprises at least three source-region semiconductor strips (Fig. 2f);
each drain-region semiconductor strip, each channel semiconductor strip, and each source-region semiconductor strip are distributed along the row direction and extend along a column direction (Fig. 1a, where it illustrates the layers are stacked extending on a horizontal plane orthogonal to the gate as in the instant application);
at least three gate strips distributed along the column direction are arranged on each side of each column of the drain-region semiconductor strips, the channel semiconductor strips, and the source-region semiconductor strips (Fig. 1a, where it illustrates the geometry of a 3x3 array of gates within the 3D memory block. It is noted that the topology of the individual transistors, indicating the equivalent of 'strips' in the instant application is evinced);
each of the gate strips extend along the height direction (Fig. 1a);
each row of the word lines is connected to gate strips arranged in a corresponding same row separately (Fig. 1a, WL1 for example);
each of the drain-region semiconductor strips of each of the memory subarray layers is served as a bit line (Fig. 2f. BL0 and BL1 for example).
Huang is silent with respect to row and column select operations.
However, Lee teaches performing a row-selection operation on at least a portion of at least one row of a plurality of word lines in the memory block to select at least a portion of at least one row of memory cells (para. 39, "The row select circuit 120 supplies the selected word line with a word line voltage necessary for any operation such as a program, erase, read, erase verify or erase repair operation". It is noted that a row-selection operation is well known in the art and necessarily a function of all memory arrays.)
Lee further teaches performing a column-selection operation on a column of memory cells of a corresponding one of the memory subarray layers to select a memory cell for performing a memory operation (para. 40, " the column select circuit 130 supplies the selected bit lines with a drain voltage necessary for any operation such as a program, erase, read, erase verify or erase repair operation". It is noted that a column selection operation is well known in the art and necessarily a function of all memory arrays.)
Huang, as modified by Lee, discloses a three-dimensional NOR memory structure comprising stacked memory subarray layers, each having a drain-region, channel and source-region semiconductor strips with vertical gate structures extending through the layers, and the performance of row and column selection operations on the array, but is silent with respect to the semiconductor regions comprising curved gate structures that increase the effective gate-channel interface area.
However, Shen teaches wherein each drain-region semiconductor strip, each channel semiconductor strip, and each source-region semiconductor strip comprise a body structure and a plurality of protrusions, respectively, the body structure extends along the column direction and is in the shape of a strip, the plurality of protrusions are distributed on both sides of the body structure in two columns, each of two columns comprises a plurality of protrusions spaced apart, and each of the plurality of protrusion extends from the body structure in the row direction toward a corresponding gate strip in a direction deviating from the body structure (Figs. 1A and 1B. See also para. 35; "Thin-film channel layer 401 therefore forms a concave channel region at each of the word lines 911-918, which extends around the perimeter of the vertical opening.", "The memory cells formed thereby have a curved and confined channel layer, between the adjacent layers of insulating material". Further see para 28; "the layers of word line material have recessed inside surfaces, recessed relative to inside surfaces facing the opening of the adjacent ones of the alternating layers of insulating material);
and a surface of each of the gate strips near the drain-region semiconductor strip, the channel semiconductor strip, and the source-region semiconductor strip is a curved concave surface (para. 34; "This concave channel region over the recessed inside surfaces of the layers of word line material can be continuous around the perimeter of the vertical opening, forming a horizontal channel." Further, see Abstr. "One of the layers of insulating material and layers of word line material have recessed inside surfaces facing the opening.", "A semiconductor channel layer is disposed on the data storage structures around a perimeter of the vertical opening". It is also noted that Shen states the purpose for the curved channel structure: para. 34; "This structure can result in better isolation between the layers of memory cells and less disturbance of neighboring cells when activating a given cell within the stack" which is analogous to the instant application and Shen's rationale appears throughout the reference for both the concave and convex embodiments.).
Huang, Lee and Shen are from the same field of endeavor directed to various data operations on non-volatile memory arrays arranged in rows and columns. Under the interpretation of the limitations of the claim pursuant to MPEP § 2173.06 in the indefiniteness rejection above (i.e., a non-planar, curved interface between the semiconductor strips and the gate strips that increases the effective gate-channel interface area), it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor/gate interface of Huang and Lee with the curved (concave) channel geometry taught by Shen. Doing so would enable the same benefits expressly identified in both the instant application and in Shen. The modification is nothing more than the application of a known performance-enhancing curved interface (Shen) to a known 3D NOR stacked structure (Huang) to achieve a predictable result.
Regarding claim 4, Huang, Lee and Shen combined disclose the limitations of claim 1,
As applied, Huang further teaches wherein each of the channel semiconductor strips is separately connected to a same common well-region line to uniformly apply a well voltage to all of the channel semiconductor strips (Fig. 2d B1 and B0).
Regarding claim 21, Huang, Lee and Shen combined disclose the limitations of claim 1.
As applied, Huang further discloses wherein each drain region semiconductor strip in the same column of the plurality of memory subarray layers is led out through a bit line connection line, and the bit line connection line extends along the height direction (Fig. 1(f) where it illustrates the drain layer steps extending and connecting to vertical connector columns BL1 & BL0 and extending up in the height direction);
each source region semiconductor strip in the same column of the plurality of memory subarray layers is led out through a source connection line, and the source connection line extends along the height direction (Fig. 1(f) where it illustrates the source layer step extending and connecting to vertical connector column SL and extending up in the height direction);
each channel semiconductor strip in the same column of the plurality of memory subarray layers is led out through a well region connection line, and the well region connection line extends along the height direction (Fig. 1(f) where it illustrates the channel layer steps extending and connecting to vertical connector columns B1 & B0 and extending up in the height direction).
Regarding claim 26, Huang, Lee and Shen combined disclose the limitations of claim 1.
As applied, Huang further discloses wherein in the height direction, a projection of at least a part of each gate strip coincides with a projection of a part of a corresponding channel semiconductor strip in each memory subarray layer on a projection plane, and the projection plane extends along the height direction and the column direction (Fig. 1(a) where it illustrates the gate structure extending above the oxide plane at the top of the memory array).
Claims 2, 3, 5, 7-10, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (Novel 3D NOR FLASH with Single-Crystal Silicon Channel; “Huang” – of Record) in view of Lee et al. (US 20020080653; “Lee” – of Record) and further in view of Shen (US 20220254803), and further in view of Lue (US 20160056168 – of Record).
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Regarding claim 2, Huang, Lee and Shen combined disclose the limitations of claim 1.
As applied, Huang further teaches each of the drain semiconductor strips, the channel semiconductor strips and the source semiconductor strips of each of the memory subarray layers cooperates with the odd gate strips in the odd word-line holes arranged on one side thereof to form a first memory cell (Fig. 2f. It is well known in the art that the source, channel and drain of a given transistor is controlled by its associated gate).
each of the drain semiconductor strips, the channel semiconductor strips and the source semiconductor strips of each the memory subarray layer cooperates with the even gate strips in the even word-line holes arranged on the other side thereof to form second memory cells (Fig. 2f. It is well known in the art that the source, channel and drain of a given transistor is controlled by its associated gate. See also Fig. 1 where it illustrates a plurality of rows of gates with stacked memory cells on both sides.)
Huang (as modified by Lee and Shen) are silent with respect to the vertical gates being arranged in a staggered pattern.
However, Lue teaches each row of the word lines comprise an odd word line and an even word line (para. 55, "Consecutively adjacent word lines can be labeled as alternating between even word lines and odd word lines")
wherein a portion of the memory cells in a same row of the memory subarray layers are connected to an odd word line of a corresponding row separately through odd gate strips in odd word-line holes of the corresponding row (para. 55, "The vertical gate columns electrically coupled to an odd word line are aligned with vertical gate columns electrically coupled to other odd word lines");
the other portion of the memory cells in the same row of the memory subarray layers are connected to an even word line of the corresponding row separately through even gate strips in even word-line holes of the corresponding row (para. 55, "The vertical gate columns electrically coupled to an even word line are aligned with vertical gate columns electrically coupled to other even word lines");
the odd word-line holes are distributed on one side of each column of the drain-region semiconductor strips, the channel semiconductor strips and the source-region semiconductor strips (Fig. 2: odd word lines. Note also para. 3, " The present invention relates to high density memory devices, and particularly to memory devices in which multiple planes of memory cells are arranged to provide a three-dimensional 3D array";
the even word-line holes are distributed on the other side of each column of the drain-region semiconductor strips, the channel semiconductor strips and the source-region semiconductor strips (Fig. 2: even word lines. Note also para. 3, " The present invention relates to high density memory devices, and particularly to memory devices in which multiple planes of memory cells are arranged to provide a three-dimensional 3D array";
all of the first memory cells in a same row of the memory subarray layers are connected to an odd word line of the corresponding same row through the odd gate strips in the odd word-line holes in the corresponding same row (Fig. 2);
all of the second memory cells in a same row of the memory subarray layers are connected to an even number word line of the corresponding same row through the even gate strips in the even word-line holes in the corresponding same row (Fig. 2).
Huang, Lee, Shen and Lue are from the same field of endeavor directed to data storage operations on non-volatile 3D memory arrays arranged in rows and columns with vertical gates. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Huang (as modified by Lee and Shen) with the teachings of Lue to stagger the vertical gates memory array. Doing so would allow a larger memory density (Lue para. 55), and help mitigate read disturb events.
Regarding claim 3, notwithstanding the rejection for indefiniteness above, Huang, Lee and Shen combined disclose the limitations of claim 1.
Huang (as modified by Lee and Shen) are silent with respect to the row-selection operations of odd and even word lines.
However, Lue teaches wherein, the performing row-selection operation on at least a portion of at least one row of a plurality of rows of the word lines in the memory block to select at least a portion of at least one row of the memory cells, comprises:
performing a row-selection operation on an odd word line of one row of the word lines in the memory block to select one row of the first memory cells, wherein the selected one row of the first memory cells comprises all of the first memory cells in the memory subarray layers arranged in the selected corresponding row (para. 20, "In one embodiment of the technology, the control circuitry performs a read operation by applying a read bias to a selected one of the plurality of word lines and applying an off bias to another word line of the plurality of word lines adjacent to the selected one of the plurality of word lines". The selected word line may be designated as the odd word line corresponding to the first row for example.);
or performing a row-selection operation on an even word line of one row of the word lines in the memory block to select one row of the second memory cells, wherein the selected one row of the second memory cells comprises all of the second memory cells in the memory subarray layers arranged in the selected corresponding row (It is noted that the selection operation described in para. 20 above could be alternately designated as the even word line corresponding to the second row for example.)
Huang, Lee and Shen, along with Lue are from the same field of endeavor directed to data storage operations on non-volatile 3D memory arrays arranged in rows and columns with vertical gates. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Huang (as modified by Lee and Shen) with the staggered vertical gates in the memory array as taught by Lue. Doing so would allow a larger memory density (Lue para. 55), and help mitigate read disturb events.
Regarding claim 5, Huang, Lee, Shen and Lue combined disclose the limitations of claim 3.
As applied, Lue further discloses wherein, in response to the memory operation being a read operation, the control method comprising:
applying a first word-line selecting voltage to an odd word line or an even word line in a row of the word lines of the memory block (para. 158, "read operation by applying a read bias to a selected one of the plurality of word lines");
applying a read voltage on a drain-region semiconductor strip corresponding to a selected memory cell of a selected memory subarray layer to determine whether the selected memory cell has current passing, for determining whether the selected memory cell has electrons stored therein (para. 158, "The bias arrangement state machine 969 is configured to perform memory operations including erase, program, and read, such as a read operation". It is noted that this limitation appears to refer to para 179 in Applicant's specification as that is the only place that it refers to "applying a read voltage". However, that section appears to refer to a step "S12a" for which there is no specific corresponding drawing or other reference but appears to be directed to the read operation. Therefore, for examination purposes, this limitation will be interpreted as performing a standard non-volatile memory read operation in which the drain-region is the bit line, and which is well known in the art. See for example, Lue's read operation above.)
Regarding claim 7, Huang, Lee and Shen combined disclose the limitations of claim 4.
Huang, Lee and Shen alone are silent with respect to a write operation on a portion of the memory array.
However, Lue teaches wherein, in response to the memory operation being a write operation of a half sector of the memory cells (the term "half sector" is unclear. Based on Applicant's specification, for examination purposes, the term will be interpreted to mean "the row of memory cells corresponding to one of either the even or odd word lines"), the control method comprising:
applying a second word line selecting voltage to an odd word line or an even word line in a row of the word lines of the memory block (Fig. 30, where it illustrates both a program and pass voltage applied to adjacent word lines such that only one row (half sector) will be programmed.);
applying a second write voltage on the common well-region line, to uniformly apply the second write voltage to all of the channel semiconductor strips in all of the memory subarray layers to inject electrons into all of the first memory cells in a same selected row corresponding to the selected odd word line or to inject electrons into all of the second memory cells in a same selected row corresponding to the selected even word lines by F-N tunneling effect (para. 158, "The bias arrangement state machine 969 is configured to perform memory operations including erase, program, and read, such as a read operation". It is noted that this limitation appears to refer to para. 196-199 in Applicant's specification as that is the only place that it refers to both "a second write voltage" and "F-N tunneling". However, that section appears to refer to a step "S12c" for which there is no specific corresponding drawing or other reference but appears to be directed to the erase operation. Therefore, for examination purposes, this limitation will be interpreted as performing a standard non-volatile memory program operation on either the odd or even row of memory cells in which fowler-nordheim tunneling (F-N tunneling) effect is used on the channel to store charge on the floating gate and which is well known in the art. See also para. 155 "One embodiment uses −FN electron programming").
As indicated above, Huang, Lee, Shen and Lue are from the same field of endeavor directed to data storage operations on non-volatile 3D memory arrays arranged in rows and columns with vertical gates. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Huang (as modified by Lee and Shen) with the teachings of Lue to employ a write operation for the purpose of permitting the memory to utilize its required storage function.
Regarding claim 8, Huang, Lee and Shen combined disclose the limitations of claim 4.
Huang, Lee and Shen alone are silent with respect to an erase operation on a portion of the memory array.
However, Lue teaches wherein, in response to the memory operation being an erase operation of a half sector of the memory cells (the term "half sector" is unclear. Based on Applicant's specification, for examination purposes, the term will be interpreted to mean "the row of memory cells corresponding to one of either the even or odd word lines"), the control method comprising:
applying a third word-line selecting voltage to an odd word line or an even word line in a row of the word lines of the memory block (Fig. 31, where it illustrates an erase voltage applied to a row of a word line in the memory block.);
applying a well-region erase voltage on the common well-region line, to uniformly apply the well-region erase voltage to all of the channel semiconductor strips in all of the memory subarray layers to erase electrons from all of the first memory cells in a same selected row corresponding to the selected odd word lines or to erase electrons from all of the second memory cells in a same selected row corresponding to the selected even word lines (para. 158, "controller implemented in this example using bias arrangement state machine 969 controls the application of bias arrangement supply voltage generated or provided through the voltage supply or supplies in block 968, such as read, erase, program, erase verify and program verify voltages", "The bias arrangement state machine 969 is configured to perform memory operations including erase, program, and read, such as a read operation by applying a read bias to a selected one of the plurality of word lines, and applying an off bias to two word lines of the plurality of word lines adjacent to the selected one of the plurality of word lines on opposite sides of the selected one of the plurality of word lines". It is noted that while the example given is a bias for a read operation of a single word line, as it is configured to also include erase operations, it is understood that it could perform an erase operation on a single word line (half sector)).
As indicated above, Huang, Lee, Shen and Lue are from the same field of endeavor directed to data storage operations on non-volatile 3D memory arrays arranged in rows and columns with vertical gates. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Huang (as modified by Lee and Shen) with the teachings of Lue to employ an erase operation for the purpose of permitting the memory to utilize erase functionality that would permit the memory data to be wiped or to prepare the memory for rewriting.
Regarding claim 9, Huang, Lee and Shen combined disclose the limitations of claim 4.
Huang, Lee and Shen alone are silent with respect to an erase operation on a sector of the memory array.
However, Lue teaches wherein, in response to the memory operation being an erase operation of a sector of the memory cells, the control method comprising (para. 149, "word lines 103-107 access all of the memory cells in a memory block for an erase operation". See also Fig. 31 where it illustrates the erase voltage (Verase) applied to the word line.):
applying a third word-line selecting voltage to an odd word line and an even word line in a row of the word lines of the memory block (Fig. 31, where it illustrates an erase voltage applied to a row of a word line in the memory block.);
applying a well-region erase voltage on the common well-region line, to uniformly apply the well-region erase voltage to all of the channel semiconductor strips in all of the memory subarray layers to erase electrons from all of the first memory cells in a same selected row corresponding to the selected odd word lines and all of the second memory cells in the same selected row corresponding to the selected even word lines (para. 149, "all of the memory cells in a memory block for an erase operation". See also Fig. 31).
As indicated above, Huang, Lee, Shen and Lue are from the same field of endeavor directed to data storage operations on non-volatile 3D memory arrays arranged in rows and columns with vertical gates. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Huang (as modified by Lee and Shen) with the teachings of Lue to employ a sector erase operation for the purpose of permitting the memory to utilize sector erase functionality that would permit subdivisions of a block, instead of the entire block, of memory data to be wiped or to prepare the memory for rewriting.
Regarding claim 10, Huang, Lee and Lue disclose the limitations of claim 3.
As applied, Huang further teaches wherein, each of the channel semiconductor strips of each of the memory subarray layer is connected to a corresponding well-region connection terminal separately, such that each of the channel semiconductor strips has a capability of being applied with a well-region voltage respectively (Fig. 2, where it shows the two channel strips connecting to plugs B1 and B2 respectively such that a different voltage could be applied to each).
Regarding claim 27, Huang, Lee and Shen combined disclose the limitations of claim 1.
Huang, Lee and Shen alone are silent with respect to staggered gate arrangements.
However, Lue teaches wherein two adjacent columns of gate strips are distributed in a staggered manner in the row direction; (Fig. 2 where it illustrates staggered vertical gate topology)
or two adjacent columns of gate strips are aligned in the row direction.
Huang, Lee, Shen and Lue are from the same field of endeavor directed to data storage operations on non-volatile 3D memory arrays arranged in rows and columns with vertical gates. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Huang (as modified by Lee and Shen) with the teachings of Lue to stagger the vertical gates memory array. Doing so would allow a larger memory density (Lue para. 55), and help mitigate read disturb events.
Claims 6, 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (Novel 3D NOR FLASH with Single-Crystal Silicon Channel; “Huang” – of Record) in view of Lee et al. (US 20020080653; “Lee” – of Record) and further in view of Shen (US 20220254803), and further in view of Lue (US 20160056168 – of Record) and further in view of Harari (US 20170092370 – of Record).
Regarding claim 6, Huang, Lee, Shen and Lue combined disclose the limitations of claim 3,
As applied, Lue further discloses applying a second word line selecting voltage to an odd word line or an even word line in a row of the word lines of the memory block (para 145, "word line 105 accesses the memory cell selected for a program operation". It is well known in the art that the term "program" is the same as "write" for non-volatile memory arrays. See also Fig. 30 where it illustrates the program voltage (Vprogram) applied to the target word line.);
applying a first write voltage on a drain-region semiconductor strip corresponding to a selected memory cell of a selected memory subarray layer to inject electrons into a storage structure of the selected memory cell by hot-carrier injection (para. 158, "The bias arrangement state machine 969 is configured to perform memory operations including erase, program, and read, such as a read operation". It is noted that this limitation appears to refer to para. 186-187 in Applicant's specification as that is the only place that it refers to "a first write voltage". However, that section appears to refer to a step "S12b" for which there is no specific corresponding drawing or other reference but appears to be directed to the erase operation. Therefore, for examination purposes, this limitation will be interpreted as performing a standard non-volatile memory program operation in which the drain-region is used for hot-carrier injection to store charge on the floating gate and which is well known in the art. See for example, Lue's program operation above.)
Huang, Lee and Lue are silent with respect to the ability to program a single memory cell.
However, Harari teaches wherein, in response to the memory operation being a write operation of a single one of the memory cells, the control method comprising (para. 7, "To read or program a storage transistor in a NOR string, only that storage transistor needs to be activated"):
Huang, Lee, Shen, Lue and Harari are from the same field of endeavor directed to various data operations on non-volatile memory arrays arranged in rows and columns. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Huang (as modified by Lee, Shen and Lue) with Harari's programming of single memory cells. Doing so would enable finer granularity of memory unit to be programmed thus speeding up the transfer of data.
Regarding claim 11, Huang, Lee, Shen and Lue combined disclose the limitations of claim 10.
As applied, Lue further discloses applying a second word-line selecting voltage to an odd word line or an even word line in a row of the word lines of the memory block (para 145, "word line 105 accesses the memory cell selected for a program operation". It is well known in the art that the term "program" is the same as "write" for non-volatile memory arrays. See also Fig. 30 where it illustrates the program voltage (Vprogram) applied to the target word line.);
applying a second write voltage on a channel semiconductor strip corresponding to a selected memory cell in a selected memory subarray layer to inject electrons into a storage structure of the selected memory cell by F-N tunneling effect (para. 158, "The bias arrangement state machine 969 is configured to perform memory operations including erase, program, and read, such as a read operation". It is noted that this limitation appears to refer to para. 196-199 in Applicant's specification as that is the only place that it refers to both "a second write voltage" and "F-N tunneling". However, that section appears to refer to a step "S12c" for which there is no specific corresponding drawing or other reference but appears to be directed to the erase operation. Therefore, for examination purposes, this limitation will be interpreted as performing a standard non-volatile memory program operation on either the odd or even row of memory cells in which fowler-nordheim tunneling (F-N tunneling) effect is used on the channel to store charge on the floating gate and which is well known in the art. See also para. 155 "One embodiment uses −FN electron programming").
Huang, Lee and Lue are silent with respect to the ability to program a single memory cell.
However, Harari teaches wherein, in response to the memory operation being a write operation of a single one of the memory cells, the control method comprising (para. 7, "To read or program a storage transistor in a NOR string, only that storage transistor needs to be activated").
Huang, Lee, Shen, Lue and Harari are from the same field of endeavor directed to various data operations on non-volatile memory arrays arranged in rows and columns. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Huang (as modified by Lee, Shen and Lue) with the teachings of Harari to program single memory cells. Doing so would enable finer granularity of memory unit to be programmed thus speeding up the transfer of data.
Regarding claim 12, Huang, Lee and Lue disclose the limitations of claim 10
As applied, Lue further discloses applying a third word-line selecting voltage to an odd word line or an even word line in a row of the word lines of the memory block (Fig. 31, where it illustrates an erase voltage applied to a row of a word line in the memory block.);
applying a well-region erase voltage on a channel semiconductor strip corresponding to a selected memory cell in a selected memory subarray layer to erase electrons from a storage structure of the selected memory cell (para. 158, "controller implemented in this example using bias arrangement state machine 969 controls the application of bias arrangement supply voltage generated or provided through the voltage supply or supplies in block 968, such as read, erase, program, erase verify and program verify voltages", "The bias arrangement state machine 969 is configured to perform memory operations including erase, program, and read, such as a read operation by applying a read bias to a selected one of the plurality of word lines, and applying an off bias to two word lines of the plurality of word lines adjacent to the selected one of the plurality of word lines on opposite sides of the selected one of the plurality of word lines". It is noted that while the example given is a bias for a read operation of a single word line, as it is configured to also include erase operations, it is understood that it could perform an erase operation on a single word line (half sector)).
Huang, Lee and Lue are silent with respect to the ability to program a single memory cell.
However, Harari teaches wherein, in response to the memory operation being a write operation of a single one of the memory cells, the control method comprising (para. 7, "To read or program a storage transistor in a NOR string, only that storage transistor needs to be activated").
Huang, Lee, Lue and Harari are from the same field of endeavor directed to various data operations on non-volatile memory arrays arranged in rows and columns. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Huang with the teachings of Lee to program single memory cells. Doing so would enable finer granularity of memory unit to be programmed thus speeding up the transfer of data.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (Novel 3D NOR FLASH with Single-Crystal Silicon Channel; “Huang” – of Record) in view of Lee et al. (US 20020080653; “Lee” – of Record), and further in view of Shen (US 20220254803) as supported by Bendersky (“Memory layout of multi-dimensional arrays” – of Record).
Regarding claim 24, Huang, Lee and Shen disclose the limitations of claim 1.
As applied, Huang further discloses wherein each gate strip is connected to a corresponding word line connection line, and the word line connection line extends along the height direction, and is configured to connect the gate strip to a corresponding word line (Fig. 2(f) where it illustrates word line WL connected to the gate extending in the height direction of the building block array transistor at the top of the structure);
and is configured to realize the connection of the word line to control gates of the memory cells in the memory subarray layers (Fig. 1(a) where it illustrates word lines connected to the control gates SSL0-SSL2).
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the plurality of gate strips in the same row are respectively configured to connect at least one corresponding word line, and each word line extends along the row direction (Fig. 1 where it illustrates the word lines connected above the gate strips. Regarding the Cartesian coordinate notion of “row direction” claimed for the word lines, as supported by Bendersky (pg. 3, para. 2), it is well understood in the art that the standard two-dimensional terms of “rows” and “columns” do not translate to three-dimensional memory structures due to the confusion it causes analyzing circuit topologies in a 3D tensor space. For example, rows and columns are commonly used to define a memory array as a flat 2D plane, but that same array plane can be realized on edge and/or rotated in 3D as it is in Huang’s 3D memory block which appear to orient their word lines in the column direction as defined in the instant application, but has the same circuit topology and connectivity and thus, is identical in structure as illustrated in the Examiner’s Markup above).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement “row” oriented word lines as “column” oriented word lines in a 3D memory array to achieve an identical circuit topology and structure because it is obvious to choose from a finite number of identified and predictable planar transistor orientations with a reasonable expectation of success.
Response to Arguments
Applicant's arguments filed May 20, 2026, have been fully considered but they are not persuasive.
Applicant contends in Remarks that the obviousness rejection of claim 1 is improper due to amending the claim to incorporate new features that the cited references fail to disclose either alone or in combination. Applicant groups the amendments to claim 1 into three sets of “distinguishing technical features” (Features A, B, and C).
Feature A (body structure + plurality of protrusions on both sides + curved concave gate surface)
Applicant argues that Huang discloses continuous planar epitaxial layers and vertical cylindrical gate pillars, and therefore fails to teach (1) semiconductor strips that each comprise a body structure and a plurality of protrusions distributed on both sides in two columns and spaced apart, or (2) a curved concave surface on the gate strips. Applicant further argues that Lee, Lue, Harari, and Bendersky likewise fail to teach Feature A.
These limitations are rejected under 35 U.S.C. § 112(b) as indefinite. When the claim language is read in light of the specification and the drawings (particularly FIGS. 4, 7, and 11), a person of ordinary skill in the art cannot determine with reasonable certainty the metes and bounds of the recited “body structure and a plurality of protrusions… distributed on both sides… spaced apart” and “curved concave surface.” Because the claim is indefinite, the structural distinctions Applicant draws over the previously applied references do not control the patentability analysis.
To the extent a broadest reasonable interpretation can be applied under MPEP § 2173.06, the examiner interprets Feature A as requiring a non-planar, curved interface between the semiconductor regions and the gate structures that increases the effective gate–channel interfacial area. Under that interpretation, the combination of Huang in view of Lee and further in view of Shen renders the claim obvious. Shen expressly teaches, in a three-dimensional NOR architecture, the formation of concave (and convex) curved channel regions against recessed word-line surfaces for the purpose of increasing interfacial area and improving isolation between layers (Shen, para. [0034]; FIGS. 1A–1B). One of ordinary skill would have been motivated to incorporate the curved interface of Shen into the stacked structure of Huang in order to obtain the performance benefits identified in both the instant specification (para. [0105]) and in Shen. Applicant’s arguments directed solely to Huang, Lee, Lue, Harari, and Bendersky do not address the newly applied Shen reference or the interpretation adopted under MPEP § 2173.06.
Features B and C (“at least three” limitations and narrowed column-selection language)
Applicant argues that Huang and Lee fail to teach the change from “a plurality of” to “at least three” memory subarray layers / semiconductor strips / gate strips, and further fail to teach the narrowed column-selection language (“a column of memory cells of a corresponding one of the memory subarray layers to select a memory cell”).
Huang expressly indicates on pg. 1874, col. 2; "A structure of the two-layer devices, as one of the building blocks for n-layer 3D NOR with n > 2 (emphasis added). N>2 meets the required limitation.
Additionally, the numerical limitation “at least three” is a matter of design choice or routine optimization that would have been obvious to one of ordinary skill in the art. The prior art already discloses multi-layer stacked arrays and multiple strips/gates; selecting a specific number such as three does not patentably distinguish the claim.
The narrowed column-selection language describes the conventional selection of a single cell within a selected subarray layer. Huang and Lee already disclose performing row-selection and column-selection operations on a multi-layer memory array. The more specific wording does not impart patentable weight sufficient to overcome the rejection.
Deletion of the single-crystal limitation
Applicant’s deletion of the requirement that each semiconductor strip be a single-crystal semiconductor strip as previously recited in claim 1 is noted. The deletion removes a limitation; it does not add a new distinguishing feature and does not render claim 1 patentable over the applied art.
In summary, for claim 1, none of Applicant’s arguments directed to Features A–C overcome the rejections under 35 U.S.C. §§ 112(b) and 103 set forth in this Office action.
Applicant next contends that the obviousness rejection for claim 2 is improper because Lue’s odd/even arrangement places odd word lines and even word lines in different rows (with vertical gate columns staggered across rows), but requires both an odd word line and an even word line in the same row, with odd gate strips on one side of each column of semiconductor strips and even gate strips on the opposite side of the same column.
This distinction is acknowledged but is not persuasive. Huang (as modified by Lee and Shen) already provides gate structures that interact with the semiconductor regions from multiple sides within the array geometry. Once such dual-sided gate structures are present, assigning the opposing sides to separately controllable word lines (conventionally labeled odd and even) is an obvious design choice for one of ordinary skill in the art. Lue is relied upon to demonstrate that the art already employs odd/even labeling and independent control of adjacent gates. The particular same-row, opposite-sides arrangement follows from Huang’s dual-sided geometry combined with ordinary skill and the conventional odd/even control taught by Lue. Applicant’s argument therefore does not overcome the rejection of claim 2.
With regard to the dependent claims, claim 1 stands rejected under both 35 U.S.C. § 112(b) and § 103, and because the additional limitations of the dependent claims do not patentably distinguish the claims over the applied art for the reasons set forth in the rejections, the dependent claims also remain rejected.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/James S. Wells/Examiner, Art Unit 2825
/Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825
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