DETAILED ACTION
This action is responsive to the Request for Continuing Examination filed November 12, 2025. Claims 1-12, and 21-28 are pending. Claim 1 has been amended. Claim 22-23, 25 and 28 are cancelled. Thus, upon entry Claims 1-12, 21, 24, and 26-27 are currently pending. Claim 1 is independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on November 12, 2025, has been entered.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on December 23, 2025. This IDS has been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: 3D Monolithic Non-Volatile NOR Memory Device.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 21, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (Novel 3D NOR FLASH with Single-Crystal Silicon Channel; “Huang” - of Record) in view of Lee et al. (US 20020080653; “Lee” – of Record)
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Regarding independent claim 1, Huang discloses a control method of a memory block, comprising:
wherein the memory block comprises a plurality of memory subarray layers stacked sequentially along a height direction (Fig. 2a, 2f);
the at least a portion of the selected row of the memory cells comprises at least a portion of the memory cells of each of the memory subarray layers arranged in the selected row (Fig. 1a, 1b, where it illustrates the topology of a row with a word line connecting two transistors through a select transistor); and
each of the memory subarray layers comprises a drain-region semiconductor layer, a channel semiconductor layer, and a source-region semiconductor layer stacked along the height direction (Fig. 2f);
in each of the memory subarray layers, the drain-region semiconductor layer comprises a plurality of drain-region semiconductor strips, the channel semiconductor layer comprises a plurality of channel semiconductor strips, and the source-region semiconductor layer comprises a plurality of source-region semiconductor strips (Fig. 2f);
each drain-region semiconductor strip, each channel semiconductor strip, and each source-region semiconductor strip are distributed along the row direction and extend along a column direction (Fig. 1a, where it illustrates the layers are stacked extending on a horizontal plane orthogonal to the gate as in the instant application);
a plurality of gate strips distributed along the column direction are arranged on each side of each column of the drain-region semiconductor strips, the channel semiconductor strips, and the source-region semiconductor strips (Fig. 1a, where it illustrates the geometry of a 3x3 array of gates within the 3D memory block. It is noted that the topology of the individual transistors, indicating the equivalent of 'strips' in the instant application is evinced);
each of the gate strips extend along the height direction (Fig. 1a);
each row of the word lines is connected to gate strips arranged in a corresponding same row separately (Fig. 1a, WL1 for example);
each of the drain-region semiconductor strips of each of the memory subarray layers is served as a bit line (Fig. 2f. BL0 and BL1 for example).
wherein each drain region semiconductor strip, channel semiconductor strip, and source region semiconductor strip is a single-crystal semiconductor strip, respectively (Fig. 2(a) where it illustrates that layers 1 through 5 (drain, channel, and source) are standard single crystal silicon. Regarding the notion of a "strip", it is observed that while no explicit isolation structures are indicated in Fig. 1(a), the schematic representation of fig. 1(b) clearly indicates that the individual transistors, while grouped as 5-layer common gate pairs (just as in the instant application and sec Examiner's Markup above), arc distinctly separately controllable from the other gate pairs and therefore are necessarily isolated).
Huang is silent with respect to row and column select operations.
However, Lee teaches performing a row-selection operation on at least a portion of at least one row of a plurality of word lines in the memory block to select at least a portion of at least one row of memory cells (para. 39, "The row select circuit 120 supplies the selected word line with a word line voltage necessary for any operation such as a program, erase, read, erase verify or erase repair operation". It is noted that a row-selection operation is well known in the art and necessarily a function of all memory arrays.)
Lee further teaches performing a column-selection operation on at least one column of memory cells of at least one of the memory subarray layers to select at least one memory cell for performing a memory operation (para. 40, " the column select circuit 130 supplies the selected bit lines with a drain voltage necessary for any operation such as a program, erase, read, erase verify or erase repair operation". It is noted that a column selection operation is well known in the art and necessarily a function of all memory arrays.)
Huang and Lee are from the same field of endeavor directed to various data operations on non-volatile memory arrays arranged in rows and columns. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Huang with the teachings of Lee to perform row and column selection on a given memory array. Doing so would allow addressing of the memory cells in an orderly and predictable manner.
Regarding claim 4, Huang and Lee teach the limitations of claim 1,
As applied, Huang further teaches wherein each of the channel semiconductor strips is separately connected to a same common well-region line to uniformly apply a well voltage to all of the channel semiconductor strips (Fig. 2d B1 and B0).
Regarding claim 21, Huang and Lee combined disclose the limitations of claim 1.
As applied, Huang further discloses wherein each drain region semiconductor strip in the same column of the plurality of memory subarray layers is led out through a bit line connection line, and the bit line connection line extends along the height direction (Fig. 1(f) where it illustrates the drain layer steps extending and connecting to vertical connector columns BL1 & BL0 and extending up in the height direction);
each source region semiconductor strip in the same column of the plurality of memory subarray layers is led out through a source connection line, and the source connection line extends along the height direction (Fig. 1(f) where it illustrates the source layer step extending and connecting to vertical connector column SL and extending up in the height direction);
each channel semiconductor strip in the same column of the plurality of memory subarray layers is led out through a well region connection line, and the well region connection line extends along the height direction (Fig. 1(f) where it illustrates the channel layer steps extending and connecting to vertical connector columns B1 & B0 and extending up in the height direction).
Regarding claim 26, Huang and Lee combined disclose the limitations of claim 1.
As applied, Huang further discloses wherein in the height direction, a projection of at least a part of each gate strip coincides with a projection of a part of a corresponding channel semiconductor strip in each memory subarray layer on a projection plane, and the projection plane extends along the height direction and the column direction (Fig. 1(a) where it illustrates the gate structure extending above the oxide plane at the top of the memory array).
Claims 2, 3, 5, 7-10, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (Novel 3D NOR FLASH with Single-Crystal Silicon Channel; “Huang” – of Record) in view of Lee et al. (US 20020080653; “Lee” – of Record) and further in view of Lue (US 20160056168 – of Record).
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Regarding claim 2, Huang and Lee disclose the limitations of claim 1.
As applied, Huang further teaches each of the drain semiconductor strips, the channel semiconductor strips and the source semiconductor strips of each of the memory subarray layers cooperates with the odd gate strips in the odd word-line holes arranged on one side thereof to form a first memory cell (Fig. 2f. It is well known in the art that the source, channel and drain of a given transistor is controlled by its associated gate).
each of the drain semiconductor strips, the channel semiconductor strips and the source semiconductor strips of each the memory subarray layer cooperates with the even gate strips in the even word-line holes arranged on the other side thereof to form second memory cells (Fig. 2f. It is well known in the art that the source, channel and drain of a given transistor is controlled by its associated gate. See also Fig. 1 where it illustrates a plurality of rows of gates with stacked memory cells on both sides.)
Huang and Lee are silent with respect to the vertical gates being arranged in a staggered pattern.
However, Lue teaches each row of the word lines comprise an odd word line and an even word line (para. 55, "Consecutively adjacent word lines can be labeled as alternating between even word lines and odd word lines")
wherein a portion of the memory cells in a same row of the memory subarray layers are connected to an odd word line of a corresponding row separately through odd gate strips in odd word-line holes of the corresponding row (para. 55, "The vertical gate columns electrically coupled to an odd word line are aligned with vertical gate columns electrically coupled to other odd word lines");
the other portion of the memory cells in the same row of the memory subarray layers are connected to an even word line of the corresponding row separately through even gate strips in even word-line holes of the corresponding row (para. 55, "The vertical gate columns electrically coupled to an even word line are aligned with vertical gate columns electrically coupled to other even word lines");
the odd word-line holes are distributed on one side of each column of the drain-region semiconductor strips, the channel semiconductor strips and the source-region semiconductor strips (Fig. 2: odd word lines. Note also para. 3, " The present invention relates to high density memory devices, and particularly to memory devices in which multiple planes of memory cells are arranged to provide a three-dimensional 3D array";
the even word-line holes are distributed on the other side of each column of the drain-region semiconductor strips, the channel semiconductor strips and the source-region semiconductor strips (Fig. 2: even word lines. Note also para. 3, " The present invention relates to high density memory devices, and particularly to memory devices in which multiple planes of memory cells are arranged to provide a three-dimensional 3D array";
all of the first memory cells in a same row of the memory subarray layers are connected to an odd word line of the corresponding same row through the odd gate strips in the odd word-line holes in the corresponding same row (Fig. 2);
all of the second memory cells in a same row of the memory subarray layers are connected to an even number word line of the corresponding same row through the even gate strips in the even word-line holes in the corresponding same row (Fig. 2).
Huang, Lee and Lue are from the same field of endeavor directed to data storage operations on non-volatile 3D memory arrays arranged in rows and columns with vertical gates. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Huang and Lee with the teachings of Lue to stagger the vertical gates memory array. Doing so would allow a larger memory density (Lue para. 55), and help mitigate read disturb events.
Regarding claim 3, Huang, Lee and Lue disclose the limitations of claim 2.
As applied, Lue further discloses wherein, the performing row-selection operation on at least a portion of at least one row of a plurality of rows of the word lines in the memory block to select at least a portion of at least one row of the memory cells, comprises:
performing a row-selection operation on an odd word line of one row of the word lines in the memory block to select one row of the first memory cells, wherein the selected one row of the first memory cells comprises all of the first memory cells in the memory subarray layers arranged in the selected corresponding row (para. 20, "In one embodiment of the technology, the control circuitry performs a read operation by applying a read bias to a selected one of the plurality of word lines and applying an off bias to another word line of the plurality of word lines adjacent to the selected one of the plurality of word lines". The selected word line may be designated as the odd word line corresponding to the first row for example.);
or performing a row-selection operation on an even word line of one row of the word lines in the memory block to select one row of the second memory cells, wherein the selected one row of the second memory cells comprises all of the second memory cells in the memory subarray layers arranged in the selected corresponding row (It is noted that the selection operation described in para. 20 above could be alternately designated as the even word line corresponding to the second row for example.)
Regarding claim 5, Huang, Lee and Lue disclose the limitations of claim 3.
As applied, Lue further discloses wherein, in response to the memory operation being a read operation, the control method comprising:
applying a first word-line selecting voltage to an odd word line or an even word line in a row of the word lines of the memory block (para. 158, "read operation by applying a read bias to a selected one of the plurality of word lines");
applying a read voltage on a drain-region semiconductor strip corresponding to a selected memory cell of a selected memory subarray layer to determine whether the selected memory cell has current passing, for determining whether the selected memory cell has electrons stored therein (para. 158, "The bias arrangement state machine 969 is configured to perform memory operations including erase, program, and read, such as a read operation". It is noted that this limitation appears to refer to para 179 in Applicant's specification as that is the only place that it refers to "applying a read voltage". However, that section appears to refer to a step "S12a" for which there is no specific corresponding drawing or other reference but appears to be directed to the read operation. Therefore, for examination purposes, this limitation will be interpreted as performing a standard non-volatile memory read operation in which the drain-region is the bit line, and which is well known in the art. See for example, Lue's read operation above.)
Regarding claim 7, Huang and Lee disclose the limitations of claim 4.
Huang and Lee alone are silent with respect to a write operation on a portion of the memory array.
However, Lue teaches wherein, in response to the memory operation being a write operation of a half sector of the memory cells (the term "half sector" is unclear. Based on Applicant's specification, for examination purposes, the term will be interpreted to mean "the row of memory cells corresponding to one of either the even or odd word lines"), the control method comprising:
applying a second word line selecting voltage to an odd word line or an even word line in a row of the word lines of the memory block (Fig. 30, where it illustrates both a program and pass voltage applied to adjacent word lines such that only one row (half sector) will be programmed.);
applying a second write voltage on the common well-region line, to uniformly apply the second write voltage to all of the channel semiconductor strips in all of the memory subarray layers to inject electrons into all of the first memory cells in a same selected row corresponding to the selected odd word line or to inject electrons into all of the second memory cells in a same selected row corresponding to the selected even word lines by F-N tunneling effect (para. 158, "The bias arrangement state machine 969 is configured to perform memory operations including erase, program, and read, such as a read operation". It is noted that this limitation appears to refer to para. 196-199 in Applicant's specification as that is the only place that it refers to both "a second write voltage" and "F-N tunneling". However, that section appears to refer to a step "S12c" for which there is no specific corresponding drawing or other reference but appears to be directed to the erase operation. Therefore, for examination purposes, this limitation will be interpreted as performing a standard non-volatile memory program operation on either the odd or even row of memory cells in which fowler-nordheim tunneling (F-N tunneling) effect is used on the channel to store charge on the floating gate and which is well known in the art. See also para. 155 "One embodiment uses −FN electron programming").
As indicated above, Huang, Lee and Lue are from the same field of endeavor directed to data storage operations on non-volatile 3D memory arrays arranged in rows and columns with vertical gates. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Huang and Lee with the teachings of Lue to employ a write operation for the purpose of permitting the memory to utilize its required storage function.
Regarding claim 8, Huang and Lee disclose the limitations of claim 4.
Huang and Lee alone are silent with respect to an erase operation on a portion of the memory array.
However, Lue teaches wherein, in response to the memory operation being an erase operation of a half sector of the memory cells (the term "half sector" is unclear. Based on Applicant's specification, for examination purposes, the term will be interpreted to mean "the row of memory cells corresponding to one of either the even or odd word lines"), the control method comprising:
applying a third word-line selecting voltage to an odd word line or an even word line in a row of the word lines of the memory block (Fig. 31, where it illustrates an erase voltage applied to a row of a word line in the memory block.);
applying a well-region erase voltage on the common well-region line, to uniformly apply the well-region erase voltage to all of the channel semiconductor strips in all of the memory subarray layers to erase electrons from all of the first memory cells in a same selected row corresponding to the selected odd word lines or to erase electrons from all of the second memory cells in a same selected row corresponding to the selected even word lines (para. 158, "controller implemented in this example using bias arrangement state machine 969 controls the application of bias arrangement supply voltage generated or provided through the voltage supply or supplies in block 968, such as read, erase, program, erase verify and program verify voltages", "The bias arrangement state machine 969 is configured to perform memory operations including erase, program, and read, such as a read operation by applying a read bias to a selected one of the plurality of word lines, and applying an off bias to two word lines of the plurality of word lines adjacent to the selected one of the plurality of word lines on opposite sides of the selected one of the plurality of word lines". It is noted that while the example given is a bias for a read operation of a single word line, as it is configured to also include erase operations, it is understood that it could perform an erase operation on a single word line (half sector)).
As indicated above, Huang, Lee and Lue are from the same field of endeavor directed to data storage operations on non-volatile 3D memory arrays arranged in rows and columns with vertical gates. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Huang and Lee with the teachings of Lue to employ an erase operation for the purpose of permitting the memory to utilize erase functionality that would permit the memory data to be wiped or to prepare the memory for rewriting.
Regarding claim 9, Huang and Lee disclose the limitations of claim 4.
Huang and Lee alone are silent with respect to an erase operation on a sector of the memory array.
However, Lue teaches wherein, in response to the memory operation being an erase operation of a sector of the memory cells, the control method comprising (para. 149, "word lines 103-107 access all of the memory cells in a memory block for an erase operation". See also Fig. 31 where it illustrates the erase voltage (Verase) applied to the word line.):
applying a third word-line selecting voltage to an odd word line and an even word line in a row of the word lines of the memory block (Fig. 31, where it illustrates an erase voltage applied to a row of a word line in the memory block.);
applying a well-region erase voltage on the common well-region line, to uniformly apply the well-region erase voltage to all of the channel semiconductor strips in all of the memory subarray layers to erase electrons from all of the first memory cells in a same selected row corresponding to the selected odd word lines and all of the second memory cells in the same selected row corresponding to the selected even word lines (para. 149, "all of the memory cells in a memory block for an erase operation". See also Fig. 31).
As indicated above, Huang, Lee and Lue are from the same field of endeavor directed to data storage operations on non-volatile 3D memory arrays arranged in rows and columns with vertical gates. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Huang and Lee with the teachings of Lue to employ a sector erase operation for the purpose of permitting the memory to utilize sector erase functionality that would permit subdivisions of a block, instead of the entire block, of memory data to be wiped or to prepare the memory for rewriting.
Regarding claim 10, Huang, Lee and Lue disclose the limitations of claim 3.
As applied, Huang further teaches wherein, each of the channel semiconductor strips of each of the memory subarray layer is connected to a corresponding well-region connection terminal separately, such that each of the channel semiconductor strips has a capability of being applied with a well-region voltage respectively (Fig. 2, where it shows the two channel strips connecting to plugs B1 and B2 respectively such that a different voltage could be applied to each).
Regarding claim 27, Huang and Lee combined disclose the limitations of claim 1.
As applied, Lue further discloses wherein two adjacent columns of gate strips are distributed in a staggered manner in the row direction; (Fig. 2 where it illustrates staggered vertical gate topology)
or two adjacent columns of gate strips are aligned in the row direction.
Huang, Lee and Lue are from the same field of endeavor directed to data storage operations on non-volatile 3D memory arrays arranged in rows and columns with vertical gates. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Huang and Lee with the teachings of Lue to stagger the vertical gates memory array. Doing so would allow a larger memory density (Lue para. 55), and help mitigate read disturb events.
Claims 6, 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (Novel 3D NOR FLASH with Single-Crystal Silicon Channel; “Huang” – of Record) in view of Lee et al. (US 20020080653; “Lee” – of Record) and further in view of Lue (US 20160056168 – of Record) and further in view of Harari (US 20170092370 – of Record).
Regarding claim 6, Huang, Lee and Lue disclose the limitations of claim 3,
As applied, Lue further discloses applying a second word line selecting voltage to an odd word line or an even word line in a row of the word lines of the memory block (para 145, "word line 105 accesses the memory cell selected for a program operation". It is well known in the art that the term "program" is the same as "write" for non-volatile memory arrays. See also Fig. 30 where it illustrates the program voltage (Vprogram) applied to the target word line.);
applying a first write voltage on a drain-region semiconductor strip corresponding to a selected memory cell of a selected memory subarray layer to inject electrons into a storage structure of the selected memory cell by hot-carrier injection (para. 158, "The bias arrangement state machine 969 is configured to perform memory operations including erase, program, and read, such as a read operation". It is noted that this limitation appears to refer to para. 186-187 in Applicant's specification as that is the only place that it refers to "a first write voltage". However, that section appears to refer to a step "S12b" for which there is no specific corresponding drawing or other reference but appears to be directed to the erase operation. Therefore, for examination purposes, this limitation will be interpreted as performing a standard non-volatile memory program operation in which the drain-region is used for hot-carrier injection to store charge on the floating gate and which is well known in the art. See for example, Lue's program operation above.)
Huang, Lee and Lue are silent with respect to the ability to program a single memory cell.
However, Harari teaches wherein, in response to the memory operation being a write operation of a single one of the memory cells, the control method comprising (para. 7, "To read or program a storage transistor in a NOR string, only that storage transistor needs to be activated"):
Huang, Lee, Lue and Harari are from the same field of endeavor directed to various data operations on non-volatile memory arrays arranged in rows and columns. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Huang with the teachings of Lee to program single memory cells. Doing so would enable finer granularity of memory unit to be programmed thus speeding up the transfer of data.
Regarding claim 11, Huang, Lee and Lue disclose the limitations of claim 10.
As applied, Lue further discloses applying a second word-line selecting voltage to an odd word line or an even word line in a row of the word lines of the memory block (para 145, "word line 105 accesses the memory cell selected for a program operation". It is well known in the art that the term "program" is the same as "write" for non-volatile memory arrays. See also Fig. 30 where it illustrates the program voltage (Vprogram) applied to the target word line.);
applying a second write voltage on a channel semiconductor strip corresponding to a selected memory cell in a selected memory subarray layer to inject electrons into a storage structure of the selected memory cell by F-N tunneling effect (para. 158, "The bias arrangement state machine 969 is configured to perform memory operations including erase, program, and read, such as a read operation". It is noted that this limitation appears to refer to para. 196-199 in Applicant's specification as that is the only place that it refers to both "a second write voltage" and "F-N tunneling". However, that section appears to refer to a step "S12c" for which there is no specific corresponding drawing or other reference but appears to be directed to the erase operation. Therefore, for examination purposes, this limitation will be interpreted as performing a standard non-volatile memory program operation on either the odd or even row of memory cells in which fowler-nordheim tunneling (F-N tunneling) effect is used on the channel to store charge on the floating gate and which is well known in the art. See also para. 155 "One embodiment uses −FN electron programming").
Huang, Lee and Lue are silent with respect to the ability to program a single memory cell.
However, Harari teaches wherein, in response to the memory operation being a write operation of a single one of the memory cells, the control method comprising (para. 7, "To read or program a storage transistor in a NOR string, only that storage transistor needs to be activated").
Huang, Lee, Lue and Harari are from the same field of endeavor directed to various data operations on non-volatile memory arrays arranged in rows and columns. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Huang with the teachings of Lee to program single memory cells. Doing so would enable finer granularity of memory unit to be programmed thus speeding up the transfer of data.
Regarding claim 12, Huang, Lee and Lue disclose the limitations of claim 10
As applied, Lue further discloses applying a third word-line selecting voltage to an odd word line or an even word line in a row of the word lines of the memory block (Fig. 31, where it illustrates an erase voltage applied to a row of a word line in the memory block.);
applying a well-region erase voltage on a channel semiconductor strip corresponding to a selected memory cell in a selected memory subarray layer to erase electrons from a storage structure of the selected memory cell (para. 158, "controller implemented in this example using bias arrangement state machine 969 controls the application of bias arrangement supply voltage generated or provided through the voltage supply or supplies in block 968, such as read, erase, program, erase verify and program verify voltages", "The bias arrangement state machine 969 is configured to perform memory operations including erase, program, and read, such as a read operation by applying a read bias to a selected one of the plurality of word lines, and applying an off bias to two word lines of the plurality of word lines adjacent to the selected one of the plurality of word lines on opposite sides of the selected one of the plurality of word lines". It is noted that while the example given is a bias for a read operation of a single word line, as it is configured to also include erase operations, it is understood that it could perform an erase operation on a single word line (half sector)).
Huang, Lee and Lue are silent with respect to the ability to program a single memory cell.
However, Harari teaches wherein, in response to the memory operation being a write operation of a single one of the memory cells, the control method comprising (para. 7, "To read or program a storage transistor in a NOR string, only that storage transistor needs to be activated").
Huang, Lee, Lue and Harari are from the same field of endeavor directed to various data operations on non-volatile memory arrays arranged in rows and columns. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Huang with the teachings of Lee to program single memory cells. Doing so would enable finer granularity of memory unit to be programmed thus speeding up the transfer of data.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (Novel 3D NOR FLASH with Single-Crystal Silicon Channel; “Huang” – of Record) in view of Lee et al. (US 20020080653; “Lee” – of Record) as supported by Bendersky (“Memory layout of multi-dimensional arrays” – of Record).
Regarding claim 24, Huang and Lee disclose the limitations of claim 1.
As applied, Huang further discloses wherein each gate strip is connected to a corresponding word line connection line, and the word line connection line extends along the height direction, and is configured to connect the gate strip to a corresponding word line (Fig. 2(f) where it illustrates word line WL connected to the gate extending in the height direction of the building block array transistor at the top of the structure);
and is configured to realize the connection of the word line to control gates of the memory cells in the memory subarray layers (Fig. 1(a) where it illustrates word lines connected to the control gates SSL0-SSL2).
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the plurality of gate strips in the same row are respectively configured to connect at least one corresponding word line, and each word line extends along the row direction (Fig. 1 where it illustrates the word lines connected above the gate strips. Regarding the Cartesian coordinate notion of “row direction” claimed for the word lines, as supported by Bendersky (pg. 3, para. 2), it is well understood in the art that the standard two-dimensional terms of “rows” and “columns” do not translate to three-dimensional memory structures due to the confusion it causes analyzing circuit topologies in a 3D tensor space. For example, rows and columns are commonly used to define a memory array as a flat 2D plane, but that same array plane can be realized on edge and/or rotated in 3D as it is in Huang’s 3D memory block which appear to orient their word lines in the column direction as defined in the instant application, but has the same circuit topology and connectivity and thus, is identical in structure as illustrated in the Examiner’s Markup above).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement “row” oriented word lines as “column” oriented word lines in a 3D memory array to achieve an identical circuit topology and structure because it is obvious to choose from a finite number of identified and predictable planar transistor orientations with a reasonable expectation of success.
Response to Arguments
Applicant's arguments filed November 12, 2025, have been fully considered but they are not persuasive.
Applicant contends that the obviousness rejection of claim 1 is improper due to amending the claim to incorporate the features of previously rejected dependent claim 28 and that the cited reference (Huang) fails to disclose the following features:
“…each drain region semiconductor strip, channel semiconductor strip, and source region semiconductor strip is a single-crystal semiconductor strip, respectively” (referred to as distinguishing technical features A on pg. 10 of Remarks).
“the memory block comprises a plurality of memory subarray layers stacked sequentially along a height direction” (referred to as distinguishing technical features B on pg. 10 of Remarks).
“each drain-region semiconductor strip, each channel semiconductor strip, and each source-region semiconductor strip are distributed along the row direction and extend along a column direction” (referred to as distinguishing technical features C on pg. 10 of Remarks).
To support their argument for (1) - technical feature A, applicant asserts that Huang does not disclose any specific process parameters or operations related to a single-crystal growth technology. Additionally, that Huang also fails to disclose how to form a single-crystal semiconductor strip in the 3D NOR flash memory array structure. And finally, applicant alleges a number of technical reasons that the structure of Huang is thought to be difficult to realize (although it is noted that Huang provides evidence of the physical device (cross section SEM photos of various relevant physical features in Fig. 3 for example) and actual test and use data from the resultant operational device (Fig. 4 and 5).
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
More specifically, the above purported deficiencies appear not to be directed to the elected invention (a control method of a memory block), but rather to the manufacturing of 3D memory arrays for which all claims were withdrawn without traverse in the response to restriction/election filed February 3, 2025. The process and techniques of manufacturing are features which are not currently claimed and as such, are not addressed in the rejection. As cited, Huang reads on the limitations of claim 1 because it discloses that the memory device comprises single-crystal layers for source, channel and drain as indicated in the rejection above. Additionally, with regard to applicant’s contention on pg. 12 of Remarks that further epitaxial layers would not be able to be grown directly above Huang’s insulating layer (Oxide) at the top of the two-layer memory subarray depicted, it is unclear how this distinguishes from the instant application as it is noted that applicant’s device has a similar “interlayer isolation strip” (Fig. 4: 14a – “Ox”) which appears to have epitaxial silicon layers both above and below it and would thus seem to contradict their argument.
To support their argument for (2) - technical feature B, applicant asserts both that Huang must be exaggerating the number of stacked layers possible while only demonstrating a two-layer memory subarray, and that the term “plurality” should apparently be taken to mean “at least three”.
It widely understood in patent law and the standards of practice that the term “plurality” is taken to precisely mean “two or more”. Applicant’s exhibit and suggestion on pg. 17 of Remarks regarding the definition of the term “plurality” is “more than two” is not well taken. Clearly, without cherry picking individual words, the offered 3c alternate definition indicates specific applicability to the “number of votes” in a context where there are “more than two candidates” which is inapposite to the limitations as claimed.
Further, with regard to Huang’s recitation of the number of potential stacked layers, it is noted that regardless of the plausibility of the maximum number of layers the technique could realize, as claimed and disclosed in the specification as well as figures 4 and 11 of the instant application, only two memory subarrays are required and as such, Huang is found to read on the limitation as indicated in the rejection above.
To support their argument for (3) – technical feature C, applicant asserts that Bendersky (a reference for claim 24) is not from the same field of endeavor as the instant application.
It is first noted that Bendersky is not cited in the rejection of claim 1. It is however, cited merely in support of Lee reference of the rejection of claim 24. But applicant has indicated no argument or finding of error for claim 24 in their remarks. That notwithstanding, as applicant states on pg. 19 of Remarks, Bendersky is directed to the field of math and as such, it is well understood in the art that math is fundamental to the field of semiconductor devices and in particular, memory arrays and is therefore reasonably pertinent to the particular problem which the inventor is involved and would qualify as a reference for obviousness determination.
However, it is understood that applicant’s argument appears to be concerned with the claimed feature of the explicit directionality of the transistor topology with respect to the terms “rows” and “columns”. It is well understood in the art of memory arrays that the terminology of rows and columns is decedent from, and inherently represents a two-dimensional concept which is not physically or functionally definitive when used in relation to a three-dimensional memory array. What is considered a column depends on the orientation of the observer when considering a 3D array. An observer from a top view perspective would have a different understanding of the transistors that may make up a column from an observer at a side view for example. To be dimensionally precise when disclosing and comparing memory arrays, one must compare the actual transistor connectivity. In the rejection of claim 1 above, it is noted that the schematic of the building-block NOR structure of Huang is identical to that of the instant application. As such, it is found that Huang reads on the limitation.
For at least these reasons, the rejection of independent claim 1 is deemed proper and maintained.
Conclusion
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/James S. Wells/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825