CTFR 18/147,396 CTFR 100255 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Status of the Claims Claims 20-34 and 36-41 are pending in the application and are currently being examined. Claims 20, 25, and 32-34 have been amended. Claims 1-19 and 35 have been canceled. No new claims have been added. Response to Arguments 07-37 AIA Applicant's arguments filed 2/27/2026 have been fully considered but they are not persuasive. Regarding the argument that Liou does not teach or suggest all of the features of amended independent claim 20 as stated on page 7 of Remarks, Examiner respectfully disagrees. Applicant states that “Liou does not teach or suggest a “sacrificial layer disposed on the barrier layer,” of that a “surface of the sacrificial layer” is “coplanar with” a “second end of the conductive via,” as recited in independent claim 20” on page 8 of Remarks. However, Examiner argues that layer IMD--- x+1 exists both as a barrier layer as well as a sacrificial layer. As stated in the prior art rejection of 10/28/2025 of claim 25, layer IMD x+1 is formed similarly to the other IMD and ILD layers. Both IMD x-1 and IMD x+1 are etched, with layer IMD x-1 etched for V x-1 and IMD x+1 being etched for bonding wire or bump. The IMD layers are already barrier layers, and the etching step involved makes the IMD layers sacrificial as well. This would mean that if IMD x+1 were a multi-layered layer, the additional layers would also be both barrier layers and sacrificial layers. These layers are also coplanar with the second end of the conductive via, because layer IMD x+1 is coplanar with the second end, and making a multi-layered layer in the same region would still be coplanar. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Specifically regarding Applicant’s argument of newly amended claim 32, amended to include limitations of dependent claim 35, the argument appears to assert that the liner of Li is not analogous to the silicon nitride layer discussed in Liou due to the lack of the similar features (i.e. metal layers, conductive via, overcoat layer) existing in Liou. Examiner agrees that these features are not in Li, but the features exist in the combined device of Liou in view of Li. Liou is silent on a thickness of a silicon nitride layer in a magnetoresistive device, something that Li rectifies. Li does not require the limitations of independent claim 32, as it is used is a secondary reference to Liou to remedy deficiencies of Liou. Regarding the argument that neither Liou nor Li teach or suggest “wherein the silicon nitride layer is at least partially transparent to ultraviolet (UV) light” as on page 10 of Remarks, Examiner agrees. However, as this is a new limitation not previously presented, another reference is being brought in to teach this new limitation, as seen in the rejection to follow. Regarding the assertion that “the combination of characteristics is novel and nonobvious because it addresses a technical problem that is not contemplated by either Liou or Li” as stated on page 10 of Remarks, Examiner respectfully disagrees. While Liou or Li may not explicitly discuss the technical problem, as long as the combined device contains the structures claimed as claimed, the combined device would provide characteristics as described. Regarding the arguments of the dependent claims, as the arguments are “the same reasons [as] independent claims 20 and 32”, the arguments will not be repeated here and Examiner refers back to the above arguments and the rejection to follow . Claim Rejections - 35 USC § 103 07-103 AIA The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. 07-15-aia AIA Claim(s) 20-22 and 24-25 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Liou et al. (US 2015/0340594 A1, hereafter Liou) . Regarding claim 20, Fig. 3 of Liou teaches a semiconductor device, comprising: a substrate (substrate, [0040]) including a semiconductor circuit (layer with transistors T, [0044]); a dielectric layer (IMD_x, [0044]) disposed over the substrate (substrate), the dielectric layer (IMD_x) including a conductive pad (M_x) coupled to the semiconductor circuit (layer with transistors T) (Liou states in [0045] that a contact plug C makes an electrical connection from the transistors T to the interconnect structure above); a barrier layer (IMD_x+1, [0048]) disposed on the dielectric layer (IMD_x); a conductive via (1010* and V_x, [0050]) with a first end (see annotated Fig. 3) connected to the conductive pad (M_x, [0048]), the conductive via (1010* and V_x) extending from the conductive pad (M_x) through the dielectric layer (IMD_x) and the barrier layer (IMD_x+1); and an anisotropic magneto-resistive (AMR) stack (magnetoresistive material layer 2000, [0039], defined to be a layer or a stack in [0034]) disposed over the barrier layer (IMD_x+1), wherein the AMR stack (2000) is in contact with a second end (see annotated Fig. 3) of the conductive via (1010* and V_x) opposite the first end. While Liou does not explicitly show a sacrificial layer disposed on the barrier layer in Fig. 3, [0050] describes this layer as being formed similar to the rest of the interconnect structures, such as the ILD layers. Then, [0045] states the ILD layers can be a single layer or multi-layered. This would make a second layer in the barrier layer (IMD_x+1), referred to here as a sacrificial layer in part due to it being etched away for placing a bonding wire or bump, an obvious variant in Liou. As the conductive via (1010* and V_x) extends through the entirety of the now multi-layered barrier layer (IMD_x+1), the conductive via (1010* and V_x) extends through the sacrificial layer. Liou also teaches the second end of the conductive via (1010* and V_x) is coplanar with a surface of the sacrificial layer (IMD_x+1) as the sacrificial layer is a part of layer IMD_x+1, which is itself coplanar with the second end of the conductive via (see annotated Fig. 3). PNG media_image1.png 504 740 media_image1.png Greyscale Regarding claim 21, Fig 3 of Liou teaches the semiconductor device of claim 20, further comprising: a passivation layer (passivation layer, [0048]) covering the AMR stack (magnetoresistive layer 2000, [0039]). Regarding claim 22, Fig 3 of Liou teaches the semiconductor device of claim 20, wherein the AMR stack (magnetoresistive layer 2000, [0049]) includes a layer of NiFe alloy [0040], and wherein the layer of NiFe alloy is in contact with the second end of the conductive via (1010* and V_x, [0050], see annotated Fig. 3). PNG media_image1.png 504 740 media_image1.png Greyscale Regarding claim 24, Fig 3 of Liou teaches the semiconductor device of claim 22, wherein the second end of the conductive via (1010* and V_x, [0050]) is coplanar with a surface of the barrier layer (IMD_x+1, [0048]), and wherein the layer of NiFe alloy (magnetoresistive layer 2000, [0049]) is disposed on the surface of the barrier layer (IMD_x+1). Regarding claim 25, Fig 3 of Liou teaches the semiconductor device of claim 22, wherein the layer of NiFe alloy (magnetoresistive layer 2000, [0049]) is disposed on the surface of the sacrificial layer (IMD_x+1, [0048]) . 07-21-aia AIA Claim (s) 23 and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liou in view of Berry et al. (US 2018/0315599 A1, hereafter Berry) and Zenke et al. (US Pat. 5,525,540 A, hereafter Zenke) . Regarding claim 23, Fig 3 of Liou teaches the semiconductor device of claim 22, wherein the barrier layer (IMD_x+1, [0048]) blocks Ni or Fe atoms of the AMR stack (magnetoresistive material layer 2000, [0039]) from diffusing through the barrier layer (IMD_x+1). While Liou is silent of the barrier layer blocking Ni or Fe atoms of the AMR stack, [0050] describes this layer as being formed similar to the rest of the interconnect structures, such as the ILD layers. Then, [0045] states the ILD layers can be formed of silicon nitride, which is known in the art to block Ni atoms as taught by Berry [0021] and Zenke (column 4 lines 13-17). Regarding claim 27, Fig 3 of Liou teaches the semiconductor device of claim 20, wherein the barrier layer (IMD_x+1, [0048]) blocks one or more constituent atoms of the AMR stack (magnetoresistive material layer 2000, [0039]) from diffusing through the barrier layer (IMD_x+1). While Liou is silent of the barrier layer blocking constituent atoms of the AMR stack (Ni or Fe atoms of Liou, [0019]), [0050] describes this layer as being formed similar to the rest of the interconnect structures, such as the ILD layers. Then, [0045] states the ILD layers can be formed of silicon nitride, which is known in the art to block Ni atoms as taught by Berry [0021] and Zenke (column 4 lines 13-17) . 07-21-aia AIA Claim (s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liou in view of Yin et al. (US 2022/0328758 A1, hereafter Yin) . Regarding claim 26, Fig 3 of Liou teaches the semiconductor device of claim 20, wherein the sacrificial layer includes a tetraethyl orthosilicate (TEOS) layer (Liou discloses the ILD layers can be formed TEOS [0045]). Liou is silent on the TEOS layer having a thickness ranging from approximately 5 to approximately 30 nanometers (nm). This would lead one of ordinary skill in the art to select a thickness of a TEOS layer that is known to be used in a magnetoresistive device. Yin teaches a thickness of a TEOS layer to be 20 nm [0023], within the range of the present application . 07-21-aia AIA Claim (s) 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liou as in view of Winarski et al. (US 2005/0231846 A1, hereafter Winarski) . Regarding claim 28, Fig 3 of Liou teaches the semiconductor device of claim 20. While Liou does not explicitly teach the semiconductor circuit (layer with transistors T, [0044]) includes one or more components configured to alter data stored therein in response to receiving ultraviolet (UV) light, Liou does state that the active devices can include memory cells [0045]. One of ordinary skill in the art would know to include a memory cell already known before the effective filing date that is known to work within a magneto-resistive device. Winarski discloses an electrically programmable read only memory (EPROM) cell within their magneto-resistive device [0035]. This EPROM is known to be erased with UV light ([0035] of Winarski). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Liou to include the EPROM of Winarski to get the expected result of a functional memory device . 07-21-aia AIA Claim (s) 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liou in view of Winarski in further view of Huynh et al. (US 2017/0316834 A1, hereafter Huynh) . Regarding claim 29, Fig 3 of Liou in view of Winarski teach the semiconductor device of claim 28, wherein the one or more components include an electrically programmable read only memory (EPROM). Liou in view of Winarski fail to explicitly state the EPROM has a floating gate, though Huynh indicates floating gates within EPROM are known in the art [0010] . 07-21-aia AIA Claim (s) 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liou in view of Chang et al. (US Pat. 9,589,969 B1, hereafter Chang) . Regarding claim 30, Fig 3 of Liou teaches the semiconductor device of claim 20. Liou is silent on the barrier layer (IMD_x+1, [0048]) transmits ultraviolet (UV) light to the semiconductor circuit (layer with transistors T, [0044]). However, Liou discloses the barrier layer as being formed similar to the rest of the interconnect structures, such as the ILD layers [0045]. Then, [0045] states the ILD layers can formed of silicon nitride. This material is known in the art to have high ultraviolet transmittance, as stated by Chang in column 4 lines 18-23 . 07-21-aia AIA Claim (s) 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liou in view of Li et al. (US 2022/0285606 A1, hereafter Li) . Regarding claim 31, Fig 3 of Liou teaches the semiconductor device of claim 20, wherein the barrier layer includes a silicon nitride (SiN) layer (IMD_x+1, [0045] and [0048]). Liou is silent on the barrier layer having a thickness ranging from approximately 20 to approximately 100 nanometers (nm). This would lead one of ordinary skill in the art to select a thickness of a SiN layer that is known to be used in a magnetoresistive device. Li teaches a thickness of a SiN layer to be 20 nm [0040], within the range of the present application . 07-21-aia AIA Claim (s) 32, 34, 36, and 38-39 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liou in view of Li in view of Someya (US 2016/0005744 A1) . Regarding claim 32, Fig 3 of Liou teaches a semiconductor device, comprising: a substrate (substrate, [0040]) including a semiconductor circuit (layer with transistors T, [0044]); a protective overcoat layer (IMD_x, [0044]) disposed over the substrate (substrate), the protective overcoat layer (IMD_x) including a conductive pad (M_x, [0048]) coupled to the semiconductor circuit (layer with transistors T); a silicon nitride layer (IMD_x+1, [0045] and [0048]) disposed on the protective overcoat layer (IMD_x); a conductive via (1010* and V_x, [0050]) with a first end (see annotated Fig. 3) connected to the conductive pad (M_x), the conductive via (1010* and V_x) extending from the conductive pad (M_x) through the protective overcoat layer (IMD_x) and the silicon nitride layer (IMD_x+1) (Liou states in [0045] that a contact plug C makes an electrical connection from the transistors T to the interconnect structure above); and an anisotropic magneto-resistive (AMR) stack (magnetoresistive material layer 2000, [0039], defined to be a layer or a stack in [0034]) disposed over the silicon nitride layer (IMD_x+1), wherein the AMR stack (2000) is in contact with a second end (see annotated Fig. 3) of the conductive via (1010* and V_x) opposite the first end. Liou is silent on the SiN layer having a thickness ranging from approximately 20 to approximately 100 nanometers (nm). This would lead one of ordinary skill in the art to select a thickness of a SiN layer that is known to be used in a magnetoresistive device. Li teaches a thickness of a SiN layer to be 20 nm [0040], within the range of the present application. Liou in view of Li fail to explicitly teach the silicon nitride layer is at least partially transparent to UV light. However, silicon nitride with a thickness of 20 nm is known in the art to allow transmission of UV light, as Someya teaches in [0014] and Fig. 3. Someya specifically teaches a thinner silicon nitride film (of 20 nm or less) allows for a quick erasure time for the device [0016] as well as still preventing moisture from penetrating the device [0014]. Regarding claim 34, Fig 3 of Liou in view of Li in view of Someya teaches the semiconductor device of claim 32. While Liou in view of Li is silent on silicon nitride layer (IMD_x+1, [0045] and [0048]) transmits ultraviolet (UV) light to the semiconductor circuit (layer with transistors T, [0044]). However, silicon nitride with a thickness of 20 nm is known in the art to allow transmission of UV light, as Someya (US 2016/0005744 A1) teaches in [0014] and Fig. 3. As the semiconductor circuit is below the silicon nitride layer, the UV light would penetrate to the semiconductor circuit. Regarding claim 36, Fig 3 of Liou in view of Li in view of Someya teaches the semiconductor device of claim 32, wherein the AMR stack (magnetoresistive material layer 2000, [0039]) includes a layer of NiFe alloy [0040], and wherein the layer of NiFe alloy (magnetoresistive layer 2000, [0049]) is in contact with the second end (see annotated Fig. 3) of the conductive via (1010* and V_x, [0050]). Regarding claim 38, Fig 3 of Liou in view of Li in view of Someya teaches the semiconductor device of claim 36, wherein the second end (see annotated Fig. 3) of the conductive via (1010* and V_x, [0050]) is coplanar with a surface of the silicon nitride layer (IMD_x+1, [0048]), and wherein the layer of NiFe alloy (magnetoresistive layer 2000, [0049]) is disposed on the surface of the silicon nitride layer (IMD_x+1). Regarding claim 39, Fig 3 of Liou in view of Li in view of Someya teaches the semiconductor device of claim 36, wherein the second end (see annotated Fig. 3) of the conductive via (1010* and V_x, [0050]) is coplanar with a surface of a tetraethyl orthosilicate (TEOS) layer disposed on the silicon nitride layer (IMD_x+1, [0048]), and wherein the layer of NiFe alloy (magnetoresistive layer 2000, [0049]) is disposed on the surface of the TEOS layer. While Liou does not explicitly show a sacrificial layer disposed on the barrier layer in Fig. 3, [0050] describes this layer as being formed similar to the rest of the interconnect structures, such as the ILD layers. Then, [0045] states the ILD layers can be a single layer or multi-layered. Liou further discloses the ILD layers can be formed of either silicon nitride or TEOS. This would make a TEOS layer disposed on the silicon nitride layer an obvious variant in Liou . 07-21-aia AIA Claim (s) 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liou in view of Li in view of Someya in view of Winarski and in further view of Huynh et al. (US 2017/0316834 A1, hereafter Huynh) . Regarding claim 33, Fig 3 of Liou in view of Li in view of Someya teaches the semiconductor device of claim 32, wherein the semiconductor circuit (layer with transistors T, [0044]). While Liou in view of Li in view of Someya does not explicitly state the circuit includes an electrically programmable read only memory (EPROM) having a floating gate, the EPROM configured to alter data stored therein in response to ultraviolet (UV) light, Liou does state that the active devices can include memory cells [0045]. One of ordinary skill in the art would know to include a memory cell already known before the effective filing date that is known to work within a magneto-resistive device. Winarski discloses an electrically programmable read only memory (EPROM) cell within their magneto-resistive device [0035]. This EPROM is known to be erased with UV light ([0035] of Winarski). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Liou to include the EPROM of Winarski to get the expected result of a functional memory device. Liou in view of Winarski fail to explicitly state the EPROM has a floating gate, though Huynh indicates floating gates within EPROM are known in the art [0010] . 07-21-aia AIA Claim (s) 37 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liou in view of Li in view of Someya in view of Berry et al. (US 2018/0315599 A1, hereafter Berry) and Zenke et al. (US Pat. 5,525,540 A, hereafter Zenke) . Regarding claim 37, Fig 3 of Liou in view of Li in view of Someya teaches the semiconductor device of claim 36, wherein the silicon nitride layer (IMD_x+1, [0048]) blocks Ni or Fe atoms of the AMR stack (magnetoresistive material layer 2000, [0039]) from diffusing through the silicon nitride layer (IMD_x+1). While Liou in view of Li in view of Someya is silent of the barrier layer blocking Ni or Fe atoms of the AMR stack, [0050] describes this layer as being formed similar to the rest of the interconnect structures, such as the ILD layers. Then, [0045] states the ILD layers can be formed of silicon nitride, which is known in the art to block Ni atoms as taught by Berry [0021] and Zenke (column 4 lines 13-17) . 07-21-aia AIA Claim (s) 26 and 40 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liou in view of Li in view of Someya in view of Yin et al. (US 2022/0328758 A1, hereafter Yin) . Regarding claim 40, Fig 3 of Liou in view of Li in view of Someya teaches the semiconductor device of claim 39. Liou in view of Li in view of Someya is silent on the TEOS layer having a thickness ranging from approximately 5 to approximately 30 nanometers (nm). This would lead one of ordinary skill in the art to select a thickness of a TEOS layer that is known to be used in a magnetoresistive device. Yin teaches a thickness of a TEOS layer to be 20 nm [0023], within the range of the present application . 07-21-aia AIA Claim (s) 41 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liou in view of Li in view of Someya in view of Wu et al. (US 2020/0044146 A1, hereafter Wu) . Regarding claim 41, Fig 3 of Liou in view of Li in view of Someya teaches the semiconductor device of claim 32. Liou in view of Li in view of Li in view of Someya is silent on a silicon oxynitride layer covering the AMR stack (magnetoresistive material layer 2000, [0039]). However, Liou shows a passivation layer covering the AMR stack in Fig. 3. One of ordinary skill in the art would select a material that is known to be used as a passivation layer in magnetoresistive devices. Wu teaches a magnetoresistive device in which the passivation layer (330, [0057]) is formed of silicon oxynitride [0057]. Conclusion 07-39 AIA THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SAMMANTHA K SALAZ/Examiner, Art Unit 2892 /ERIC W JONES/Primary Examiner, Art Unit 2892 Application/Control Number: 18/147,396 Page 2 Art Unit: 2892 Application/Control Number: 18/147,396 Page 3 Art Unit: 2892 Application/Control Number: 18/147,396 Page 4 Art Unit: 2892 Application/Control Number: 18/147,396 Page 5 Art Unit: 2892 Application/Control Number: 18/147,396 Page 6 Art Unit: 2892 Application/Control Number: 18/147,396 Page 7 Art Unit: 2892 Application/Control Number: 18/147,396 Page 8 Art Unit: 2892 Application/Control Number: 18/147,396 Page 10 Art Unit: 2892 Application/Control Number: 18/147,396 Page 11 Art Unit: 2892 Application/Control Number: 18/147,396 Page 12 Art Unit: 2892 Application/Control Number: 18/147,396 Page 13 Art Unit: 2892 Application/Control Number: 18/147,396 Page 14 Art Unit: 2892 Application/Control Number: 18/147,396 Page 15 Art Unit: 2892
Prosecution Insights