Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see section titled “Rejections under 35 U.S.C. 102 and 103,” filed 04/24/2026, with respect to the rejection(s) of claims 1-20 under 35 U.S.C. 102 and 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Agarwal et al. (US20210057352A1, hereinafter Agarwal) and Sankman et al. (US20190363046A1, hereinafter Sankman).
Regarding claim 1, Agarwal teaches an integrated circuit (IC) package comprising:
at least one dielectric layer (See below annotated fig. 13 molding layers 370 and 332);
a bridge die embedded in the at least one dielectric layer (See below annotated fig. 13 interconnect chip 373 embedded within molding layer 370);
first and second interconnects extending at least partially through the at least one dielectric layer, the first interconnect extending between the bridge die and a first side of the at least one dielectric layer (See below annotated fig. 13 first interconnect extending between interconnect chip 373 and bottom surface of molding layer 370), the second interconnect extending from the first side to a second side of the at least one dielectric layer (See below annotated fig. 13 conductive pillar 368a extending from a bottom to a top surface of molding layer 370); and
Agarwal does not appear to teach
a material on a sidewall of at least one of the first or second interconnects, the material including at least one of silicon or titanium.
Sankman teaches
a material on a sidewall of at least one of the first or second interconnects, the material including at least one of silicon or titanium (Fig. 2M protective layer 145 on a sidewall of pad 124 and par. 29 teaches that “the protective layer 145 may be silicon nitride”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Agarwal with the teachings of Sankman because “the protective layer 145 may prevent or mitigate the etching of the conductive material 170 from its side faces [during an etch], substantially preserving the “width” of the pads 124/lines 126” (Sankman par. 31).
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See below for full claims mapping.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Agarwal (US20210057352A1) in view of Sankman (US20190363046A1).
Regarding claim 1, Agarwal teaches an integrated circuit (IC) package comprising:
at least one dielectric layer (See above annotated fig. 13 molding layers 370 and 332);
a bridge die embedded in the at least one dielectric layer (See above annotated fig. 13 interconnect chip 373 embedded in molding layer 370);
first and second interconnects extending at least partially through the at least one dielectric layer, the first interconnect extending between the bridge die and a first side of the at least one dielectric layer (See above annotated fig. 13 first interconnect extending between interconnect chip 373 and bottom surface of molding layer 370), the second interconnect extending from the first side to a second side of the at least one dielectric layer (See above annotated fig. 13 conductive pillar 368a extending from a bottom to a top surface of molding layer 370); and
Agarwal does not appear to teach
a material on a sidewall of at least one of the first or second interconnects, the material including at least one of silicon or titanium.
Sankman teaches
a material on a sidewall of at least one of the first or second interconnects, the material including at least one of silicon or titanium (Fig. 2M protective layer 145 on a sidewall of pad 124 and par. 29 teaches that “the protective layer 145 may be silicon nitride”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Agarwal with the teachings of Sankman because “the protective layer 145 may prevent or mitigate the etching of the conductive material 170 from its side faces [during an etch], substantially preserving the ‘width’ of the pads 124/lines 126” (Sankman par. 31).
Regarding claim 2, the combination of Agarwal and Sankman teaches the IC package as defined in claim 1,
wherein the material covers at least a portion of an outer diameter of the at least one of the plurality of interconnects (Sankman fig. 2M protective layer 145 on sidewall of pad 124 covers portion of outer diameter of pad 124. As Sankman teaches the usage of protective layer 145 for etch protection they also teach how it is disposed in relation to an interconnect).
Regarding claim 3, the combination of Agarwal and Sankman teaches the IC package as defined in claim 2,
wherein a portion of the at least one of the plurality of interconnects not covered by the material includes an indent (Sankman fig. 2G undercuts 147 formed within pads 124 where protective layer 145 is not covering. As Sankman teaches the usage of protective layer 145 for etch protection they also teach how it is disposed in relation to an interconnect).
Regarding claim 4, the combination of Agarwal and Sankman teaches the IC package as defined in claim 1,
wherein the at least one of the plurality of interconnects is a pillar that is laterally surrounded by the material (Sankman fig. 2M pad 124 has a pillar shape and is laterally surrounded by protective layer 145. As Sankman teaches the usage of protective layer 145 for etch protection they also teach how it is disposed in relation to an interconnect).
Regarding claim 5, the combination of Agarwal and Sankman teaches the IC package as defined in claim 4,
wherein the material is surrounded by the at least one dielectric layer (Sankman fig. 2M dielectric layer 102-2 surrounds protective layer 145. As Sankman teaches the usage of protective layer 145 for etch protection they also teach how it is disposed in relation to an interconnect).
Regarding claim 6, the combination of Agarwal and Sankman teaches the IC package as defined in claim 1,
wherein the material includes silicon nitride (Sankman par. 29 teaches that “the protective layer 145 may be silicon nitride.” As Sankman teaches the usage of protective layer 145 for etch protection they also teach the material it comprises).
Regarding claim 7, the combination of Agarwal and Sankman teaches the IC package as defined in claim 1,
including first and second dies embedded in the at least one dielectric layer (Agarwal fig. 13 semiconductor chips 305/310 embedded in molding layer 332).
Regarding claim 8, the combination of Agarwal and Sankman teaches the IC package as defined in claim 7,
wherein the at least one of the first or second interconnects is a plated bump for the bridge die, the bridge electrically coupled to the first and second dies (See above annotated Agarwal fig. 13 first interconnect is a plated bump for the bridge die and the bridge die is electrically connected to semiconductor chips 305/310).
Regarding claim 9, Agarwal teaches a die chip comprising:
a die (Fig. 13 semiconductor chip 310);
a dielectric (Fig. 13 molding layers 370 and 332);
a first interconnect extending through at least a portion of the dielectric, the first interconnect electrically coupling the die to a bridge die surrounded by the dielectric (See above annotated fig. 13 first interconnect extending between interconnect chip 373 and bottom surface of molding layer 370 and electrically couples semiconductor chip 310 to interconnect chip 373);
a second interconnect extending through the dielectric at a location laterally adjacent to the bridge die (See above annotated fig. 13 conductive pillar 368a extending from a bottom to a top surface of molding layer 370).
Agarwal does not appear to teach
a material on a lateral side of at least one of the first interconnect or the second interconnect, the material including at least one of silicon or titanium.
Sankman teaches
a material on a lateral side of at least one of the first interconnect or the second interconnect, the material including at least one of silicon or titanium (Fig. 2M protective layer 145 on a sidewall of pad 124 and par. 29 teaches that “the protective layer 145 may be silicon nitride”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Agarwal with the teachings of Sankman because “the protective layer 145 may prevent or mitigate the etching of the conductive material 170 from its side faces [during an etch], substantially preserving the “width” of the pads 124/lines 126” (Sankman par. 31).
Regarding claim 10, the combination of Agarwal and Sankman teaches the die chip as defined in claim 9,
wherein the die is a first die, and further including the die chip includes a second die (Agarwal fig. 13 semiconductor chip 310 is a first die and semiconductor chip 305 is a second die).
Regarding claim 11, the combination of Agarwal and Sankman teaches the die chip as defined in claim 10,
wherein the bridge die is electrically coupled to the first die and the second die (Agarwal fig. 13 interconnect chip 373 electrically couples semiconductor chips 305/310).
Regarding claim 12, the combination of Agarwal and Sankman teaches the die chip as defined in claim 11,
wherein the first interconnect extends between at least one of the first or second dies and the bridge die (See above annotated Agarwal fig. 13 first interconnect extends between semiconductor chip 310 and interconnect chip 373).
Regarding claim 13, the combination of Agarwal and Sankman teaches the die chip as defined in claim 10,
wherein the first die and the second die are carried by a carrier (Agarwal fig. 21 semiconductor chips 305 and 310 are carried by carrier wafer 380).
Regarding claim 14, Agarwal teaches a method comprising:
providing bridge pillars on a dielectric substrate (See above annotated fig. 13 first interconnect extending between interconnect chip 373 and bottom surface of molding layer 370 and electrically couples semiconductor chip 310 to interconnect chip 373);
providing core pillars on the dielectric substrate, the core pillars larger than the bridge pillars, the bridge pillars between different ones of the core pillars (See above annotated fig. 13 conductive pillar 368a extending from a bottom to a top surface of molding layer 370. Conductive pillars 368 are larger and different than the first interconnect);
performing an etch process proximate to or on the at least one of the bridge pillars or the core pillars (Par. 57 teaches that “[p]ortions of the plating seed layer 381 lateral to the pillars 368 a and 368 b are etched away”).
Agarwal does not appear to teach
applying a material to at least partially cover at least one of the bridge pillars or the core pillars, the material including at least one of silicon or titanium.
Sankman teaches
applying a material to at least partially cover at least one of the bridge pillars or the core pillars, the material including at least one of silicon or titanium (Fig. 2M protective layer 145 on a sidewall of pad 124 and par. 29 teaches that “the protective layer 145 may be silicon nitride”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Agarwal with the teachings of Sankman because “the protective layer 145 may prevent or mitigate the etching of the conductive material 170 from its side faces [during an etch], substantially preserving the “width” of the pads 124/lines 126” (Sankman par. 31).
Regarding claim 15, the combination of Agarwal and Sankman teaches the method as defined in claim 14,
wherein the dielectric substrate is a first dielectric substrate, and the method includes placing a second dielectric substrate onto the first dielectric substrate such that at least a portion of the material is between the at least one of the bridge pillars or the core pillars and the second dielectric substrate (Agarwal fig. 13 teaches additional molding layer 332 disposed on molding layer 370. First interconnect, see above annotated Agarwal fig. 13, is disposed between molding layers 332/370. Therefore, the teachings of Sankman, which involve the introduction of an etch stop layer for protecting interconnects, would mean that at least a portion of Sankman’s SiN layer would be disposed between the first interconnect and molding layer 332).
Regarding claim 16, the combination of Agarwal and Sankman teaches the method as defined in claim 14,
wherein the performing of the etch process includes performing a seed layer etch of a seed layer adjacent or proximate to the dielectric substrate (Agarwal par. 57 teaches that “[p]ortions of the plating seed layer 381 lateral to the pillars 368 a and 368 b are etched away” which is proximate to molding layer 370).
Regarding claim 20, the combination of Agarwal and Sankman teaches the method as defined in claim 14, including
etching a photoresist to define a gap at least partially surrounding the at least one of the bridge pillars or the core pillars, and
wherein the material is applied into the gap (Sankman par. 26 “[t]he photoresist 114 may be patterned using any suitable lithographic technique [e.g., exposing the photoresist 114 with a mask to change the solubility of different portions of the photoresist 114 and then etching away the more soluble portions, as known in the art]” and so Sankman discloses etching photoresist 114 to form spaces surrounding conductive material 170 in which protective layer 145 is deposited. As Sankman teaches the usage of protective layer 145 for etch protection they also teach how to produce the layer).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Agarwal (US20210057352A1) and Sankman (US20190363046A1) as applied to claim 14 above, and further in view of Nie et al. (US20200312771A1, hereinafter Nie).
Regarding claim 18, the combination of Agarwal and Sankman teaches the method as defined in claim 14.
The combination of Agarwal and Sankman does not appear to teach
including embedding known good dies (KGDs) in the dielectric substrate.
Nie teaches
Including embedding known good dies (KGDs) in the dielectric substrate (Par. 23 “dies need to be tested before embedding for significant cost savings, and only known good dies (KGDs) are allowed to continue in the process flow to the end of line for production”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Agarwal and Sankman with the teachings of Nie because the usage of tested and known good dies provides “significant cost savings” (Nie par. 23).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Agarwal (US20210057352A1) and Sankman (US20190363046A1) as applied to claim 14 above, and further in view of Aoki et al. (US20160322319A1, hereinafter Aoki).
Regarding claim 19, the combination of Agarwal and Sankman teaches the method as defined in claim 14.
The combination of Agarwal and Sankman does not appear to teach
including applying a thermal treatment to a photoresist to define a gap at least partially surrounding the at least one of the bridge pillars or the core pillars, and
wherein the material is applied into the gap.
Aoki teaches
including applying a thermal treatment to a photoresist to define a gap at least partially surrounding the at least one of the bridge pillars or the core pillars (Figs. 7/8, par. 39 “[t]he space 30 is generated due to the heated resist being shrunk”), and
wherein the material is applied into the gap (Fig. 9 metal barrier layer 32 deposited into spaces 30).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Agarwal and Sankman with the teachings of Aoki because as both the combination of Agarwal and Sankman and Aoki teach a suitable method for depositing a material on a conductive pillar, it would have been obvious to substitute Sankman’s blanket deposition and seed etch with Aoki’s heat shrink of a resist and deposition to achieve the predictable result of using a resist which shrinks upon heating to form a gap in a resist surrounding a conductive pillar and deposit a material in said gap.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Agarwal (US20210057352A1) and Sankman (US20190363046A1) as applied to claim 1 above, and further in view of Amanapu et al. (US20190198444A1, hereinafter Amanapu).
Regarding claim 21, the combination of Agarwal and Sankman teaches the IC package as defined in claim 1.
The combination of Agarwal and Sankman do not appear to teach
wherein the material includes titanium.
Amanapu teaches
wherein the material includes titanium (Par. 41 “[t]he etch protection layer 145 can be formed of a material such as Ta, TaN, Ti, TiN, silicon oxide (e.g., SiO2), silicon nitride (SiN)).”
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Agarwal and Sankman with the teachings of Amanapu because as both the combination of Agarwal and Sankman and Amanapu teach suitable materials for use as an etch stop layer, it would have been obvious to substitute the combination of Agarwal and Sankman’s SiN etch stop layer with Amanapu’s Ti etch stop layer to achieve the predictable result of forming an etch stop layer formed from Ti.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE LEON LINDSEY whose telephone number is (571)272-4028. The examiner can normally be reached Monday - Friday, 8:00 a.m. - 5:00 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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