Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 9-17, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sankman et al. (US20190363046A1, hereinafter Sankman).
Regarding claim 1, Sankman discloses an integrated circuit (IC) package comprising:
at least one dielectric layer (Fig. 2M dielectric materials 102-1/102-2);
an interconnect extending at least partially through or from the at least one dielectric layer (Fig. 2M pad. 124 is connected to another interconnect within dielectric material 102-1 as taught by par. 24 “the layer of dielectric material 102-1 may have conductive features (e.g., vias, lines, or pads) therein”); and
a material on at least a portion of a sidewall of the interconnect, wherein the material comprises at least one of silicon or titanium (Fig. 2M protective layer 145 on a sidewall of pad 124 and par. 29 teaches that “the protective layer 145 may be silicon nitride”).
Regarding claim 2, Sankman discloses the IC package as defined in claim 1,
wherein the material covers at least a portion of an outer diameter of the interconnect (Fig. 2M protective layer 145 on sidewall of pad 124 covers portion of outer diameter of pad 124).
Regarding claim 3, Sankman discloses the IC package as defined in claim 2,
wherein a portion of the interconnect not covered by the material includes an indent (Fig. 2G undercuts 147 formed within pads 124 where protective layer 145 is not covering).
Regarding claim 4, Sankman discloses the IC package as defined in claim 1,
wherein the interconnect is a pillar that is laterally surrounded by the material (Fig. 2M pad 124 has a pillar shape and is laterally surrounded by protective layer 145).
Regarding claim 5, Sankman discloses the IC package as defined in claim 4,
wherein the material is surrounded by the at least one dielectric layer (Fig. 2M dielectric layer 102-2 surrounds protective layer 145).
Regarding claim 6, Sankman discloses the IC package as defined in claim 1,
wherein the material comprises silicon nitride (Par. 29 teaches that “the protective layer 145 may be silicon nitride”).
Regarding claim 9, Sankman discloses a die chip comprising:
a die (Fig. 9 left die 1656);
a dielectric (Fig. 9 mold compound 1668);
an interconnect extending through at least a portion of the dielectric, the interconnect electrically coupled to the die (Fig. 9 interconnects 1658 extends through mold compound 1668 and is electrically coupled to left die 1656); and
a material on at least a portion of a lateral side of the interconnect (Fig. 2M protective layer 145 on a sidewall of pad 124 and par. 49 teaches that “FIGS. 7-11 illustrate various examples of apparatuses that may include any of the IC package supports 100 disclosed herein”), the material including at least one of silicon or titanium (Par. 29 teaches that “the protective layer 145 may be silicon nitride”).
Regarding claim 10, Sankman discloses the die chip as defined in claim 9,
wherein the die is a first die, and further including a second die (Fig. 9 right die 1656 is a second die).
Regarding claim 11, Sankman discloses the die chip as defined in claim 10, further including
a bridge die that is electrically coupled to the first die and the second die (Fig. 9 interposer 1657 is an electrical bridge that couples left die and right dies 1656).
Regarding claim 12, Sankman discloses the die chip as defined in claim 11,
wherein the interconnect extends between at least one of the first or second dies and the bridge die (Fig. 9 interconnects 1658 extend between left die 1656 and interposer 1657).
Regarding claim 13, Sankman discloses the die chip as defined in claim 10,
wherein the first die and the second die are carried by a carrier (Fig. 9 left and right dies 1656 are both disposed on package substrate 1652).
Regarding claim 14, Sankman discloses a method comprising:
defining an interconnect onto a dielectric substrate (Fig. 2D conductive material 170 on dielectric materials 102-1);
applying a material to at least partially cover at least a sidewall of the interconnect (Figs. 2E-2F protective layer 145 covers at least partially covers at least a sidewall of conductive material 170), wherein the material comprises at least one of silicon or titanium (Par. 29 teaches that “the protective layer 145 may be silicon nitride”); and
performing an etch process proximate or on the interconnect (Par. 31, fig. 2G “illustrates an assembly 212 subsequent to performing a seed etch to remove the exposed seed layer 120 from the assembly 210”).
Regarding claim 15, Sankman discloses the method as defined in claim 14,
wherein the dielectric substrate is a first dielectric substrate (Fig. 2M dielectric material 102-1 is a first dielectric substrate), and further including placing a second dielectric substrate onto the first dielectric substrate such that at least a portion of the material is positioned between the interconnect and the second dielectric substrate (Fig. 2M dielectric material 102-2 is a second dielectric substrate where protective layer 145 is between first and second dielectric materials 102-1/102-2).
Regarding claim 16, Sankman discloses the method as defined in claim 14,
wherein the performing the etch process includes performing a seed layer etch of a seed layer adjacent or proximate to the dielectric substrate (Par. 31, fig. 2G “illustrates an assembly 212 subsequent to performing a seed etch to remove the exposed seed layer 120 from the assembly 210”).
Regarding claim 17, Sankman discloses the method as defined in claim 14,
wherein the interconnect is a first interconnect (Figs 2M/3F lowermost pad 124 as shown in fig. 2M is a first interconnect), and further including
coupling a second interconnect between the die and a bridge die (Fig. 3F shows a second layer of interconnect pads 124 disposed on the first interconnect below and par. 49 teaches that “FIGS. 7-11 illustrate various examples of apparatuses that may include any of the IC package supports 100 disclosed herein”).
Regarding claim 20, Sankman discloses the method as defined in claim 14, further including
etching a photoresist to define a gap at least partially surrounding the interconnect, and
wherein the material is applied into the gap (Par. 26 “[t]he photoresist 114 may be patterned using any suitable lithographic technique [e.g., exposing the photoresist 114 with a mask to change the solubility of different portions of the photoresist 114 and then etching away the more soluble portions, as known in the art]” and so Sankman discloses etching photoresist 114 to form spaces surrounding conductive material 170 in which protective layer 145 is deposited).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Sankman (US20190363046A1).
Regarding claim 7, Sankman teaches the IC package as defined in claim 1, further including
first and second dies embedded in the at least one dielectric layer (Fig. 10 IC package 1720 and par. 76 teaches that “multiple IC packages may be coupled to the package interposer 1704” and so Sankman teaches multiple IC packages coupled to interposer 1704. While Sankman does not explicitly disclose these IC packages embedded within dielectric layers 102-1/102-2, the primary function of the IC packages is to be coupled to interposer 1704. A rearrangement of the IC packages to be embedded within dielectric layers 102-1/102-2 would not provide any new or unexpected results as the primary function of the IC packages coupling to interposer 1704 is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore rearrange the IC packages to be embedded within dielectric layers 102-1/102-2, see MPEP 2144.04(VI)(B)).
Regarding claim 8, Sankman teaches the IC package as defined in claim 7,
wherein the interconnect is a plated bump for a die bridge that is electrically coupled to the first and second dies (Fig. 10 coupling components 1718 between IC package 1720 and a second IC package as taught above in the rejection of claim 7. Additionally, par. 49 teaches that “FIGS. 7-11 illustrate various examples of apparatuses that may include any of the IC package supports 100 disclosed herein” and so Sankman teaches that an interconnect as taught in fig. 2M used as an interconnect between a bridging interposer 1704 and an IC package 1720/a second IC package as taught above in the rejection of claim 7).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Sankman in view of Nie et al. (US20200312771A1, hereinafter Nie).
Regarding claim 18, Sankman teaches the method as defined in claim 14.
Sankman does not appear to teach
embedding known good dies (KGDs) in the dielectric substrate.
Nie teaches
embedding known good dies (KGDs) in the dielectric substrate (Par. 23 “dies need to be tested before embedding for significant cost savings, and only known good dies (KGDs) are allowed to continue in the process flow to the end of line for production”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sankman with the teachings of Nie because the usage of tested and known good dies provides “significant cost savings” (Nie par. 23).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Sankman in view of Aoki et al. (US20160322319A1, hereinafter Aoki).
Regarding claim 19, Sankman teaches the method as defined in claim 14.
Sankman does not appear to teach
applying a thermal treatment to a photoresist to define a gap at least partially surrounding the interconnect, and
wherein the material is applied into the gap.
Aoki teaches
applying a thermal treatment to a photoresist to define a gap at least partially surrounding the interconnect (Figs. 7/8, par. 39 “[t]he space 30 is generated due to the heated resist being shrunk”)
wherein the material is applied into the gap (Fig. 9 metal barrier layer 32 deposited into spaces 30).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sankman with the teachings of Aoki because as both Sankman and Aoki teach a suitable method for depositing a material on a conductive pillar, it would have been obvious to substitute Sankman’s blanket deposition and seed etch with Aoki’s heat shrink of a resist and deposition to achieve the predictable result of using a resist which shrinks upon heating to form a gap in a resist surrounding a conductive pillar and deposit a material in said gap.
Conclusion
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/COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812