DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 8 and 10-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Watanabe et al. (U.S. Publication No. 2021/0343911).
Regarding claim 1, Watanabe teaches an integrated circuit (IC) package comprising:
a dielectric substrate (Fig. 12B, substrate 11);
an interconnect (interconnect 14) associated with the dielectric substrate (Fig. 12B); and
light absorption material (11L) proximate or surrounding the interconnect (Fig. 12B), the light absorption material to increase in temperature in response to being exposed to a pulsed light for thermal treatment corresponding to the IC package (paragraph [0088]).
Regarding claim 2, Watanabe teaches the IC package as defined in claim 1, wherein the exposure of the light absorption material to the pulsed light is to at least partially reflow the interconnect (paragraph [0088]).
Regarding claim 3, Watanabe teaches the IC package as defined in claim 1, wherein the dielectric substrate includes or is adjacent a layer having the light absorption material (layer 11L is a part of the whole substrate made up of 11/11W/11L/11Z).
Regarding claim 4, Watanabe teaches the IC package as defined in claim 3, wherein the light absorption material is a layer on or within the dielectric (see Fig. 12B).
Regarding claim 5, Watanabe teaches the IC package as defined in claim 4, wherein the layer extends across multiple interconnects and the thermal treatment corresponds to reflow of the interconnects (Fig. 12B, multiple interconnects 14).
Regarding claim 8, Watanabe teaches the IC package as defined in claim 1, wherein the dielectric substrate is a first dielectric substrate and the light absorption material is positioned between the first dielectric substrate and a second dielectric substrate (see Fig. 13B, second substrate 12P where 11L is between 11 and 12P).
Regarding claim 10, Watanabe teaches an apparatus comprising:
a die (Fig. 13A, die package 12P);
a dielectric (11Z);
an interconnect (14) extending through at least a portion of the dielectric, the interconnect electrically coupled to the die (Fig. 13A); and
a light absorption layer (11L), the light absorption layer having a light absorption material to increase in temperature in response to being exposed to a pulsed light for at least one of reflow of the interconnect or curing corresponding to the die chip (paragraph [0088]).
Regarding claim 11, Watanabe teaches the apparatus as defined in claim 10, wherein the die is a first die, and further the apparatus including a second die (12G, 12R and 12B are all separate dies, see paragraph [0046], each is an LED chip).
Regarding claim 12, Watanabe teaches the apparatus as defined in claim 10, wherein the light absorption layer is positioned at or proximate a solder bump for reflow thereof (solder 15, see paragraph [0088]).
Regarding claim 13, Watanabe teaches the apparatus as defined in claim 10, wherein the die is an embedded die (embedded in the package 12P).
Regarding claim 14, Watanabe teaches the apparatus as defined in claim 10, wherein the curing corresponds to curing the dielectric (curing claimed in alternative to reflow and therefore not needed).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Watanabe in view of Gavagnin et al. (WO 2024/068295).
Regarding claim 6, Watanabe teaches the IC package as defined in claim 1, but does not teach further including a die embedded in the dielectric substrate.
However, Gavagnin teaches another package in which the substrate for an LED chip (Gavagnin Fig. 1, LED 108 on substrate 100) has an embedded die (120). It would have been obvious to a person of skill in the art at the time of the effective filing date that the substrate could have had an embedded die because this is a common method of building ultra-fine connections within a substrate to connect dies to one another.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Watanabe in view of Chen et al. (U.S. Publication No. 2025/0022991).
Regarding claim 7, Watanabe teaches the IC package as defined in claim 1, but does not teach wherein the dielectric substrate includes or defines an optical coupler mounting.
however, Chen teaches that a substrate can include an optical coupler (Chen Fig. 1, optical coupler 112). It would have been obvious to a person of skill in the art at the time of the effective filing date that an optical coupler could have been integrated into the substrate because this allows for transmission of optical signals to a photonic die (Chen paragraph [0011]).
Allowable Subject Matter
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 9, the prior art, alone or in combination, fails to teach or suggest wherein the light absorption material is at a sawtooth interface between the first and second dielectrics.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Evan G Clinton whose telephone number is (571)270-0525. The examiner can normally be reached Monday-Friday at 8:30am to 5:30pm.
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/EVAN G CLINTON/Primary Examiner, Art Unit 2899
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