DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-7 and 10-12 in the reply filed on 04/13/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/17/2026 and 03/17/2023 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
A broad range or limitation together with a narrow range or limitation that falls within the broad range or limitation (in the same claim) may be considered indefinite if the resulting claim does not clearly set forth the metes and bounds of the patent protection desired. See MPEP § 2173.05(c). In the present instance, claim 1 recites the broad recitation "the third layer corresponding to electrodes of the thin film capacitor," and the claim also recites "the third layer defining a dielectric of the thin film capacitor" which is the narrower statement of the range/limitation. The claim(s) are considered indefinite because there is a question or doubt as to whether the feature introduced by such narrower language is (a) merely exemplary of the remainder of the claim, and therefore not required, or (b) a required feature of the claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, and 4 are rejected under U.S.C. 103 as being unpatentable over Chuang; US 2023/0402502 A1; 06/2022 in view of Marek et al.; US 2022/0190802 A1; 12/2021
Claim 1: Chuang discloses an apparatus comprising: a first layer ( Fig. 4B: conductive landing pad s 401); and a thin film capacitor including: a second layer ( Fig. 4B: first dielectric layer 402 ) on the first layer ( Fig. 4B #401 ), the second layer ( Fig. 4B #402 ) defining a plurality of openings ( Fig. 4B: trenches 403); a third layer ( Fig. 4D: bottom electrode layer 404 ) on the first layer ( Fig. 4A #401 ) and in the plurality of openings ( Fig. 4B #403 ), the second layer ( Fig. 4D #402 ) and the third layer ( Fig. 4D #404 ) corresponding to electrodes of the thin film capacitor ( as discussed above ); and a fourth layer ( Fig. 4D: first capacitor dielectric layer 405a ) disposed between the first layer ( Fig. 4D #401 ) and the second layer ( Fig. 4D #402 ),
Chuang does not appear to disclose the third layer including an oxidized material, the third layer defining a dielectric of the thin film capacitor.
However, Marek teaches the third layer ( Fig. 2B third layer 259 ) including an oxidized material ( [0031] For example, the substrate(s) and/or dielectric layers may comprise one or more suitable ceramic materials. Suitable materials are generally electrically insulating and thermally conductive. For example, in some embodiments, the substrate may include sapphire, ruby, alumina (Al.sub.2O.sub.3), aluminum nitride (AlN), beryllium oxide (BeO), aluminum oxide (Al.sub.2O.sub.3), boron nitride (BN), silicon (Si), silicon carbide (SiC), silica (SiO.sub.2), silicon nitride (Si.sub.3N.sub.4), gallium arsenide (GaAs), gallium nitride (GaN), zirconium dioxide (ZrO.sub.2), mixtures thereof, oxides and/or nitrides of such materials, or any other suitable ceramic material. Additional example ceramic materials include barium titanate (BaTiO.sub.3), calcium titanate (CaTiO.sub.3), zinc oxide (ZnO), ceramics containing low-fire glass, or other glass-bonded materials ), the third layer ( Fig. 2B #259 ) defining a dielectric of the thin film capacitor ( [0054] A third layer 259 (e.g., of dielectric material) can be arranged over the monolithic substrate 206 and the third patterned conductive layer 258 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Marek with Chuang to implement the third layer including an oxidized material, the third layer defining a dielectric of the thin film capacitor because this layer typically provides both electrical and structural roles by providing insulation, high capacitance and enabling self-healing while also defining the geometry for subsequent layers.
Claim 2: Chuang and Marek disclose the apparatus of claim 1 ( as discussed above).
Chuang does not appear to disclose the oxidized material is aluminum oxide.
However, Marek teaches the oxidized material is aluminum oxide ( [0031] For example, the substrate(s) and/or dielectric layers may comprise one or more suitable ceramic materials. Suitable materials are generally electrically insulating and thermally conductive. For example, in some embodiments, the substrate may include sapphire, ruby, alumina (Al.sub.2O.sub.3), aluminum nitride (AlN), beryllium oxide (BeO), aluminum oxide (Al.sub.2O.sub.3), boron nitride (BN), silicon (Si), silicon carbide (SiC), silica (SiO.sub.2), silicon nitride (Si.sub.3N.sub.4), gallium arsenide (GaAs), gallium nitride (GaN), zirconium dioxide (ZrO.sub.2), mixtures thereof, oxides and/or nitrides of such materials, or any other suitable ceramic material. Additional example ceramic materials include barium titanate (BaTiO.sub.3), calcium titanate (CaTiO.sub.3), zinc oxide (ZnO), ceramics containing low-fire glass, or other glass-bonded materials ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Marek with Chuang to implement the oxidized material is aluminum oxide because this material is an excellent dielectric, it provides a thin and uniform insulating layer, and is naturally formed through anodization of aluminum.
Claim 4: Chuang and Marek disclose the apparatus of claim 1 ( as discussed above).
Chuang teaches the plurality of openings ( Fig. 4B #403 ) includes a first trench ( Fig. 4B left most trench ) and a second trench ( Fig. 4B middle trench ) , the first trench has a first width ( as shown in Fig. 4B ), the second trench has a second width ( as shown in Fig. 4B ), the first width substantially equal to the second width ( width of both trenches are the same as shown in Fig. 4B ).
Claim 3 is rejected under U.S.C. 103 as being unpatentable over Chuang; US 2023/0402502 A1; 06/2022 in view of Marek et al.; US 2022/0190802 A1; 12/2021 as it relates to claim 1 above and further in view of Meng et al.; US 2022/0376120 A1; 05/2022
Claim 3: Chuang and Marek disclose the apparatus of claim 1 ( as discussed above).
Neither Chuang nor Marek appear to disclose the second layer includes aluminum.
However, Meng teaches the second layer includes aluminum ( [0012] In certain embodiments, the dielectric stack layer further comprises a second layer deposited on the first layer, wherein the second layer comprises aluminum oxide (Al.sub.2O.sub.3) grown on the first layer ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Meng with Chuang and Marek to implement the second layer includes aluminum because this material is resistant to environmental corrosion in DC film capacitors.
Claims 5 and 12 are rejected under U.S.C. 103 as being unpatentable over Chuang; US 2023/0402502 A1; 06/2022 in view of Marek et al.; US 2022/0190802 A1; 12/2021 as it relates to claim 1 above and further in view of Oyamada; US 2020/0126934 A1; 05/2017
Claim 5: Chuang and Marek disclose the apparatus of claim 1 ( as discussed above).
Neither Chuang nor Marek appear to disclose the plurality of openings is arranged in a grid.
However, Oyamada teaches the plurality of openings is arranged in a grid ( Fig. 4 dielectric openings 12A ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Oyamada with Chuang and Marek to implement the plurality of openings is arranged in a grid because this approach reduces thermal and mechanical stresses that maximizes both reliability and performance.
Claim 12: Chuang and Marek disclose the apparatus of claim 1 ( as discussed above).
Neither Chuang nor Marek appear to disclose a first one of the plurality of openings is a first square having a first width, a second one of the plurality of openings is a second square having a second width, the first width substantially equal to the second width.
However, Oyamada teaches a first one of the plurality of openings is a first square having a first width ( Fig. 4 dielectric openings 12A select the one on the top left side ), a second one of the plurality of openings is a second square having a second width ( Fig. 4 #12A select the one on the bottom right side ), the first width substantially equal to the second width ( as shown in Fig. 4 the widths are the same for the first and second opening).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Oyamada with Chuang and Marek to implement a first one of the plurality of openings is a first square having a first width, a second one of the plurality of openings is a second square having a second width, the first width substantially equal to the second width because this design choice helps to ensure consistent capacitance, reliability, and manufacturability.
Claim 6 is rejected under U.S.C. 103 as being unpatentable over Chuang; US 2023/0402502 A1; 06/2022 in view of Marek et al.; US 2022/0190802 A1; 12/2021 as it relates to claim 1 above and further in view of Hanbuecken et al.; US 9,165722 B2; 05/2013
Claim 6: Chuang and Marek disclose the apparatus of claim 1 ( as discussed above).
Neither Chuang nor Marek appear to disclose the plurality of openings include a plurality of irregular pores.
However, Hanbuecken teaches the plurality of openings include a plurality of irregular pores ( Col. 4 lines 20-24 The pitch P separating two pores 101 of the organized array may lie between 10 nm and 1 μm. The pores 101 may have a diameter of between 5 nm and 500 nm, whether they are arranged in an organized array or not ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Hanbuecken with Chuang and Marek to implement the plurality of openings include a plurality of irregular pores because the deposition could have non-uniformities along with mechanical stresses and intrinsic dielectric material heterogeneity.
Claim 7 is rejected under U.S.C. 103 as being unpatentable over Chuang; US 2023/0402502 A1; 06/2022 in view of Marek et al.; US 2022/0190802 A1; 12/2021 as it relates to claim 1 above and further in view of Tolar et al.; US 3,969,197; 02/1974
Claim 7: Chuang and Marek disclose the apparatus of claim 1 ( as discussed above).
Neither Chuang nor Marek appear to disclose the apparatus is an integrated circuit package.
However, Tolar teaches the apparatus is an integrated circuit package ( Col. 8 lines 31-37 Although the technology set forth herein has been described particularly in its connection with fabrication of thin film capacitor structures, it should also be borne in mind that similar technology may be effectively applied to gate insulation of MOS integrated circuits and may be utilized to fabricate thin film capacitors on bipolar integrated circuits ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Tolar with Chuang and Marek to implement the apparatus is an integrated circuit package because integrating a thin film capacitor into an IC is beneficial to enhance power integrity, reduce noise, and optimize high-frequency performance.
Claim 10 is rejected under U.S.C. 103 as being unpatentable over Chuang; US 2023/0402502 A1; 06/2022 in view of Marek et al.; US 2022/0190802 A1; 12/2021 as it relates to claim 1 above and further in view of Zhang et al.; US 2023/0197351 A1; 12/2021
Claim 10: Chuang and Marek disclose the apparatus of claim 1 ( as discussed above).
Neither Chuang nor Marek appear to disclose the second layer includes copper.
However, Zhang teaches the second layer includes copper ( [0028] In embodiments, the first metal layer 112 is electrically isolated from the second metal layer 116. In embodiments, the first metal layer 112 and the second metal layer 116 may include copper ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Tolar with Chuang and Marek to implement the second layer includes copper because this selection maximizes electrical conductivity and compatibility with the dielectric layer.
Claim 11 is rejected under U.S.C. 103 as being unpatentable over Chuang; US 2023/0402502 A1; 06/2022 in view of Marek et al.; US 2022/0190802 A1; 12/2021 as it relates to claim 1 above and further in view of Harada et al.; US 2025/0120104 A1; 12/2022
Claim 11: Chuang and Marek disclose the apparatus of claim 1 ( as discussed above).
Neither Chuang nor Marek appear to disclose including a fourth layer adjacent the second layer, the second and fourth layers collectively corresponding to a first one of the electrodes, the second layer including a first material and a fourth layer including a second material different than the first material.
However, Harada teaches including a fourth layer ( Fig. 1A an electrode layer 31 ) adjacent the second layer ( Fig. 1A insulating member 21), the second and fourth layers collectively corresponding to a first one of the electrodes ( as shown in Fig. 1A ), the second layer ( Fig. 1A #21 ) including a first material ( [0026] The insulating members 21 and 22 are made of, e.g., a resin material ) and a fourth layer ( Fig. 1A #31 ) including a second material ( [0026] The electrode layer 31 is made of, e.g., a metal material such as copper, nickel, gold, or an alloy material thereof ) different than the first material ( as discussed above resin is different than metal materials ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Harada with Chuang and Marek to implement including a fourth layer adjacent the second layer, the second and fourth layers collectively corresponding to a first one of the electrodes, the second layer including a first material and a fourth layer including a second material different than the first material because a multilayer approach balances energy density with mechanical and electrical resilience.
Conclusion
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/K.N.F./Examiner, Art Unit 2817
/ALI NARAGHI/Primary Examiner, Art Unit 2817
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