DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-14 in the reply filed on 02/25/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a gate structure disposed proximate the first GAA FET and the second GAA FET…” Claim 14 recites “the third material is substantially the same as the first material…”
The term "proximate" is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. “Proximate” is defined as " very near : close” (see Merriam Webster online dictionary). This language is indefinite as the specification does not describe how close something needs to be to be “proximate” to something.
The term “proximate” modifies a target, and implicitly requires boundaries at some maximum value above the target and at some minimum value below the target beyond which one is not “substantially” the target any more. Neither the claims, nor the specification, defines these boundaries. Thus, it is unclear whether one must be within some small percentage of deviation of the target (such as 0.01 %, 0.1 %, 1 %, 2 %, 5 %, 10 %, or some other percentage) or within a certain number of units of the target (in this case, the target is distance, and possible values of meters), and specifically which of these possible values defines the boundaries. If one were to poll 100 people having ordinary skill in the art, there would be many different responses for the boundaries. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear. Similar arguments are made for the term “substantially” in claim 14.
Therefore, claims 1 and 14 is rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention, and claims 2-13 are rejected for at least their deficiencies.
For the purposes of Examination, any distance will be interpreted to fall within the scope of “proximate,” and any materials will be interpreted as being “substantially” the same.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8 and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiang et al. (US 20220254623 A1, hereinafter Chiang)
With regards to claim 1, Chiang discloses a semiconductor device (FIGS. 8- 21) comprising:
a first Gate-All-Around (GAA) field-effect transistor (FET) (N type FET, see FIG. 21) disposed on a silicon layer; (silicon substrate 202, see paragraph [0018])
a second GAA FET (P type FET, see FIG. 21) disposed on the silicon layer adjacent to the first GAA FET;
an isolation layer (isolation feature 222) disposed within the silicon layer between a first bottom dielectric isolation (BDI) layer (left blocking layer 208) of the first GAA FET and a second BDI layer (right blocking layer 208) of the second GAA FET; and
a gate structure (at least gate electrode 228/264) disposed proximate the first GAA FET and the second GAA FET, wherein at least one of a cap or a sidewall spacer (at least dielectric 226/262) isolates the gate structure from the silicon layer. (See FIGS. 8 and 21)
With regards to claim 2, Chiang discloses the semiconductor device of claim 1, wherein the cap or the sidewall spacer is disposed vertically between the isolation layer and at least one of the first BDI layer or the second BDI layer. (see FIG. 21, showing the vertical disposition between layers 208)
With regards to claim 3, Chiang discloses the semiconductor device of claim 2, wherein the at least one of the cap or the sidewall spacer includes a nitride-based dielectric material. (Paragraph [0041]: “the gate dielectric layer 262 includes one or more layers of a dielectric material, such as silicon oxide, silicon nitride…”)
With regards to claim 4, Chiang discloses the semiconductor device of claim 2, wherein the gate structure is isolated from the silicon layer by the cap. (See FIG. 21, showing the isolation)
With regards to claim 5, Chiang discloses the semiconductor device of claim 2, wherein the gate structure is at least partially isolated from the silicon layer by the sidewall spacer. (See FIG. 21, showing the at least partial separation of layers 216 of the gate by the dielectric 262)
With regards to claim 6, Chiang discloses the semiconductor device of claim 4, wherein the cap is in direct contact with an oxide layer. (SiO inner spacer 238, see Paragraph [0033]. See also FIGS. 8, 19B, and 21, showing the direct contact of 238 to 262)
With regards to claim 7, Chiang discloses the semiconductor device of claim 6, wherein the oxide layer is disposed vertically between the cap and the isolation layer. (See FIGS. 8, 19B, and 21, showing the vertical disposition of the spacers 238 between the dielectric 262 and the isolation feature 222)
With regards to claim 8, Chiang discloses the semiconductor device of claim 7, wherein the oxide layer is in contact with a nitride-based dielectric liner. (Paragraph [0041]: “the gate dielectric layer 262 includes one or more layers of a dielectric material, such as silicon oxide, silicon nitride…”)
With regards to claim 10, Chiang discloses the semiconductor device of claim 9, wherein the cap is…of Silicon nitride (SiN). (Paragraph [0041]: “the gate dielectric layer 262 includes one or more layers of a dielectric material, such as silicon oxide, silicon nitride…”)
It should be noted that the limitation “is formed via an anisotropic deposition” is being interpreted as a product by process, and will not be given patentable weight (See MPEP 2113 I.)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Xie et al. (US 20210217654 A1) – bottom dielectric 202 on a FET gate.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812