Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 15-21 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected claim grouping concerning a method of forming a patterned solder resist, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 05/29/2026
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
As a matter of claim interpretation – the instant claim uses “comprising” language and as such does not exclude unrecited elements (e.g. additional films/layers/components) or steps.
Claim(s) 1, 7, 9, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (US 20140069694 A1) and Kawano et al (US 20200343293 A1)
Regarding Claim 1, 7, 9, and 13, Cho discloses a circuit substrate and pattern formed thereon, wherein a first solder resist layer is formed on the pattern, then opened, then a plating layer is formed on the circuit pattern and a second solder resist layer formed atop the first solder resist layer (Abstract).
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As per Figure 6 and [0055]-[0062], a circuit comprises a substrate 110, a circuit pattern 120 formed thereon, a first solder resist 130 (solder resist or mask), and electroless plating layers 140-160, where these layers may be applied by ENEPIG plating – where layer 140 is Nickel, 150 is Palladium, and 160 is Gold ([0060]) (claim 7, claim 13). Above the plating layers is a second solder resist 230, which is used to cover the edge portion of the plating layers to protect them, as the edge portions are vulnerable ([0060]).
Cho does not teach a layer on the metal layer including silicon and nitrogen.
This limitation is met by Kawano.
Kawano teaches a semiconductor apparatus configured to decrease the occurrence of exfoliation between conducting layers and insulating layers (Abstract).
As per figure 2A, [0039]-[0040], and [0049]-[0053] adhesive layers 50 and 53 are used as bonding regions between conductive layers 31 and 33 and insulating layers 41 and 43, where the adhesive layers comprise nitrogen and silicon.
A person having ordinary skill in the art would have found it obvious to arrive at the claimed invention prior to the effective filing date by depositing the adhesive layer of Kawano atop the plating layers of Cho prior to depositing the second solder resist so as to improve adhesion between the layers and reduce the risk of delamination and damage to the plating layers.
Claim(s) 2-5 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (US 20140069694 A1) and Kawano et al (US 20200343293 A1) as applied to claim 1 and 9 above, and further in view of Yu et al (US 20180151453 A1).
Regarding Claims 2-5 and 10, Cho and Kawano teach the limitations of the claims as discussed above regarding claims 1 and 9 but do not teach an opening extending through the solder resist and adhesion promoter layers where the opening has a tapered cross-sectional shape and/or a width of the opening is smaller proximate the adhesive layer then at the first surface of the solder resist. Cho teaches an opening in the solder resist.
These limitations are met by Yu.
Yu teaches a semiconductor device and a method for forming a conductive post on a die, wherein a substrate 50 has a pad 52 and a dielectric layer 54 deposited thereatop. A seed layer 56 (metal layer or a combination of metal layers, such as a gold layer and/or nickel layer – see [0021]), and a photoresist 58 is deposited and processed to form an opening 60.
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The opening 60 has a trench with a tapered region (claim 10), wherein the opening has a first width at the first surface at the top of the resist, a second, narrower width at the raised portions of the layer 54 and 56 covering the pad (claim 4) and a third width to affect a taper at the trench onto a second surface at the base. This configuration is used to facilitate the filling of the trench with a metal filler to create a post/conductive structure, as such it extends to the metallic layer. An incorporation of this design feature into the assembly of Kawano and Cho would necessarily extend the trench from the top surface of the resist to a second surface of the adhesive layer of Kawano, through to the third surface of the plating layers of Cho to maintain conductive connection between the plating layers and the conductive post (claim 3). The opening of the trench of Yu includes a footer region having a flat portion and then a slope to the base of the tapered opening, where including an adhesive layer while maintaining the conductive opening would result in regions of the sidewall where a main region has a rate of change of zero (the flat portion) and a rate of change that is greater than zero (the sloped region leading to the base of the taper) (claim 6). None of the references require an undercut (claim 5)
A person having ordinary skill in the art would have found it obvious to arrive at the claimed invention prior to the effective filing date by using a trench configuration of resist, adhesive layer, and plating layers, - where the trench extends to the conductive plating layers - in the assembly of Kawano and Cho as taught by Yu to facilitate filling for a conductive element such as a post while protecting the resist layer from delaminating away from the metal plating layer.
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (US 20140069694 A1) and Kawano et al (US 20200343293 A1) as applied to claim 1 above, and further in view of Bhate et al (US20100314750 A1).
Regarding claim 8, Cho and Kawano teach the limitations of the claim as discussed above regarding claim 1.
Neither reference disclose a particular roughness of a solder resist used.
This limitation is met by Bhate.
Bhate teaches an IC package comprising a substrate, and insulating material, and a mark on the material (abstract).
In one embodiment the solder resist material used as the electrically insulating material has a first surface roughness and a mark having a surface roughness orders of magnitude higher than the rest of the resist. Conventional surface roughness of solder resist material is described in [0023] as being approximately 30 nm, which falls within the claimed range of “less than 120 nm” (See MPEP 2144.05.I).
Bhate attributes this value to “a typical solder resist”. Cho does not state any particularities (chemical components and the like) about the solder resist used and thus it is considered to disclose a “typical solder resist” (the examiner also notes that the instant claims are similarly silent on material limitations/chemical components).
A person having ordinary skill in the art would have found it obvious to arrive at the claimed invention prior to the effective from the disclosure of Cho, Kawano, and Bhate - using a conventional solder resist having a surface roughness of approximately 30nm in order to protect the plated layers of Cho from deformation or damage.
Claim(s) 11 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (US 20140069694 A1), Kawano et al (US 20200343293 A1), and Yu et al (US 20180151453 A1) as applied to claim 9 and 10 above, and further in view of Chang et al (US 20080157362 A1).
Regarding Claims 11 and 12, Cho, Yu, and Kawano teach the limitations of the claims as discussed above regarding claims 9 and 10.
These references do not teach an embodiment wherein the width of the opening is substantially constant between the first and second surfaces and opens to increase away from the second surface toa third surface of the solder mask that faces away from the adhesion promoter, and where a width increases by a first rate from the second surface to an intermediate point between the second and third surfaces and then increases opening by a second rate from the point to a third surface where the first rate is greater than the second rate.
These limitations are met by Chang.
Change teaches a semiconductor substrate and conductive bump structure, wherein a metallization structure comprises a substrate 2, bonding pad 4, passivation layer 6, where the passivation layer has an opening to expose the bonding pad 4 - the passivation layer may be, for example, Silicon Nitride (SiN) ([0022]). One or more underbump metallization layers 8A-8D are deposited atop the pad and passivation layer ([0023]).
A photoresist mask layer is formed over the layer 8D and then patterned and developed, then etched to form an opening, where the opening comprises a recess 18 (an undercut in the resist), where this curved recess comprises a plurality of increases to the opening , where the rate of increase (slope) at the topmost vertical position along the recess is highest at a surface and decreases (the slope becomes more horizontal) at the inner surface of the recess/undercut,
Chang uses this recess to create thicker footing for a later-deposited layer/structure ([0024]) to protect it from undesired further undercutting during further processing.
A person having ordinary skill in the art would have found it obvious to arrive at the claimed invention by incorporating the undercut method of Chang into the assembly of Cho, Kawano, and Yu to thicken the base of the conductive feature of Yu applied to the assembly and prevent undercutting during further processing and etching.
Conclusion
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/A.P.T./Examiner, Art Unit 1737
/John S. Chu/Primary Examiner, Art Unit 1737
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