DETAILED ACTION
This Office Action is in response to the Amendment filed on November 10, 2025
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the second dielectric is coplanar with the channel layer" in line 10. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-15, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen (US Pub. 2020/0357822 A1).
In re claims 1, Chen shows (fig. 4i (i)) a memory device, comprising: a film stack comprising functional tiers stacked in a first direction, each functional tier comprising a first dielectric layer (405) and a conductive layer (418, 419); and channel structures (Poly Si Channel 409; see also fig. 4i(ii)) disposed in an array core region, wherein each channel structure extends through the film stack in the first direction and comprises: a control gate (413) in a center; a memory film (Ferroelectric Layer 411) disposed on a sidewall of the control gate and comprising a ferroelectric film; and a channel layer (Poly Si Channel) disposed on a sidewall of the memory film.
In re claim 3, Chen shows (fig. 4i (i)) a barrier layer (412) disposed between the control gate and the ferroelectric film; and an interface layer (410) disposed between the ferroelectric film and the channel layer.
In re claims 4-7, Chen shows (fig. 4i (i)) each functional tier further comprises a second dielectric layer (another layer 405). The second dielectric layer is coplanar with the conductive layer and the channel layer. The second dielectric layer (other layer of 405) separates the conductive layer into a first portion (419 top) and a second portion that (419 bottom) is electrically isolated from the first portion. In a second direction that is perpendicular to the first direction, a first end (top) and a second end (bottom) of the channel layer (409) contact the first portion and the second portion of the conductive layer, respectively.
In re claims 8, Chen shows (fig. 5) a first staircase structure (423, right, labeled) and a second staircase structure (left, not labeled) disposed in the film stack on opposite sides of the array core region, wherein each functional tier of the film stack corresponds to a first step of the first staircase structure and a second step of the second staircase structure.
In re claim 9, Chen shows (fig. 5) the first step of the first staircase structure is configured to provide electrical connection to the first portion of the conductive layer and the second step of the second staircase structure is configured to provide electrical connection to the second portion of the conductive layer.
In re claim 10, Chen shows (fig. 5) staircase contact pads disposed on the first step of the first staircase structure and the second step of the second staircase structure, wherein each of the staircase contact pads contacts a portion of the second dielectric layer and a portion of the conductive layer.
In re claims 11 and 12, Chen shows (fig. 4i (i)) a slit structure (414-1, 414-2, etc.) extending through the film stack in the first direction, wherein the slit structure is disposed between adjacent rows of channel structures, wherein slit structures extend in a second direction perpendicular to the first direction and are configured to separate the channel structures into different memory blocks, wherein each memory block comprises one or more rows of channel structures.
In re claims 13 and 14, Chen shows (fig. 4i (i)) a trench isolation (414 filled inside slit 414-1, 414-2) extending through the film stack in the first direction, wherein the trench isolation extending in a third direction that is perpendicular to the first direction and the second direction. The trench isolation (414) is connected with the second dielectric layer (another 405) of each functional tier.
In re claim 15, Chen shows (figs. 4c-4h(i)) a ferroelectric memory device, comprising: forming a dielectric stack (405,406; fig. 4c), wherein the dielectric stack comprises first dielectric layers (405-2) and second dielectric layers (405-3) alternatingly stacked in a first direction; forming a channel hole (407-1, 407-2, fig. 4d (i)) in the dielectric stack in an array core region; and forming a channel structure (409; fig. 4e) in the channel hole, comprising: forming a channel layer on a sidewall of the channel hole; forming a memory film (411; fig. 4f) on a sidewall of the channel layer, wherein the memory film comprises a ferroelectric film; and forming a control gate (413; fig. 4g) on a sidewall of the memory film.
In re claim 18, Chen shows (figs. 4c-4h(i)) forming a slit opening in the dielectric stack, wherein the slit opening extends in a second direction perpendicular to the first direction and is disposed between adjacent rows of channel structures; and replacing portions of the second dielectric layers exposed by the slit opening with conductive layers.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 16, 17, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US Pub. 2020/0357822 A1) as applied to claims 1 and 15 above, and further in view of Noh et al. (US Pub. 2020/0203427 A1).
In re claim 2, Chen shows (fig. 4i (i)) the control gate (413) and the memory film (411) extend through the film stack in the first direction. Chen shows all of the elements of the claims except the channel layer is disconnected in the first direction by the first dielectric layer of each functional tier. Noh shows (fig. 7A) a memory device having a channel layer (70) disconnected in the first direction by the first dielectric layer (30) of each functional tier. With this configuration, discrete or individual channels are formed thereby allowing for a more neuromorphic device [0014]. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to modify the memory device of Chen by forming the disconnected channels as taught by Noh to form a neuromorphic memory device.
In re claims 16 and 17, Chen shows all of the elements of the claims except the forming of the channel layer comprises: removing portions of the second dielectric layers of the dielectric stack that are exposed by the channel hole to form recesses on the sidewall of the channel hole; and disposing the channel layer in the recesses on the sidewall of the channel hole and wherein the forming of the channel layer further comprises removing portions of the channel layer on sidewalls of the first dielectric layers. Noh shows (figs. 24-28) a method of forming a memory device comprising removing portions of the second dielectric layers (20) of the dielectric stack (20, 30; fig. 24) that are exposed by the channel hole (H1; fig. 25A) to form recesses (CR; fig. 25A) on the sidewall of the channel hole; and disposing the channel layer (70; fig. 27A) in the recesses on the sidewall of the channel hole. The forming of the channel layer (70) further comprises removing portions (70a, fig. 26) of the channel layer on sidewalls of the first dielectric layers (30) (see the removed portions in fig. 27A). With this configuration, discrete or individual channels are formed thereby allowing for a more neuromorphic device [0014]. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to modify the memory device of Chen by forming the disconnected channels as taught by Noh to form a neuromorphic memory device.
In re claims 19 and 20, the neither reference specifically discloses forming trench isolation prior to forming the slit opening, however, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the components in any order, since it has been held that a mere reversal of the essential working parts of a device involves only routine skill in the art. In re Einstein, 8 USPQ 167.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Harari (US Pub. 2023/0262988 A1), Lee (US Pub. 202/30011675 A1), Wu (US Pub. 2021/0399052 A1), and Lai (US Pub. 2021/0183872 A1) each disclose various elements of the claims.
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/MATTHEW E WARREN/Primary Examiner, Art Unit 2815
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