DETAILED ACTION
This Office Action is in response to the RCE and Amendment filed on April 7, 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 6-22 are rejected under 35 U.S.C. 103 as being unpatentable over Noh et al. (US Pub. 2020/0203427 A1) in view of Chen (US Pub. 2020/0357822 A1).
In re claim 1, Noh et al. shows (figs. 2A,7C, 33A, 33B) a memory device, comprising: a film stack comprising functional tiers (30, 70, 76, 78) stacked in a first direction, each functional tier comprising a first dielectric layer (30), a second dielectric layer (20), a conductive layer (76, 78), wherein the second dielectric layer (20) is sandwiched between a first portion (76)of the conductive layer and a second portion (78) of the conductive layer in a second direction perpendicular to the first direction; and channel structures (70) disposed in an array core region, wherein each channel structure extends through the film stack in the first direction and comprises: a control gate (50) in a center; a memory film (60) disposed on a sidewall of the control gate and memory film, wherein the second dielectric layer (20) is coplanar with the channel layer (see fig. 30A, layer 20 is in the same layer structure as channel 70). Noh shows all of the elements of the claims except the memory film comprising a ferroelectric film. The limitation in question is patentably distinct over the cited prior art since ferroelectrics are well known to be used in semiconductor devices as memory films. However, Chen discloses [0018] ferroelectric materials can be used between a gate electrode and the channel to provide storage (memory) for a semiconductor device. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to modify the dielectric layer of Noh by using a ferroelectric because Chen teaches that ferroelectrics are suitable and compatible materials for use as memory layers in semiconductor devices.
In re claim 2, Noh and Chen, when combined, show all of the elements of the claims including wherein the control gate (Noh, fig. 33A, 50) and the memory film extend (60) through the film stack in the first direction (vertical), and the channel layer (70) is disconnected in the first direction by the first dielectric layer of each functional tier.
In re claim 3, Noh and Chen, when combined, show all of the elements of the claims including wherein the memory film further comprises:a barrier layer disposed between the control gate and the ferroelectric film; and an interface layer disposed between the ferroelectric film and the channel layer (Chen; [0018]).
In re claim 6, Noh and Chen, when combined, show all of the elements of the claims including wherein the second dielectric layer (Noh; fig. 33B, 20) separates the conductive layer into the first portion (76) and the second portion (78) that is electrically isolated from the first portion.
In re claim 7, Noh and Chen, when combined, show all of the elements of the claims including wherein in the second direction that is perpendicular to the first direction, a first end and a second end of the channel layer (70) contact the first portion and the second portion of the conductive layer (76,78), respectively (Noh; fig. 33B).
In re claims 8, Noh and Chen, when combined, show all of the elements of the claims including (Chen; fig. 5) a first staircase structure (423, right, labeled) and a second staircase structure (left, not labeled) disposed in the film stack on opposite sides of the array core region, wherein each functional tier of the film stack corresponds to a first step of the first staircase structure and a second step of the second staircase structure.
In re claim 9, Noh and Chen, when combined, show all of the elements of the claims including (Chen; fig. 5) the first step of the first staircase structure is configured to provide electrical connection to the first portion of the conductive layer and the second step of the second staircase structure is configured to provide electrical connection to the second portion of the conductive layer.
In re claim 10, Noh and Chen, when combined, show all of the elements of the claims including (Chen; fig. 5) staircase contact pads disposed on the first step of the first staircase structure and the second step of the second staircase structure, wherein each of the staircase contact pads contacts a portion of the second dielectric layer and a portion of the conductive layer.
In re claims 11 and 12, Noh and Chen, when combined, show all of the elements of the claims including (Chen; fig. 4i (i)) a slit structure (414-1, 414-2, etc.) extending through the film stack in the first direction, wherein the slit structure is disposed between adjacent rows of channel structures, wherein slit structures extend in a second direction perpendicular to the first direction and are configured to separate the channel structures into different memory blocks, wherein each memory block comprises one or more rows of channel structures.
In re claims 13 and 14, Noh and Chen, when combined, show all of the elements of the claims including (Chen; fig. 4i (i)) a trench isolation (414 filled inside slit 414-1, 414-2) extending through the film stack in the first direction, wherein the trench isolation extending in a third direction that is perpendicular to the first direction and the second direction. The trench isolation (414) is connected with the second dielectric layer (another 405) of each functional tier.
In re claim 15, Noh et al. discloses (figs. 24-35; [0138-0149]) a method for forming a ferroelectric memory device, comprising: forming a dielectric stack (fig. 24), wherein the dielectric stack comprises first dielectric layers (30) and second dielectric layers (20) alternatingly stacked in a first direction, wherein each second dielectric layer is stacked on top of and in contact with a corresponding first dielectric layer of the first dielectric layers; forming a channel hole (figs. 25B; H1) in the dielectric stack in an array core region; and forming a channel structure (figs. 26; 70a) in the channel hole, comprising: forming a channel layer (fig. 27A; 70) on a sidewall of the channel hole; forming a memory film (fig. 28; 60a) on a sidewall of the channel layer,
In re claim 16, Noh and Chen, when combined, show all of the elements of the claims. Noh shows (figs. 24-28) a method of forming a memory device comprising removing portions of the second dielectric layers (20) of the dielectric stack (20, 30; fig. 24) that are exposed by the channel hole (H1; fig. 25A) to form recesses (CR; fig. 25A) on the sidewall of the channel hole; and disposing the channel layer (70; fig. 27A) in the recesses on the sidewall of the channel hole.
In re claim 17, Noh and Chen, when combined, show all of the elements of the claims. Noh shows the forming of the channel layer (70) further comprises removing portions (70a, fig. 26) of the channel layer on sidewalls of the first dielectric layers (30) (see the removed portions in fig. 27A).
In re claim 18, Noh and Chen, when combined, show all of the elements of the claims. Chen shows (figs. 4c-4h(i)) forming a slit opening in the dielectric stack, wherein the slit opening extends in a second direction perpendicular to the first direction and is disposed between adjacent rows of channel structures; and replacing portions of the second dielectric layers exposed by the slit opening with conductive layers.
In re claims 19 and 20, neither reference specifically discloses forming trench isolation prior to forming the slit opening, however, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the components in any order, since it has been held that a mere reversal of the essential working parts of a device involves only routine skill in the art. In re Einstein, 8 USPQ 167.
In re claim 21, Noh and Chen, when combined, show all of the elements of the claims. Noh shows (fig.29) wherein each second dielectric layer (20) is stacked on top of and in contact with a corresponding first dielectric layer (30) of the first dielectric layers.
In re claim 22, Noh and Chen, when combined, show all of the elements of the claims. Noh shows (fig. 34B) the conductive layer (76, 78) of a functional tier of the functional tiers is disposed on both sides of the second dielectric layer (20) of the functional tier in an X direction perpendicular to a direction of stacking of the functional tiers such that the second dielectric layer is sandwiched between the conductive layer in the X direction.
Response to Arguments
Applicant’s arguments with respect to claims 1-22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/MATTHEW E WARREN/Primary Examiner, Art Unit 2815
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