DETAILED ACTION
1. This office action is in response to communication filed on 11/19/2025. Claims 1 and 12 have been amended. Claims 3-5 and 14-15 have been canceled. Claims 1-2, 6-13 and 16-20 are pending on this application.
Response to Arguments
2. Applicant's arguments filed 11/19/2025 with respect to amended claims 1 and 12 have been fully considered but they are not persuasive.
Under remark, applicant argued “Wang does not teach suggest these features: produce a first digital output indicative of a result of a comparison between the analog input voltage and the first reference voltage, wherein the first non-volatile memory device comprises a first memristor device, wherein the first digital output indicates whether a first resistance state of the first memristor device after an application of the first reference voltage and the analog input voltage to the first comparator is an initial resistance state of the first memristor device before the application of the first reference voltage and the application of the analog input voltage to the first comparator, wherein the initial resistance state comprises a high-resistance state or a low- resistance state, and wherein the first memristor device switches between the high- resistance state and the low-resistance state according to a voltage across the first memristor that corresponds to a difference between the first reference voltage and the analog input voltage," as recited in amended claim 1. (Emphasis added.). Applicant further submits that the Office action does not rely on Ge to teach these features and do not cure the deficiencies of Wang.”. Examiner respectful disagrees from the following:
A magnetoresistive device is understood of as a magnetic resistance non-volatile memory device (such as MRAM), each magnetoresistive device can have a "high" or "low" resistance state, which can be determined by the relative orientation of the magnetic moments in the device layers. The negative spin current can influence these states, leading to a change in the device's overall resistance.
Fig. 6 and Col. 13 lines 35-52 of Wang discloses: Multiplexer 622 may be electrically connected to conductive channel 612, which allows the selective application of the analog input voltage to conductive channel 612. For example, the magnetization states of magnetoresistive devices 605 do not change until explicitly reset, even if no power is applied (e.g., magnetoresistive devices 605 are non-volatile). Accordingly, the magnetization states of magnetoresistive devices 605 need to be periodically reset (e.g., every time a new comparison needs to be made). When magnetoresistive devices 605 are to be reset, controller 614 outputs a signal to the EN2 pin that allows the voltage at the RESET pin of multiplexer 622 to be applied to conductive channel 622. In normal operation (e.g., when the magnetization states of magnetoresistive devices 605 are used for analog-to-digital conversion), controller 614 (or some other unit) outputs a signal to the EN2 pin that causes multiplexer 622 to output the pulse from S&H 620
Col. 15 line 40 to Col. 16 line 22 of Wang discloses: In operation, ADC 600 may include three phases: 1) a reset phase, 2) a conversion phase, and 3) a read-out phase. The first phase in ADC operation is to reset ADC 600 into a preset state. In some examples, ADC 600 may be reset by applying a large negative spin-current (J) to set each of the respective magnetoresistive devices 605 into a preset stage. For instance, the voltage at the RESET pin of multiplexer 622 may cause a large current to flow through conductive channel 612, which in turn causes a large negative spin-current to output to each of magnetoresistive devices 605 to present magnetoresistive devices 605.
Once ADC 600 has been reset, the conversion phase may be initiated. In operation, the conversion stage includes applying a reference voltage across the resistor ladder, thus generating a different bias voltage at each tap 603 of the resistance ladder. Controller 614 may generate a controller voltage which may turn on all of the switches 604. When all of the switches 604 are on, the respective bias voltage (and thus bias current) at each switch 604 may be applied to the respective magnetoresistive device 605. In some examples, the spin-current may be proportional to the input analog voltage and the direct current. Thus, the spin-current may change the magnetization state of each of the respective magnetoresistive devices 605 where the spin-current is greater than the bias current for the respective magnetoresistive device 605. After conversion, switch 604 may be turned off. This conversion phase may be considered as a phase to set the magnetization state.
The third phase of operation of ADC 600 is the read-out phase. After the respective magnetoresistive devices 605 have been switched to the appropriate state (AP or P), controller 614 may determine the magnetization state of each respective comparator 605 and represent the magnetization state as a logical value that forms a signal output 616. In some examples, the encoder may determine the magnetization state of each respective comparator 605 and no conversion to a logical value may be needed. In such examples, the magnetization state may be considered as output signals 616.
ADC 600 may contain 2.sup.n output signals 616, one for each of the comparators 601. Each respective output signal 616 may be output to an encoder (FIG. 8, 800) which may convert the respective output signals 616 into a digital value. Since the magnetoresistive devices 605 are non-volatile, the conversion results are accessible at any time. For example, after controller 614 turns off switches 604, by applying a voltage or a current at output 616 to each of magnetoresistive devices 605 and determining the current or voltage, respectively, controller 614 or the encoder may determine the impedance of magnetoresistive devices 605, and the impedance indicates the magnetization state.
As understood of magnetorestive device, Fig. 6 described by Col. 13 lines 35-52 and Col. 15 line 40 to Col. 16 line 22 Wang discloses: produce a first digital output (b2n) indicative of a result of a comparison (601) between the analog input voltage (Input) and the first reference voltage (first reference 603) , wherein the first non-volatile memory device (first memory magnetorestive 605) comprises a first magnetorestive device (first magnetorestive 506), wherein the first digital output (b2n) indicates whether a first resistance state (high or low resistance state of magnetorestive 506) of the first magnetorestive device (605) after an application of the first reference voltage (first reference 603) and the analog input voltage (Input) to the first comparator (comparator 601) is an initial state (Col. 15 lines 40-44 disclose “In operation, ADC 600 may include three phases: 1) a reset phase, 2) a conversion phase, and 3) a read-out phase. The first phase in ADC operation is to reset ADC 600 into a preset state”; wherein the preset state is an initial state of each magnetoresitive 605 and preset state of each magnetoresitive 605 is either a high or low resistance state) of the first magnetorestive device (605) before (Col. 15 lines 40-44 disclose “In operation, ADC 600 may include three phases: 1) a reset phase, 2) a conversion phase, and 3) a read-out phase. The first phase in ADC operation is to reset ADC 600 into a preset state”) the application of the first reference voltage (first reference voltage 603) and the application of the analog input voltage (Input) to the first comparator (first 601), wherein the initial resistance state (preset state of 605 as described on Col. 15 lines 40-44) comprises a high-resistance state or a low- resistance state (each magnetoresistive device can have a "high" or "low" resistance state), and wherein the first magnetoresitive device switches between the high- resistance state and the low-resistance state (switching between high and low resistance states of 605) according to a voltage across the first magnetoresitive (voltage cross of 605 from potential difference between voltage input and voltage reference 603) that corresponds to a difference between the first reference voltage (first voltage reference 603) and the analog input voltage (Input).
However, Wang et al. discloses magnetoresitive device instead of memristor device as claimed.
Fig. 1 and Fig. 2 of Ge et al. discloses an apparatus (100, 200), comprising: a first comparator (106) comprising a first memristor non-volatile memory device (106, 206).
Wang et al. and Ge et al. are common subject matter of non-volatile memory device of comparator; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate the non-voltatile memristor memory device of Ge et al. into non-voltatile magnetoresitive memory device Wang et al. for the purpose of providing a non-volatile storage element the reduced power consumption and battery life is increased (paragraph 0012 of Ge et al.).
Memristor of Ge et al. cure the deficiencies of Wang, by modified by magnetoresistive device of Wang with the Memristor device of Ge et al. Accordingly, the subject matter of amended claims 1 and 12 are unpatentable over previous cited references Wang and Ge et al.
In this office action, the rejections of claims 1-2, 6-13 and 16-20 are sustain from previous cited references.
Claim Objections
3. Claim 6 is objected to because of the following informalities: Claim 6 depended on claim 4. However, claim 4 has been canceled. Appropriate correction is required.
Claim 16 is objected to because of the following informalities: Claim 16 depended on claim 15. However, claim 15 has been canceled. Appropriate correction is required.
Claim 17 is objected to because of the following informalities: Claim17 depended on claim 15. However, claim 15 has been canceled. Appropriate correction is required.
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claim(s) 1-2, 6-10, 12-13, and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. U.S. patent No. 9,240,799 in view of Ge et al. Pub. No. 2019/0261884.
Regarding claim 1. Fig. 6 of Wang et al. discloses n apparatus (600) , comprising: a first comparator (first 601; Col. 12 lines 41-42) comprising a first non-volatile memory device (magnetoresistive 605, Col. 13 line 41), wherein the first comparator (first 601) is to: receive a first reference voltage (first reference voltage 603) and an analog input voltage (Input) as inputs ((input of each comparator 601); and produce a first digital output ( b2n) indicative of a result of a comparison (result of 601) between the analog input voltage (voltage on Input) and the first reference voltage (First refence voltage 603) , wherein the first non-volatile memory device (605) comprises a first magnetoresistive device (first 605) , wherein the first digital output ( b2n) indicates whether a first resistance state (high or low resistance state of 605) of the first magnetoresistive device (605) in response to after an application of the first reference voltage (first reference voltage 603) and the analog input voltage (Input) to the first comparator (603) is an initial resistance state (Col. 15 lines 40-44 disclose “In operation, ADC 600 may include three phases: 1) a reset phase, 2) a conversion phase, and 3) a read-out phase. The first phase in ADC operation is to reset ADC 600 into a preset state”; wherein the preset state is an initial state of each magnetoresitive 605 and preset state of each magnetoresitive 605 is either a high or low resistance state) of the first magnetoresitive device (605) before the application of the first reference voltage (first 603) and the application of the analog input voltage (Input) to the first comparator (601), wherein the initial resistance state (reset to preset state described in Col. 15 lines 40-44 ) comprises a high-resistance state or a low-resistance state (A magnetoresistive device is understood of as a magnetic resistance non-volatile memory device (such as MRAM), each magnetoresistive device can have a "high" or "low" resistance state), and wherein the first magnetoresistive device (605) switches between the high-resistance state and the low- resistance state (switches between high and low resistance state of each 605) according to a voltage (voltage cross of 605 from potential difference between voltage input and voltage reference 603) that corresponds to a difference between the first reference voltage (first voltage reference 603) and the analog input voltage (Input).
However, Wang discloses magnetoresistive device instead of memristor device as claimed.
Fig. 1 and Fig. 2 of Ge et al. discloses an apparatus (100, 200), comprising: a first comparator (106) comprising a first memristor non-volatile memory device (106, 206).
Wang et al. and Ge et al. are common subject matter of non-volatile memory device of comparator; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Ge et al. into Wang et al. for the purpose of providing a non-volatile storage element the reduced power consumption and battery life is increased (paragraph 0012 of Ge et al.).
Regarding claim 2. Wang et al. and Ge et al. applied to claim 1 above, Fig. 8 of Wang et al. further comprising: an encoder (800) to generate one or more binary values (d1…dn) based at least in part on the first digital output (b2n) generated by the first comparator (601).
Regarding claim 6. Wang et al. combined with Ge et al. applied to claim 4 above, Fig. 6 of Wang further comprising: one or more programming circuits (614) to program the first memristor (605 modified by memristor of Ge et al. applied to claim 1 above) to the initial resistance state (Col. 15 lines 40-44 disclose “In operation, ADC 600 may include three phases: 1) a reset phase, 2) a conversion phase, and 3) a read-out phase. The first phase in ADC operation is to reset ADC 600 into a preset state”; wherein the preset state is an initial state of each magnetoresitive 605 and preset state of each magnetoresitive 605 is either a high or low resistance state).
Regarding claim 7. Wang et al. combined with Ge et al. applied to claim 1 above, Fig. 6 of Wang et al. further discloses: a second comparator (second 601; Col. 41-43) comprising a second non-volatile memory device (second 605), wherein the second non-volatile memory device (second 605) comprises a second memristor device (second 605 modified by memristor of Ge et al. applied to claim 1 above) wherein the second comparator (second 601) is to generate a second digital output ( b2n-1) indicative of a result of a comparison (second comparator 601) of the analog input voltage (INPUT) with a second reference voltage (second tap of voltage divider by resistor ladder 602), wherein the second digital output ( b2n-1) represents a second resistance state of the second memristor (state of second 605; 605 modified by memristor of Ge et al. applied to claim 1 above) in response to an application of the second reference voltage (second tap of resistor ladder) and an application of the analog input voltage (INPUT) to the second comparator (second 601).
Regarding claim 8. Wang et al. combined with Ge et al. applied to claim 7 above, Fig. 6 of Wang et al. further discloses: wherein the second digital output (b2n-1) indicates whether the second resistance state of the second memristor device (state of second 605; 605 modified by memristor of Ge et al. applied to claim 1 above) is in a high-resistance state or a low-resistance state (Col. 15 lines 25-28).
Regarding claim 9. Wang et al. combined with Ge et al. applied to claim 7 above, Fig. 6 of Wang et al. further discloses wherein the second memristor device (second 605; 605 modified by memristor of Ge et al. applied to claim 1 above) is programmed to an initial resistance state (Initial state of 605) before the application of the second reference voltage (second reference of resistor ladder) and the application of the analog input voltage (Vin) to the second comparator (second 605) , and wherein the first second digital output (b2n-1) comprises a voltage signal (voltage signal of b2n-1 ) indicative of whether the second memristor device (second 605; 605 modified by memristor of Ge et al. applied to claim 1 above) remains in the initial resistance state (initial state of 605; (Col. 13 lines 38-41) after the application of the second reference voltage (second reference voltage reference ladder) and the application of the analog input voltage (input) to the second comparator (second 601).
Regarding claim 10. Wang et al. combined with Ge et al. applied to claim 1 above, Fig. 6 of Wang et al. further discloses a voltage divider circuit (voltage divider by resistor ladder 602) to generate a plurality of reference voltages (plurality of reference taps 603), wherein the plurality of reference voltages (plurality of reference taps 603) comprises the first reference voltage (first tap reference 603).
Regarding claim 12. Fig. 6 of Wang et al. discloses a method for performing analog-to-digital conversion (Col. 12 lines 39-40), comprising: programming a first magnetoresistive device (605) to an initial resistance state (Col. 13 lines 35-52 discloses Reset State of 605) by applying a programming voltage (Col. 15 lines 40 to Col. 16 line 22 discloses in the reset state of 605 the voltage at the RESET pin of multiplexer 622 may cause a large current to flow through conductive channel 612, which in turn causes a large negative spin-current to output to each of magnetoresistive devices 605 to present magnetoresistive devices 605) to the first magnetoresistive device (605); applying, to a first comparator first (601; Col. 12 lines 41-42) comprising the first magnetoresistive device (first 605) that is programmed to the initial resistance state (Col. 15 lines 40 to Col. 16 line 22 discloses in the reset state of 605 the voltage at the RESET pin of multiplexer 622 may cause a large current to flow through conductive channel 612, which in turn causes a large negative spin-current to output to each of magnetoresistive devices 605 to present magnetoresistive devices 605), a first reference voltage (first 603); applying an analog input voltage (voltage of Input ) to the first comparator (601), wherein the initial resistance state (Col. 15 lines 40-44 disclose “In operation, ADC 600 may include three phases: 1) a reset phase, 2) a conversion phase, and 3) a read-out phase. The first phase in ADC operation is to reset ADC 600 into a preset state”; wherein the preset state is an initial state of each magnetoresitive 605 and preset state of each magnetoresitive 605 is either a high or low resistance state) comprises a high-resistance state or a low-resistance state (A magnetoresistive device is understood of as a magnetic resistance non-volatile memory device (such as MRAM), each magnetoresistive device can have a "high" or "low" resistance state), and wherein the first magnetoresistive device (first 605) switches between the high-resistance state and the low-resistance state (switches between high and low resistance stage of 605) according to a voltage across (voltage cross of 605 from potential difference between voltage input and voltage reference 603) the first magnetoresistive (605) that corresponds to a difference between the first reference voltage (first reference voltage 603) and the analog input voltage (voltage Input) ; and producing, based on the voltage signal (voltage signal for 605), a first digital output (b2n) indicative of a result of a comparison (result of 601) between the analog input voltage (Vin) and the first reference voltage (603).
However, Wang discloses magnetoresistive device instead of memristor device as claimed.
Fig. 1 and Fig. 2 of Ge et al. discloses an apparatus (100, 200), comprising: a first comparator (106) comprising a first memristor non-volatile memory device (106, 206).
Wang et al. and Ge et al. are common subject matter of non-volatile comparator; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Ge et al. into Wang et al. for the purpose of providing a non-volatile storage element the reduced power consumption and battery life is increased (paragraph 0012 of Ge et al.).
Regarding claim 13. Wang et al. combined with Ge et al. applied to claim 12 above, Fig. 8 of Wang et al. further discloses: generating, by an encoder (800), one or more binary values (d1…dn) based at least in part on the first digital output (b2n).
Regarding claim 16. Wang et al. combined with Ge et al. applied to claim 15 above, Fig. 6 of Wang et al. further discloses wherein the first digital output (b2n) indicates whether the first resistance state of the first memristor device (first 605 modified by memristor of Ge et al. applied to claim 1 above) is the high-resistance state or the low-resistance state (Col. 15 lines 25-28).
Regarding claim 17. Wang et al. combined with Ge et al. applied to claim 15 above, Fig. 6 of Wang et al. further discloses: programming (614 and Reset) the memristor device (first 605; 605 modified by memristor of Ge et al. applied to claim 1 above) to the initial resistance state (Col. 13 lines 38-41) after producing (Col. 13 lines 41-44 discloses “the magnetization states of devices 605 need to be periodically reset (e.g., every time a new comparison needs to be made)”) the first digital output (b2n).
Regarding claim 18. Wang et al. combined with Ge et al. applied to claim 12 above, Fig. 6 of Wang et al. further discloses:, Fig. 6 further comprising: applying, to a second comparator (second 601) comprising a second memristor device (second 605; 605 modified by memristor of Ge et al. applied to claim 1 above), a second reference voltage (second tap 301 of resistor divided circuit 602) and the analog input voltage (Input); and producing, using the second comparator (second 601), a second digital output (b2n-1) indicative of a result of a comparison (result of second 601) between the analog input voltage (input) and the second reference voltage (second tap 301 of resistor divided circuit 602).
Regarding claim 19. Wang et al. combined with Ge et al. applied to claim 18 above, Fig. 6 of Wang et al. further discloses: wherein the second digital output (b2n-1) indicates whether the second memristor device (second 605; 605 modified by memristor of Ge et al. applied to claim 1 above) is in a high resistance state or a low-resistance state (A magnetoresistive device is understood of as a magnetic resistance non-volatile memory device (such as MRAM), magnetoresistive device can have a "high" or "low" resistance state).
7. Claims 11 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. combined with Ge et al. applied to claim 1 and 12 above, and further in view of Andre U.S. patent No. 7,697,321.
Regarding claim 11. Wang et al. combined with Ge et al. applied to claim 1 above discloses wherein the voltage divider circuit (voltage divider by resistor ladder 602) but does not disclose wherein the voltage divider circuit (voltage divider by resistor ladder 602) comprising a plurality of non-volatile memory devices (605) connected in series.
Fig. 2 of Andre discloses voltage divider circuit (voltage divider 208-212, and 216-212) comprising a plurality of non-volatile memory devices (Col. 3 lines 20-32 disclose magnetic resistance element of each 208-216) connected in series (series of 208-212, and 216-212).
Wang et al./Gei et al. and Andre are common subject matter of voltage divided formed by resistors connected in series; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Andre into Wang et al./Gei et al. for the purpose of providing a non-volatile storage element usable in an integrated circuit that is able to retain the state of the storage element in the absence of power to the integrated circuit (Col. 1 lines 25-29 of Andre).
Regarding claim 20. Wang et al. combined with Ge et al. applied to applied to claim 12 above Fig. 6 of Wang et al. further discloses wherein the voltage divider circuit (voltage divider by resistor ladder 602) but does not disclose wherein the voltage divider circuit (voltage divider by resistor ladder 602) comprising at least one of non-volatile memory device.
Fig. 2 of Andre discloses voltage divider circuit (voltage divider 208-212, and 216-212) comprising at least of non-volatile memory device (Col. 3 lines 20-32 disclose magnetic resistance element of each 208-216).
Wang et al/Gei et al. and Andre are common subject matter of voltage divided formed by resistors connected in series; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Andre into Wang et al./Gei et al. for the purpose of providing a non-volatile storage element usable in an integrated circuit that is able to retain the state of the storage element in the absence of power to the integrated circuit (Col. 1 lines 25-29 of Andre).
Conclusion
8. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
11/29/2025
/LINH V NGUYEN/Primary Examiner, Art Unit 2845