Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1, 3 and 4 have been amended. Claims 5 and 6 are newly added claims.
Response to Amendment
Amendment to the title has been acknowledged and accepted. Amendment to the specification is objected as it has a minor informality which includes the typo “impedanceinductance” in ¶ [0016]. Correction is required.
Amendments to Claims 1, 3, and 4 are acknowledged. However, the amendment of claim 1 fails to address the 35 USC §112(b) rejection of claim 1 from the previous office action dated 06/05/2025, therefore, rejection is maintained. Corrections are required.
Response to Arguments
Applicant's arguments filed 10/06/2025 have been fully considered but they are not persuasive. The applicant argues in pg. 6 that the amendment to claim 1 which now recites the limitation “the conductive plane is electrically insulated from the semiconductor chip,” is not taught by the individual or combined disclosure of Domes or Kamikura. However, the examiner reasserts the rejection of the previous office action dated 06/05/2025 and submit that the rejection which maps applicant’s conductive plane 52 to Dome’s Metallization layer 31 (311, 312) must be electrically insulated in some areas from the semiconductor chip in order functionally connect bond wires 51 and 52. Otherwise, the lack of electrical insulation would short the electrical signals, rendering bond wires 51 and 52 of Domes, useless. However, in order to advance prosecution, the examiner presents a new mapping where the applicant’s conductive plane 52 is mapped to metallization layer 12 or 22 of Domes as discussed below.
The applicant further argues in pg. 7 that a person of ordinary skill in the art would not look to Kamikura in light of Domes for the addition of specific component as there would be no expectation of success that including an inductor 32 would lead to solving parasitic capacitances between the semiconductor chip and the insulating substrate or between the conductive plane and the sole plate. However, the examiner submits that these elements mentioned by the applicant are present in both the disclosures of Domes and Kamikura where the aim of both disclosure is to reduce the electromagnetic noise generated amongst these capacitive elements (Domes [0002], Kamikura [0004]). Therefore, a person of ordinary skill would have looked to both references to learn their various methods of suppressing electromagnetic noise via the use of metallization layer (Domes) and metallization layers coupled with resistors and inductors (Kamikura).
Specification
The substitute specification filed 10/05/2025 has not been entered because it does not conform to 37 CFR 1.125(b) and (c) because: ¶[0016] contains the typo “impedanceinductance”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding the independent claim 1, the limitation "at least 1µH" is indefinite as this is not a known unit for impedance. For examination purposes, the examiner interprets this limitation as the imaginary component of the impedance, jX, is at least 1 Ohm.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Domes (DE 10 2013210146 A1), hereinafter referred to as Domes, in further view of Kamikura et al. (US 20180007785 A1), hereinafter referred to as Kamikura.
Regarding the independent claim 1:
[AltContent: textbox (: Exhibit 1: Domes, Fig. 3, depicting sole plate 32, insulating layer 10, 20, semiconductor devices 6 and 7.)]
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Domes teaches a component which is configured to switch an electrical signal, the component comprising: an insulating substrate bearing a semiconductor chip which ensures switching of the electrical signal (Domes [0031], Fig. 3 depicts semiconductor chips (6, 7), and insulation carrier (10), The examiner notes that the semiconductor chip of Domes refers to any type of bipolar or unipolar transistor which are known in the art for their switching capabilities. (Domes [0053] “…any type of bipolar or unipolar transistor, for example an insulated gate field effect transistor (IGFET), a JFET, thyristors, but also any other electrical power components. Suitable IGFETs include MOSFETs or IGBTs, but also all other types of IGFETs.”);
a sole plate on which the substrate is secured (Domes [0031], Fig. 3 depicts sole plate (32), “…lower metallization layer 32”),
the sole plate being configured to discharge heat emitted during switching of the component (Dome [0033] Fig. 3, depicts sole plate 32 in thermal contact with heat sink 9, “to reduce the thermal contact resistance between the heat sink 9 and the main substrate 3, a thermally conductive paste can be introduced between the heat sink 9”;
a conductive plane positioned between the plate and the insulating substrate (Domes Fig. 3 conductive plane 12, 22, between insulating substrate 10, 20, and plate 32.
the conductive plane being insulated electrically against the sole plate (Domes Fig. 3, insulation 30 electrically insulating elements above it including conductive plane 12, 22, [0031] “… are electrically insulated from each other by the electrically insulating carrier 30.”);
Domes fail to teach the device further comprising a specific component with impedance of at least 1 Ohm and/or at least 1 µH, by means of which the conductive plane is connected to a reference voltage.
[AltContent: textbox (Exhibit 2: Fig. 3 Kamikura with semiconductor devices 30, insulating substrate 11, and conducting plane 21)]
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However, in a similar field of endeavor, Kamikura teaches a power circuit device with a conductive plate 21 that is connected to a reference voltage through a ground wire 22 (Kamikura [0037], Fig. 1 and Fig. 2 depicting conductive plate 21 connected to a ground wire 22. Fig. 3, depicting the placement of conductive plate 21 beneath circuit board 11 (support substrate of semiconductor components (4, 5))).
Furthermore, Kamikura teaches a variation of this device wherein the conductive plate 21 is connected to a specific component, which is a resistor 33, that is then connected to the reference voltage, which in this case, is a ground voltage (Kamikura [0081], Fig. 15, “…conductive plate 21 and first metal frame 9a may be connected by resistance 33”).
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Kamikura further teaches that the value of resistance 33 is determined such that the impedance of the noise loop is high enough to direct the flow of the common mode current towards a preferred noise loop where a noise filter (3 and 2) is installed (Kamikura [0081] “In this case, a value of the resistance 33 is determined so that impedance of the noise loop 17 is higher than that of the noise loop 16”). Therefore, it is conceivable to implement a resistor having an impedance of at least 1 Ohm or at least 1 µΩ depending on the application or specifications of the device. Furthermore, the determination of the appropriate impedance for the resistor is considered knowable via routine optimization and experimentation using known methods in the art and therefore lacks the required inventive step.
[AltContent: textbox (Exhibit 3 Kamikura Fig. 15 depicting resistor 33 connecting conducting plane 21 to ground.)]
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, to apply the teachings Kamikura to the disclosure of Domes, to implement a grounded conductive plate with resistive components in order to further suppress the formation of common mode currents on the outer regions of the device such as a sole plate, heatsink or a chassis or housing (Kamikura [0014]). This is obvious to try as electromagnetic noise is known to cause signal interferences, device inefficiencies, and device malfunctions (Kamikura [0002]-[0003]).
Regarding the claim 2: The combined disclosure of Domes and Kamikura teaches the component of claim 1.
Domes fails to teach the component wherein the specific component is a resistor of at least 1 Ohm.
However, in a related field of endeavor, Kamikura teaches the wherein the specific component is a resistor of at least 1 Ohm (Kamikura [0081], Fig. 15, “…conductive plate 21 and first metal frame 9a may be connected by resistance 33… a value of the resistance 33 is determined so that impedance of the noise loop 17 is higher than that of the noise loop 16”).
Similar to the discussion in the rejection of claim 1, since Kamikura further teaches that the value of resistance 33 is determined according to the characteristics of the noise loop pathway, it is conceivable to implement a resistor having an impedance of at least 1 Ohm depending on the application and specifications of the device. Furthermore, the determination of the appropriate resistor to be used is considered knowable via routine optimization and experimentation using known methods in the art and therefore lacks the required inventive step.
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, to apply the teachings Kamikura to the disclosure of Domes, to implement a grounded conductive plate that is connected to a resistor in order to further suppress the formation of common mode currents on the outer regions of the device such as a sole plate, heatsink or a chassis or housing (Kamikura [0014]). This is obvious to try as electromagnetic noise is known to cause signal interferences, device inefficiencies, and device malfunctions (Kamikura [0002]-[0003]).
Regarding Claim 3: The combined disclosure of Domes and Kamikura teaches the component of claim 1 that may comprise a static converter.
Domes teaches the component wherein the plates of each component are in common (Domes Fig. 3, depicting the plate 32 to be both shared by both components 311 and 312).
Domes fail to teach wherein the conductive planes of each component are in common.
However, in a related field of endeavor, Kamikura teaches the use of a conductive plane that is in common (Kamikura Fig. 2, depicts the conductive plane to be shared among all the components (4, 5) underneath heat sinks (30)).
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, to apply the teachings of Kamikura to the disclosure of Domes, in order to implement a conductive plane along with a sole plate that is both common to all components. This is obvious to try as the addition of a conductive plane with a resistive element is a known method of suppressing common mode currents in static converter devices, with the expected results of being able to mitigate the negative effects of common mode currents such as unwanted signal interferences, device inefficiencies, and device malfunctions (Kamikura [0002]-[0003], [0014]).
Regarding claim 4: The combined disclosure of Domes and Kamikura teaches the component of claim 1 that may comprise a static converter wherein the conductive planes and the sole plates of each component are in common.
Domes further teaches the component further comprising a first group of components and a second group of components (Domes Fig. 8, depicting first group of components 100-1, and second group 100-2),
wherein, in each of the groups of components the plates of each component are in common (Domes Fig. 8, depicting the plate 32 to be in common amongst the components in each of the group),
Domes fail to teach wherein, in each of the groups of components the conductive planes are in common , wherein the conductive plane of the first group is connected to a first reference voltage by means of a first inductor, and the conductive plane of the second group is connected to a second reference voltage by means of a second inductor, and wherein the two inductors are coupled, and have an impedance of at least 1 µH.
However, in a similar field of endeavor, Kamikura teaches a static converter device where a common conductive plane is implemented.
Kamikura further teaches that in each of the groups of components the conductive planes are in common (Kamikura [0037], Fig. 2 and Fig. 3, depicts the conductive plane (21) to be shared among all the components (5, 6) underneath heat sinks (30))
wherein the conductive plane of the first group is connected to a first reference voltage by means of a first inductor (Kamikura [0037], Fig. 1, “common mode coil 2 and the conductive plate 21 are connected by a bypass capacitor 20”.). The examiner also notes that in Fig. 1, the wire 8 connecting the bottom inductor is noted as the negative side which is interpreted by the examiner as being the first reference voltage (Kamikura [0036], Fig. 1 (8) “while negative polarity sides thereof form a second wire 8.”),
and the conductive plane of the second group is connected to a second reference voltage by means of a second inductor (Kamikura [0037], Fig. 1 , “common mode coil 2 and the conductive plate 21 are connected by a bypass capacitor 20”). The examiner also notes that in Fig. 1, the other side of the conductive plane 21 is shown to form an electrically conductive loop via parasitic capacitance, that is connected to the top inductor through the wire 7 which is noted to have a positive polarity, which the examiner interprets as the second reference voltage, (Kamikura [0036] “One common mode coil 2 is connected to the system power supply 100…Positive polarity [side] of the rectifier circuit 4, step-up circuit 10, and inverter 5 form a first wire 7”),
and wherein the two inductors are coupled (Kamikura [0036], Fig. 1 “a grounding capacitor 3 is
attached to either end of a common mode coil 2.” Where the examiner notes that in Fig. 1, the common mode coil 2 is shown to comprise of two coupled inductors sharing a common magnetic core indicated by parallel lines as is known in the art and similar to what is shown in fig. 5 of the applicant’s disclosure.),
and have an impedance of at least 1 µΩ (Kamikura [0073] “a value of the inductor 32 is determined so that impedance of a noise loop 17 is higher than that of the noise loop 16.” Where the examiner interprets this as being able to modify the impedance of the inductor according to the specific applications of the device. Furthermore, the determination of impedance values is considered by the examiner to be knowable as a part of routine experimentation or optimization and therefore lacks the required inventive step.)
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, to apply the teachings of Kamikura to the disclosure of Domes, in order to implement, in addition to a common sole plate, a conductive plane that is also common and is connected to reference voltages via coupled inductors as this is a known method of suppressing common mode currents as taught by Kamikura. This is obvious to try as it is desirable to mitigate the negative effects associated with common mode currents such as unwanted signal interferences, device inefficiencies, and device malfunctions (Kamikura [0002]-[0003], [0014]).
Re: Claim 5. The combined disclosure of Domes and Kamikura teaches the component of claim 1.
Domes further teach the component wherein the insulating substrate is directly in placed on the conductive plane (Domes Fig. 3, insulating substrate 10, 20, directly placed on 12, 22),
Re: Claim 6. The combined disclosure of Domes and Kamikura teaches the component of claim 1.
Domes further teach the component wherein the insulating substrate further is covered by a metallization configured to electrically connect the semiconductor chip to ensure switching of the electrical signal (Domes Fig. 3 metallization layer 11, 21, covering insulating substrate 10, 20 where connecting layer 43 (44) and bond wire 51 (52) indicate that metallization layer 11 (and 21) are electrically connected to the semiconductor chip 6. (7)).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILIO ARDEO whose telephone number is (703)756-1235. The examiner can normally be reached Mon-Fri EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EMILIO ARDEO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899