Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/11/2026 has been entered with this RCE.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 18, the claim has dependency to claim 2, which has been cancelled, therefore the scope of the claim is unclear based from the new claims seen in the amendment filed 05/11/2026. Since claim 2 was dependent to claim 1 as seen in the claims from 12/29/2022 for examination, the claim 18 will assume dependency to claim 1 and be examined below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 12-13 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable by Park et al. (US-20190115079-A1 referred to as Park).
Regarding claim 1. Park discloses a semiconductor device comprising: a device with high clamping voltage (HVC device), and an ovonic threshold device (OTS) device, wherein the HVC device and the OTS device are connected in series and configured for electrostatic discharge protection ([0020, 0029], figure 1, the HVC device #120 and the OTS device #112 are seen connected in series. Since both devices (#120 and #112) are connected in series, the electronic components within the devices would allow protection for the circuitry since the connectivity is linear (in series) which further allows protection for the other device, therefore, reads on ‘configured for’ electrostatic discharge protection – noting that the prior art has the same configuration as the claimed limitations, therefore, would both be ‘configured for ESD protection’ – if there are further structural limitations that distinguish the present invention over the prior art as to reasons for ESD protection, they should be part of the claimed invention).
Regarding claim 3. Park discloses a semiconductor device as claimed in claim 1, wherein the HVC device and the OTS device are combined in a package ([0020, 0029], figure 1, the HVC device #120 and the OTS device #112 are seen combined in one circuitry package).
Regarding claim 12. Park discloses method of producing a semiconductor device as claimed in claim 1 comprising: connecting the HVC device in series with the OTS device and configured for electrostatic discharge protection ([0020, 0029], figure 1, the HVC device #120 and the OTS device #112 are seen connected in series. Since both devices (#120 and #112) are connected in series, the electronic components within the devices would allow protection for the circuitry since the connectivity is linear (in series) which further allows protection for the other device, therefore, could be configured for electrostatic discharge protection).
Regarding claim 13. Park discloses wherein the HVC device and the OTS device are combined in a package ([0020, 0029], figure 1, the HVC device #120 and the OTS device #112 are seen combined in one circuitry package).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 14, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US-20190115079-A1) in view of Pryor et al. (US-4845533-A referred to as Pryor).
Regarding claim 4. Park lacks wherein the OTS device is integrated in a metal stack of the HVC device.
Pryor discloses wherein the OTS device is integrated in a metal stack of the HVC device ([col 10 lines 18-31], figure 3, the threshold switching material #38 represents the ovonic threshold switch made of chalcogenide. The OTS #38 is seen integrated in a metal stack #42 and #34).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Park to include a threshold switching device in a metal stack as taught by Pryor in order to provide steep switching for high voltages and quick switch responses without degradation.
Regarding claim 14. Park as modified lacks wherein the OTS device is integrated in a metal stack of the HVC device.
Pryor discloses wherein the OTS device is integrated in a metal stack of the HVC device ([col 10 lines 18-31], figure 3, the threshold switching material #38 represents the Ovonic Switching Device made of chalcogenide. The OTS #38 is seen integrated in a metal stack #42 and #34).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Park to include a threshold switching device in a metal stack as taught by Pryor in order to provide steep switching for high voltages and quick switch responses without degradation.
Regarding claim 19. Park as modified lacks wherein the OTS device is integrated in a metal stack of the HVC device.
Pryor discloses wherein the OTS device is integrated in a metal stack of the HVC device ([col 10 lines 18-31], figure 3, the threshold switching material #38 represents the Ovonic Switching Device made of chalcogenide. The OTS #38 is seen integrated in a metal stack #42 and #34).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Park to include a threshold switching device in a metal stack as taught by Pryor in order to provide steep switching for high voltages and quick switch responses without degradation.
Claims 5, 15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US-20190115079-A1) in view of Hong (US-10388561-B2).
Regarding claim 5. Park as modified lacks wherein the semiconductor device further comprises a first external pin and a second external pin.
Hong discloses wherein the semiconductor device further comprises a first external pin and a second external pin (figure 3, the semiconductor device is seen with a first external pin on top of electrode #1130 and a second external pin underneath of electrode #1110).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Park as modified to include a first and second external pin as taught by Hong in order to provide maximum usability of the semiconductor device with an increased manufacturing efficiency.
Regarding claim 15. Park as modified lacks wherein the semiconductor device further comprises a first external pin and a second external pin.
Hong discloses wherein the semiconductor device further comprises a first external pin and a second external pin (figure 3, the semiconductor device is seen with a first external pin on top of electrode #1130 and a second external pin underneath of electrode #1110).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Park as modified to include a first and second external pin as taught by Hong in order to provide maximum usability of the semiconductor device with an increased manufacturing efficiency.
Regarding claim 20. Park lacks wherein the semiconductor device further comprises a first external pin and a second external pin.
Hong discloses wherein the semiconductor device further comprises a first external pin and a second external pin (figure 3, the semiconductor device is seen with a first external pin on top of electrode #1130 and a second external pin underneath of electrode #1110).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Park to include a first and second external pin as taught by Hong in order to provide maximum usability of the semiconductor device with an increased manufacturing efficiency.
Claims 6, 7, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US-20190115079-A1) in view of Pryor (US-4845533-A) and Fukahori (US-20190123040-A1).
Regarding claim 6. Park lacks wherein the HVC device comprises:
at least one p-n-junction with a high breakdown voltage;
a first metallization layer;
a second metallization layer; and
wherein the OTS device is positioned between the first metallization layer and the second metallization layer the HVC device.
Pryor discloses wherein the HVC device comprises:
a first metallization layer ([col 12 line 67 – col 13 line 24], figure 3, the first metallization layer #34.1);
a second metallization layer ([col 12 line 67 – col 13 line 24], figure 3, the second metallization layer #42.1); and
wherein the OTS device is positioned between the first metallization layer and the second metallization layer the HVC device ([col 10 lines 18-31] and [col 12 line 67 – col 13 line 24], figure 3, the OTS device #38.1 is seen positioned in between the first metallization layer #34.1 and the second metallization layer #42.1. The OTS device #38.1 can be seen pointed at figure 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Park to include a first and second metallization layer with a OTS device in between as taught by Pryor in order to provide uniform electrical distribution for greater circuit response and also thermal management to increase the devices lifetime.
Park et al. as modified by Pryor et al. still lacks wherein the HVC device comprises:
at least one p-n-junction with a high breakdown voltage;
Fukahori discloses wherein the HVC device comprises:
at least one p-n-junction with a high breakdown voltage ([0046], figure 3(a), the p-n junction is seen as the p-type layers #41 and n-type layers #51 is seen in junction. It is noted that the electrode #61 represents the first metallization layer which is placed directly on top of p-type layer #41);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Park et al. as modified to include a p-n junction as taught by Fukahori in order to reduce current leakage within the circuitry and to provide additional voltage handling.
Regarding claim 7. Park lacks wherein the HVC device comprises: a first metallization layer, a second metallization layer, a third metallization layer and a fourth metallization layer;
wherein the OTS device comprises a first OTS layer and a second OTS layer;
wherein the first metallization layer is positioned on the top of a first p layer, the first OTS layer is positioned on the top of the first metallization layer, and the second metallization layer is positioned on the top of the first OTS layer, so that the first OTS layer is sandwiched between the first metallization layer and the second metallization layer; and
wherein the third metallization layer is positioned on the top of a second p layer, the second OTS layer is positioned on the top of the third metallization layer, and the fourth metallization layer is positioned on the top of the second OTS layer, so that the second OTS layer is sandwiched between the third metallization layer and the fourth metallization layer.
Pryor discloses wherein the HVC device comprises: a first metallization layer, a second metallization layer, a third metallization layer and a fourth metallization layer ([col 12 line 67 – col 13 line 24], figure 3, the figure depicts the first metallization layer #34.1, the second metallization layer #42.1, the third metallization layer #34.2, and the fourth metallization layer #42.2);
wherein the OTS device comprises a first OTS layer and a second OTS layer ([col 10 lines 18-31] and [col 12 line 67 – col 13 line 24], figure 3, the first OTS layer #38.1 and second OTS layer #38.2 is pointed in the figure. The OTS device #38.1 and #38.2 can be seen pointed at figure 2);
wherein the first OTS layer is positioned on the top of the first metallization layer, and the second metallization layer is positioned on the top of the first OTS layer, so that the first OTS layer is sandwiched between the first metallization layer and the second metallization layer ([col 12 line 67 – col 13 line 24], figure 3, the first OTS layer #38.1 can be seen on top of the first metallization layer #34.1 and underneath the second metallization layer #42.1. This makes the first OTS layer #38.1 being sandwiched by both metallization layers); and
wherein the second OTS layer is positioned on the top of the third metallization layer, and the fourth metallization layer is positioned on the top of the second OTS layer, so that the second OTS layer is sandwiched between the third metallization layer and the fourth metallization layer ([col 12 line 67 – col 13 line 24], figure 3, the second OTS layer #42.2 can be seen on top of the third metallization layer #34.2 and underneath the fourth metallization layer #42.2. This makes the second OTS layer #38.2 being sandwiched by both metallization layers).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Park to include four different metallization layers and two OTS layers as taught by Pryor in order to provide additional voltage handling in the device and to optimize the space provided within the circuitry for greater results.
Park et al. as modified by Pryor et al. still lacks wherein the first metallization layer is positioned on the top of a first p layer, and wherein the third metallization layer is positioned on the top of a second p layer.
Fukahori discloses wherein the first metallization layer is positioned on the top of a first p layer ([0046], figure 3(A), the first metallization layer #61 can be seen positioned on top of the first p layer #41), and wherein the third metallization layer is positioned on the top of a second p layer ([0046], figure 3(A), the third metallization layer #62 can be seen positioned on top of the second p layer #42).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Park et al. as modified to include the metallization layers to be disposed on the p layers as taught by Fukahori in order to reduce current leakage for both OTS devices and to improve symmetry and control within the device.
Regarding claim 16. Park lacks wherein the HVC device comprises:
at least one p-n-junction with a high breakdown voltage;
a first metallization layer;
a second metallization layer; and
wherein the OTS device is positioned between the first metallization layer and the second metallization layer the HVC device.
Pryor discloses wherein the HVC device comprises:
a first metallization layer ([col 12 line 67 – col 13 line 24], figure 3, the first metallization layer #34.1);
a second metallization layer ([col 12 line 67 – col 13 line 24], figure 3, the second metallization layer #42.1); and
wherein the OTS device is positioned between the first metallization layer and the second metallization layer the HVC device ([col 10 lines 18-31] and [col 12 line 67 – col 13 line 24], figure 3, the OTS device #38.1 is seen positioned in between the first metallization layer #34.1 and the second metallization layer #42.1. The OTS device #38.1 can be seen pointed at figure 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Park to include a first and second metallization layer with a OTS device in between as taught by Pryor in order to provide uniform electrical distribution for greater circuit response and also thermal management to increase the devices lifetime.
Park et al. as modified by Pryor et al. still lacks wherein the HVC device comprises:
at least one p-n-junction with a high breakdown voltage;
Fukahori discloses wherein the HVC device comprises:
at least one p-n-junction with a high breakdown voltage ([0046], figure 3(a), the p-n junction is seen as the p-type layers #41 and n-type layers #51 is seen in junction. It is noted that a the electrode #61 represents the first metallization layer which is placed directly on top of p-type layer #41);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Park et al. as modified to include a p-n junction as taught by Fukahori in order to reduce current leakage within the circuitry and to provide additional voltage handling.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Park (US-20190115079-A1) in view of Fukahori (US-20190123040-A1).
Regarding claim 8. Park lacks wherein the HVC device comprises:
two p-n-junctions, a first p-n junction and a second p-n junction, wherein the first p-n junction is realized by a first layer of a first polarity and a second layer of a second polarity, and wherein the second p-n junction is realized by the second layer and a third layer of the first polarity.
Fukahori discloses wherein the HVC device comprises:
two p-n-junctions, a first p-n junction and a second p-n junction, wherein the first p-n junction is realized by a first layer of a first polarity and a second layer of a second polarity, and wherein the second p-n junction is realized by the second layer and a third layer of the first polarity (figure 3(A), the first p-n junction is realized as the first layer #41 of a first polarity and the second layer #51 of a second polarity. The second p-n junction is realized as the second layer #51 and a third layer #42 of a first polarity).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Park et al. as modified to include a first and second p-n junction with three layers as taught by Fukahori in order for the device to handle greater voltages and to provide bidirectional control in both polarities.
Claims 9 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US-20190115079-A1).
Regarding claim 9. Park lacks wherein the OTS device is tuned so that the robustness of the OTS device mirrors the robustness of the HVC device.
MPEP 2144.05 IIB states that a particular parameter must first be recognized as a result effective variable, i.e., a variable which achieves a recognizable result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation. In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977).
It would have been obvious to one of ordinary skill in the art at the time of filing to have further modified for Park to include equal robustness for the OTS device and the HVC device as a result of routine experimentation as equal robustness would provide stable performance for the device’s lifetime by reducing the threshold drift and increasing the device’s reliability over time.
Regarding claim 17. Park lacks wherein the OTS device is tuned so that the robustness of the OTS device mirrors the robustness of the HVC device.
MPEP 2144.05 IIB states that a particular parameter must first be recognized as a result effective variable, i.e., a variable which achieves a recognizable result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation. In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977).
It would have been obvious to one of ordinary skill in the art at the time of filing to have further modified for Park to include equal robustness for the OTS device and the HVC device as a result of routine experimentation as equal robustness would provide stable performance for the devices lifetime by reducing the threshold drift and increasing the devices reliability over time.
Claims 10 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US-20190115079-A1) in view of Maxim et al. (US-20200274499-A1 referred as Maxim).
Regarding claims 10 and 18. Park lacks wherein the high voltage clamp within the HVC device is realized by a BJT device or a MOS device.
Maxim discloses wherein the high voltage clamp within the HVC device is realized by a BJT device or a MOS device ([0016], figure 1, the high voltage clamp within the HVC device #120 is realized by a MOS device as described).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Park to include the high voltage clamp within the HVC device to be realized by a MOS device as taught by Maxim in order to provide additional protection from transient voltages, allow an enhanced precision clamping, and for the MOS devices ease of integration.
Response to Amendment
Applicant's arguments filed 05/11/2026 have been fully considered but they are not persuasive.
It is noted that Applicant's arguments are related to the amended subject matter, simply stating the new amendments are not seen in the prior art. As is seen in the new rejection above, these amended features are disclosed by the prior art by Park et al.. All the arguments relating to limitations previously presented and rejected in the last arguments will be addressed below.
Regarding pages 8-14 relating to claim 1, the applicant argues about the HVC device and the OTS device connected in series not being present in Park et al. reference due to the disrupted connection in the circuitry. In this case, the examiner states that there is no difference on how the circuit handles the series connection since the beginning and ending nodes of which the HVC and OTS device is coupled to leads to the same path of the remaining circuitry. Therefore, there would be no disruption if additional elements are present in between the series connection since both the OTS device and the HVS device would still have a single shared amperage. Also, even if there was this disruption, as long as the prior art is connected in series at one point in different switching configurations, it would still read on the claimed limitation – at that point in time. If applicant wanted the elements interpreted as directly connected (touching) and in series, that would need to be claimed, as all elements that share the same current value are considered in series.
Additionally, the applicant argues about the HVC device and the OTS device configured for electrostatic discharge protection not being present in Park et al. reference due to the structural difference. The examiner states there is no structural difference in the Park et al. reference since both the HVC device and the OTS device are connected in series and thus would be able to provide the same electrostatic discharge protection as the current invention having one path to ground. If there is some additional structure in the present application that makes it applicable for electrostatic discharge, that should be claimed to distinguish from the prior art.
No dependent claims were separately argued, therefore, they remain rejected.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB R MARIN whose telephone number is (571)272-5887. The examiner can normally be reached Monday to Friday from 8:30am - 5:00pm ET.
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/JACOB RAUL MARIN/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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