DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The Office acknowledges the new title directed to interweaved fingers. The Office suggests including the phrase “resistance compensating interweaved electrode fingers” into the current title.
Prosecution Reopened Following Appeal Brief
In view of the Applicant’s Appeal Brief filed on 10/27/2025, PROSECUTION IS HEREBY REOPENED. The reasons for reopening being set forth below.
To avoid abandonment of the application, appellant must exercise one of the following two options:
(1) file a reply under 37 CFR 1.111 (if this Office action is non-final) or a reply under 37 CFR 1.113 (if this Office action is final); or,
(2) initiate a new appeal by filing a notice of appeal under 37 CFR 41.31 followed by an appeal brief under 37 CFR 41.37. The previously paid notice of appeal fee and appeal brief fee can be applied to the new appeal. If, however, the appeal fees set forth in 37 CFR 41.20 have been increased since they were previously paid, then appellant must pay the difference between the increased fees and the amount previously paid.
A Supervisory Patent Examiner (SPE) has approved of reopening prosecution by signing below:
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
Response to Appeal Brief
Applicant's arguments filed October 27, 2025 in the Appeal Brief have been fully considered but are (mostly) moot in light of the rejection below. In specific, the rejection below uses a new interpretation, briefly argued in the advisory action dated 8/7/2025, but not present in an official rejection.
Applicant notes on pgs. 13-14 of the above referenced Appeal Brief that the Examiner has not established a proper rationale regarding the proposed switching of a view of Efland fig. 5. Without acquiescing to the alleged reasonableness of the Applicant’s assertion, the rejection below is set forth.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-16 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. No. US 5468984 A to Efland et al. (hereinafter “Efland”) in view of U.S. Pat. Pub. No. US 20070181924 A1 to Baumgartner et al. (hereinafter “Baumgartner”).
Regarding claim 1, Efland teaches a semiconductor device comprising an interconnect (abstract) in fig. 5 (fig. 5 viewed from a reverse side, or viewed as if the structure is flipped over), wherein the interconnect (abstract) is arranged to transfer current from one terminal to another (col. 14 ln. 38-60), wherein the interconnect (abstract) comprises:
a first layer (elements 29, 25, 30, and 27 hereinafter “first layer”) (col. 7 ln. 26-37) comprising a plurality of interweaved fingers (30 and 25);
a second layer (elements 31, 34, 41, 35, 39, 36 and 33 hereinafter “second layer”) (col. 7 ln. 37-59), wherein the second layer (second layer) is arranged to compensate the difference of resistance in the first layer (col. 7 ln. 50-59).
Efland does not teach wherein each of the interweaved fingers (30 and 25) varies in width in a direction of propagation of current thereby resulting in a difference of resistance in each of the interweaved fingers (30 and 25) in the direction of propagation of current.
Baumgartner, however, teaches an integrated capacitor structure (abstract), in fig. 4, wherein each of the interweaved fingers (SE11, SE21, SE12, and SE22) [0023] varies in width in a direction of propagation of current (y axis) [0023] thereby resulting in a difference of resistance in each of the interweaved fingers (SE11, SE21, SE12, and SE22) in the direction of propagation of current (y axis).
It would have been obvious to a person of ordinary skill in the art (POSITA), before the effective filing date of the invention, to modify the interweaved fingers of Efland to comprise a varying width in the direction of current propagation to control the current density in the interweaved fingers as taught by Baumgartner in [0023]-[0024].
To further clarify, it is noted that Efland in view of Baumgartner does not explicitly teach that the second layer is arranged below the first layer, when using fig. 5. These layers, however, may be viewed from an opposite side when compared to the view presented in fig. 5 of Efland. There is no functionality of Efland which changes in doing this because Efland teaches an interconnection structure comprising, inter alia, circuit components such as an ESD circuit, Zener diodes, and diffusion regions (abstract). Such components are understood as being built on or in a carrier or substrate (see figs. 1-4, 11-14, & 16-18). The broadest reasonable interpretation of Efland thus allows for the structure to be viewed from a variety of angles. In specific, including an orientation where the second layer is arranged below the first layer. M.P.E.P. 2111.
Furthermore, the above interpretation is taken considering the level of skill of the person of ordinary skill in the art, this skill level certainly allowing for a structure like Efland in view of Baumgartner to be viewed opposite to the view of Efland fig. 5 (i.e., flipped over) before or after the structure is built in or on a package. This interpretation is considered in light M.P.E.P. 2111 wherein is taught that the broadest reasonable interpretation does not mean the broadest possible interpretation. Accordingly, the Examiner believes that the above interpretation does not approach such a pseudo limit of reasonableness (i.e., the interpretation above is reasonable, not only possible) considering the combination of each of Efland and Baumgartner as a whole.
Regarding claim 2, Efland in view of Baumgartner teaches a semiconductor device according to claim 1. Efland further teaches, in fig. 5, wherein the second layer (second layer) comprises a plurality of strips (elements 34, 41, 35, 39, and 36) arranged perpendicular to the direction of propagation of current, wherein the strips (elements 34, 41, 35, 39, and 36) compensate the resistance difference in the first layer (first layer) (col. 7 ln. 50-59).
Efland does not teach wherein the width of the strips (elements 34, 41, 35, 39, and 36) varies.
Baumgartner, however, teaches an integrate capacitor structure (abstract), in fig. 4, wherein each of the interweaved fingers (SE11, SE21, SE12, and SE22) [0023] varies in width [0023].
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the interweaved fingers of Efland to comprise a varying width to control the current density in the interweaved fingers as taught by Baumgartner in [0023]-[0024].
Regarding claim 3, Efland in view of Baumgartner teaches a semiconductor device according to claim 1. Efland is silent in teaching a semiconductor device, in fig. 5, wherein the second layer (second layer) has a physical parameter (col. 7 ln. 50-59) that is varied in the direction of propagation of current to compensate the resistance difference in the first layer (col. 7 ln. 50-59). Efland appears to teach a consistent physical parameter in fig. 5 to compensate the resistance difference in the first layer as taught in (col. 7 ln. 50-59).
Baumgartner, however, teaches an integrate capacitor structure (abstract), in fig. 4, wherein each of the interweaved fingers (SE11, SE21, SE12, and SE22) [0023] varies in width i.e., a physical parameter [0023].
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the interweaved fingers of Efland to comprise a varying width in the direction of the propagation of current to control the current density in the interweaved fingers as taught by Baumgartner in [0023]-[0024].
Regarding claim 4, Efland in view of Baumgartner teaches a semiconductor device according to claim 1. Efland further teaches, in fig. 5, wherein both the first layer (first layer) and the second layer (second layer) are metallic (col. 3 ln. 23-44).
Regarding claim 5, Efland in view of Baumgartner teaches a semiconductor device according to claim 1. Efland does not teach, in fig. 5, wherein the plurality of interweaved fingers (30 and 25) in the first layer (first layer) has a pyramidal shape.
Baumgartner, however, teaches an integrate capacitor structure (abstract), in fig. 4, wherein each of the interweaved fingers (SE11, SE21, SE12, and SE22) [0023] has a pyramidal shape [0023].
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the interweaved fingers of Efland to comprise a pyramidal shape to control the current density in the interweaved fingers as taught by Baumgartner in [0023]-[0024].
Regarding claim 6, Efland in view of Baumgartner teaches a semiconductor device according to claim 1. Efland further teaches, in fig. 5, wherein the semiconductor device is selected from the group consisting of: an ESD diode (col. 3 ln. 23-25), a TVS diode, and a lateral MOSFET.
Regarding claim 7, Efland in view of Baumgartner teaches a semiconductor device according to claim 2. Efland is silent in teaching, in fig. 5, wherein the second layer (second layer) has a physical parameter that is varied in the direction of propagation of current to compensate the resistance difference in the first layer (first layer).
Baumgartner, however, teaches an integrate capacitor structure (abstract), in fig. 4, wherein each of the interweaved fingers (SE11, SE21, SE12, and SE22) [0023] varies in width i.e., a physical parameter [0023].
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the second layer of Efland to comprise a varying width in the direction of the propagation of current to control the current density in the second layer as taught by Baumgartner in [0023]-[0024].
Regarding claim 8, Efland in view of Baumgartner teaches a semiconductor device according to claim 2. Efland further teaches, in fig. 5, wherein both the first layer (first layer) and the second layer (second layer) are metallic (col. 3 ln. 23-44).
Regarding claim 9, Efland in view of Baumgartner teaches a semiconductor device according to claim 2. Efland does not teach, in fig. 5, wherein the plurality of interweaved fingers (30 and 25) in the first layer (first layer) has a pyramidal shape.
Baumgartner, however, teaches an integrate capacitor structure (abstract), in fig. 4, wherein each of the interweaved fingers (SE11, SE21, SE12, and SE22) [0023] has a pyramidal shape [0023].
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the interweaved fingers of Efland to comprise a pyramidal shape to control the current density in the interweaved fingers as taught by Baumgartner in [0023]-[0024].
Regarding claim 10, Efland in view of Baumgartner teaches a semiconductor device according to claim 2. Efland further teaches, in fig. 5, wherein the semiconductor device is selected from the group consisting of: an ESD diode (col. 3 ln. 23-25), a TVS diode, and a lateral MOSFET.
Regarding claim 11, Efland in view of Baumgartner teaches a semiconductor device according to claim 3. Efland further teaches, in fig. 5, wherein both the first layer (first layer) and the second layer (second layer) are metallic (col. 3 ln. 23-44).
Regarding claim 12, Efland in view of Baumgartner teaches a semiconductor device according to claim 3. Efland does not teach, in fig. 5, wherein the plurality of interweaved fingers (30 and 25) in the first layer (first layer) has a pyramidal shape.
Baumgartner, however, teaches an integrate capacitor structure (abstract), in fig. 4, wherein each of the interweaved fingers (SE11, SE21, SE12, and SE22) [0023] has a pyramidal shape [0023].
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the interweaved fingers of Efland to comprise a pyramidal shape to control the current density in the interweaved fingers as taught by Baumgartner in [0023]-[0024].
Regarding claim 13, Efland in view of Baumgartner teaches a semiconductor device according to claim 3. Efland further teaches, in fig. 5, wherein the semiconductor device is selected from the group consisting of: an ESD diode (col. 3 ln. 23-25), a TVS diode, and a lateral MOSFET.
Regarding claim 14, Efland in view of Baumgartner teaches a semiconductor device according to claim 4. Efland further teaches, in fig. 5, wherein the plurality of interweaved fingers (30 and 25) in the first layer (first layer) has a pyramidal shape.
Baumgartner, however, teaches an integrate capacitor structure (abstract), in fig. 4, wherein each of the interweaved fingers (SE11, SE21, SE12, and SE22) [0023] has a pyramidal shape [0023].
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the interweaved fingers of Efland to comprise a pyramidal shape to control the current density in the interweaved fingers as taught by Baumgartner in [0023]-[0024].
Regarding claim 15, Efland in view of Baumgartner teaches a semiconductor device according to claim 4. Efland further teaches, in fig. 5, wherein the semiconductor device is selected from the group consisting of: an ESD diode (col. 3 ln. 23-25), a TVS diode, and a lateral MOSFET.
Regarding claim 16, Efland in view of Baumgartner teaches a semiconductor device according to claim 5. Efland further teaches, in fig. 5, wherein the semiconductor device is selected from the group consisting of: an ESD diode (col. 3 ln. 23-25), a TVS diode, and a lateral MOSFET.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN EDWARD CUTLER whose telephone number is (703)756-5415. The examiner can normally be reached Monday-Friday 7:30 am - 5:00 pm Eastern Time.
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/ETHAN EDWARD CUTLER/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892