Prosecution Insights
Last updated: September 25, 2026
Application No. 18/147,957

A MULTI-LAYER SEMICONDUCTOR DEVICE INTERCONNECT INCLUDING INTERWEAVED FINGERS

Final Rejection §103§112
Filed
Dec 29, 2022
Priority
Dec 31, 2021 — EU 21218440.2
Examiner
CUTLER, ETHAN EDWARD
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Nexperia B.V.
OA Round
4 (Final)
92%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
55 granted / 60 resolved
+23.7% vs TC avg
Moderate +12% lift
Without
With
+11.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
20 currently pending
Career history
82
Total Applications
across all art units

Statute-Specific Performance

§103
65.2%
+25.2% vs TC avg
§102
25.8%
-14.2% vs TC avg
§112
9.1%
-30.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 60 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The Office acknowledges the new title directed to interweaved fingers. The Office suggests including the phrase “resistance compensating interweaved electrode fingers” into the current title. Drawings Figures 1-4 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 1 recites “the second layer comprising the plurality of interweaved fingers and a semiconductor layer.” This phrase is not supported by the specification i.e., the semiconductor layer being disposed in the second layer is not supported. Correction is required. Claims 2-16 depend from claim 1 and are rejected for the same reasons above. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-16 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation “the second layer comprising the plurality of interweaved fingers” in ln. 9. There is insufficient antecedent basis for this limitation in the claim. In specific, there seems to be incorrect antecedent basis drawn from the plurality of interweaved fingers of the first layer. Claim 1, as amended, requires that the plurality of interweaved fingers of the first layer be disposed in the first layer and the second layer, which is mutually exclusive, i.e., a recited structure cannot be in two places at once. In the interest of compact prosecution, it is interpreted that the plurality of interweaved fingers allegedly of the second layer is “an additional plurality of interweaved fingers.” Claims 2-16 depend from claim 1 and are rejected for the same reasons above. Response to Arguments Applicant's arguments filed 4/28/2026 have been fully considered but are not persuasive. The Applicant argues that the interpretation taken by the office is “completely divorced” from the specification. However, this cannot be true, as the Office supplies a rejection with citations to the specification, which further includes an interpretation of how these references read on the claim based on the specification itself. The evidence is presented in a clear manner in keeping with required regulatory practices. The Applicant further argues that the Office advances a “complete redesign” of Efland’s device. Such a statement is not true, however, as viewing the Efland device from a different viewpoint is hardly a redesign. The Applicant argues that the limitation of resistance compensation has not been met. However, due to the Applicant’s amendments, it is suggested that a uniform current of the device results in resistance compensation (see amended claim 1 and compare to Efland col. 3 ln. 50-55). Because of this requirement made by the Applicant in claim 1, it is understood that a uniform current requires resistance compensation to achieve this result. The Applicant argues that claim 2 has no reason for combination. This is not true, however, as the reason for combination is that the current density is controlled as taught by Baumgartner [0023]-[0024]. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-16 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. No. US 5468984 A to Efland et al. (hereinafter “Efland”) in view of U.S. Pat. Pub. No. US 20160268386 A1 to Prechtl (hereinafter “Prechtl”) and further in view of U.S. Pat. Pub. No. US 20070181924 A1 to Baumgartner et al. (hereinafter “Baumgartner”). Regarding claim 1, Efland teaches a semiconductor device comprising an interconnect (abstract) in fig. 5 (fig. 5 viewed from a reverse side, or viewed as if the structure is flipped over), wherein the interconnect (abstract) is arranged to transfer current from one terminal to another (col. 14 ln. 38-60), wherein the interconnect (abstract) comprises: a first layer (elements 29, 25, 30, and 27 hereinafter “first layer”) (col. 7 ln. 26-37) comprising a plurality of interweaved fingers (30 and 25); a second layer (elements 31, 34, 41, 35, 39, 36 and 33 hereinafter “second layer”) (col. 7 ln. 37-59), and disposed in between (being disposed in a space separating parts of the first layer) the first layer (first layer), the second layer (second layer) comprising an additional plurality of interweaved fingers (fingers of material of structures 34 and 35), wherein the second layer (second layer) is arranged to compensate the difference of resistance and achieve a uniform distribution of current (uniform current switching; col. 3 ln. 50-55) in the first layer (col. 7 ln. 50-59) so that all current paths in the first layer have the same resistance (see below for rational). Efland, does not teach a second layer comprising a semiconductor layer. Prechtl, however, teaches wherein the second layer (lower layer 25; fig. 1) [0040] comprises a semiconductor layer (substrate 5; fig. 1) [0038] It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Efland fig. 5 to include a semiconductor substrate to insulate the structure as taught by Prechtl [0038]. Efland in view of Prechtl does not teach wherein each of the interweaved fingers (30 and 25) varies in width in a direction of propagation of current thereby resulting in a difference of resistance in each of the interweaved fingers (30 and 25) in the direction of propagation of current. Baumgartner, however, teaches an integrated capacitor structure (abstract), in fig. 4, wherein each of the interweaved fingers (SE11, SE21, SE12, and SE22) [0023] varies in width in a direction of propagation of current (y axis) [0023] thereby resulting in a difference of resistance in each of the interweaved fingers (SE11, SE21, SE12, and SE22) in the direction of propagation of current (y axis). It would have been obvious to a person of ordinary skill in the art (POSITA), before the effective filing date of the invention, to modify the interweaved fingers of Efland to comprise a varying width in the direction of current propagation to control the current density in the interweaved fingers as taught by Baumgartner in [0023]-[0024]. To further clarify, it is noted that Efland in view of Baumgartner and Prechtl does not explicitly teach that the second layer is arranged below the first layer, when using fig. 5. These layers, however, may be viewed from an opposite side when compared to the view presented in fig. 5 of Efland. There is no functionality of Efland which changes in doing this because Efland teaches an interconnection structure comprising, inter alia, circuit components such as an ESD circuit, Zener diodes, and diffusion regions (abstract). Such components are understood as being built on or in a carrier or substrate (see figs. 1-4, 11-14, & 16-18). The broadest reasonable interpretation of Efland thus allows for the structure to be viewed from a variety of angles. In specific, including an orientation where the second layer is arranged below the first layer. M.P.E.P. 2111. Furthermore, the above interpretation is taken considering the level of skill of the person of ordinary skill in the art, this skill level certainly allowing for a structure like Efland in view of Baumgartner to be viewed opposite to the view of Efland fig. 5 (i.e., flipped over) before or after the structure is built in or on a package. This interpretation is considered in light M.P.E.P. 2111 wherein is taught that the broadest reasonable interpretation does not mean the broadest possible interpretation. Accordingly, the Examiner believes that the above interpretation does not approach such a pseudo limit of reasonableness (i.e., the interpretation above is reasonable, not only possible) considering the combination of each of Efland, Baumgartner, and Prechtl as a whole. Regarding the resistance limitations of claim 1, it is understood that the structure of claim 1 requires that the resistance of the first layer will be uniform if the current is uniform. Because of this, Efland reads on this portion of claim 1 because Efland achieves uniform current switching (col. 3 ln. 50-55). This interpretation holds when considering general properties of resistance and current i.e., current is limited by resistance, i.e., resistance is the opposition to the flow of current. Therefore, a uniform current in the device must necessarily mean a same resistance as defined by claim 1. Regarding claim 2, Efland in view of Baumgartner and Prechtl teaches a semiconductor device according to claim 1. Efland further teaches, in fig. 5, wherein the second layer (second layer) comprises a plurality of strips (elements 34, 41, 35, 39, and 36) arranged perpendicular to the direction of propagation of current, wherein the strips (elements 34, 41, 35, 39, and 36) compensate the resistance difference in the first layer (first layer) (col. 7 ln. 50-59). Efland does not teach wherein the width of the strips (elements 34, 41, 35, 39, and 36) varies. Baumgartner, however, teaches an integrate capacitor structure (abstract), in fig. 4, wherein each of the interweaved fingers (SE11, SE21, SE12, and SE22) [0023] varies in width [0023]. It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the interweaved fingers of Efland to comprise a varying width to control the current density in the interweaved fingers as taught by Baumgartner in [0023]-[0024]. Regarding claim 3, Efland in view of Baumgartner and Prechtl teaches a semiconductor device according to claim 1. Efland is silent in teaching a semiconductor device, in fig. 5, wherein the second layer (second layer) has a physical parameter (col. 7 ln. 50-59) that is varied in the direction of propagation of current to compensate the resistance difference in the first layer (col. 7 ln. 50-59). Efland appears to teach a consistent physical parameter in fig. 5 to compensate the resistance difference in the first layer as taught in (col. 7 ln. 50-59). Baumgartner, however, teaches an integrate capacitor structure (abstract), in fig. 4, wherein each of the interweaved fingers (SE11, SE21, SE12, and SE22) [0023] varies in width i.e., a physical parameter [0023]. It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the interweaved fingers of Efland to comprise a varying width in the direction of the propagation of current to control the current density in the interweaved fingers as taught by Baumgartner in [0023]-[0024]. Regarding claim 4, Efland in view of Baumgartner and Prechtl teaches a semiconductor device according to claim 1. Efland further teaches, in fig. 5, wherein both the first layer (first layer) and the second layer (second layer) are metallic (col. 3 ln. 23-44). Regarding claim 5, Efland in view of Baumgartner and Prechtl teaches a semiconductor device according to claim 1. Efland does not teach, in fig. 5, wherein the plurality of interweaved fingers (30 and 25) in the first layer (first layer) has a pyramidal shape. Baumgartner, however, teaches an integrate capacitor structure (abstract), in fig. 4, wherein each of the interweaved fingers (SE11, SE21, SE12, and SE22) [0023] has a pyramidal shape [0023]. It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the interweaved fingers of Efland to comprise a pyramidal shape to control the current density in the interweaved fingers as taught by Baumgartner in [0023]-[0024]. Regarding claim 6, Efland in view of Baumgartner and Prechtl teaches a semiconductor device according to claim 1. Efland further teaches, in fig. 5, wherein the semiconductor device is selected from the group consisting of: an ESD diode (col. 3 ln. 23-25), a TVS diode, and a lateral MOSFET. Regarding claim 7, Efland in view of Baumgartner and Prechtl teaches a semiconductor device according to claim 2. Efland is silent in teaching, in fig. 5, wherein the second layer (second layer) has a physical parameter that is varied in the direction of propagation of current to compensate the resistance difference in the first layer (first layer). Baumgartner, however, teaches an integrate capacitor structure (abstract), in fig. 4, wherein each of the interweaved fingers (SE11, SE21, SE12, and SE22) [0023] varies in width i.e., a physical parameter [0023]. It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the second layer of Efland to comprise a varying width in the direction of the propagation of current to control the current density in the second layer as taught by Baumgartner in [0023]-[0024]. Regarding claim 8, Efland in view of Baumgartner and Prechtl teaches a semiconductor device according to claim 2. Efland further teaches, in fig. 5, wherein both the first layer (first layer) and the second layer (second layer) are metallic (col. 3 ln. 23-44). Regarding claim 9, Efland in view of Baumgartner and Prechtl teaches a semiconductor device according to claim 2. Efland does not teach, in fig. 5, wherein the plurality of interweaved fingers (30 and 25) in the first layer (first layer) has a pyramidal shape. Baumgartner, however, teaches an integrate capacitor structure (abstract), in fig. 4, wherein each of the interweaved fingers (SE11, SE21, SE12, and SE22) [0023] has a pyramidal shape [0023]. It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the interweaved fingers of Efland to comprise a pyramidal shape to control the current density in the interweaved fingers as taught by Baumgartner in [0023]-[0024]. Regarding claim 10, Efland in view of Baumgartner and Prechtl teaches a semiconductor device according to claim 2. Efland further teaches, in fig. 5, wherein the semiconductor device is selected from the group consisting of: an ESD diode (col. 3 ln. 23-25), a TVS diode, and a lateral MOSFET. Regarding claim 11, Efland in view of Baumgartner and Prechtl teaches a semiconductor device according to claim 3. Efland further teaches, in fig. 5, wherein both the first layer (first layer) and the second layer (second layer) are metallic (col. 3 ln. 23-44). Regarding claim 12, Efland in view of Baumgartner and Prechtl teaches a semiconductor device according to claim 3. Efland does not teach, in fig. 5, wherein the plurality of interweaved fingers (30 and 25) in the first layer (first layer) has a pyramidal shape. Baumgartner, however, teaches an integrate capacitor structure (abstract), in fig. 4, wherein each of the interweaved fingers (SE11, SE21, SE12, and SE22) [0023] has a pyramidal shape [0023]. It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the interweaved fingers of Efland to comprise a pyramidal shape to control the current density in the interweaved fingers as taught by Baumgartner in [0023]-[0024]. Regarding claim 13, Efland in view of Baumgartner and Prechtl teaches a semiconductor device according to claim 3. Efland further teaches, in fig. 5, wherein the semiconductor device is selected from the group consisting of: an ESD diode (col. 3 ln. 23-25), a TVS diode, and a lateral MOSFET. Regarding claim 14, Efland in view of Baumgartner and Prechtl teaches a semiconductor device according to claim 4. Efland further teaches, in fig. 5, wherein the plurality of interweaved fingers (30 and 25) in the first layer (first layer) has a pyramidal shape. Baumgartner, however, teaches an integrate capacitor structure (abstract), in fig. 4, wherein each of the interweaved fingers (SE11, SE21, SE12, and SE22) [0023] has a pyramidal shape [0023]. It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the interweaved fingers of Efland to comprise a pyramidal shape to control the current density in the interweaved fingers as taught by Baumgartner in [0023]-[0024]. Regarding claim 15, Efland in view of Baumgartner and Prechtl teaches a semiconductor device according to claim 4. Efland further teaches, in fig. 5, wherein the semiconductor device is selected from the group consisting of: an ESD diode (col. 3 ln. 23-25), a TVS diode, and a lateral MOSFET. Regarding claim 16, Efland in view of Baumgartner and Prechtl teaches a semiconductor device according to claim 5. Efland further teaches, in fig. 5, wherein the semiconductor device is selected from the group consisting of: an ESD diode (col. 3 ln. 23-25), a TVS diode, and a lateral MOSFET. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN EDWARD CUTLER whose telephone number is (703)756-5415. The examiner can normally be reached Monday-Friday 7:30 am - 5:00 pm Eastern Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached on (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ETHAN EDWARD CUTLER/Examiner, Art Unit 2892 /NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
Read full office action

Prosecution Timeline

Show 3 earlier events
May 23, 2025
Final Rejection mailed — §103, §112
Jul 24, 2025
Response after Non-Final Action
Aug 25, 2025
Notice of Allowance
Oct 27, 2025
Response after Non-Final Action
Nov 09, 2025
Response after Non-Final Action
Feb 04, 2026
Non-Final Rejection mailed — §103, §112
Apr 28, 2026
Response Filed
Aug 25, 2026
Final Rejection mailed — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12745412
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
3y 8m to grant Granted Sep 22, 2026
Patent 12740086
FET DEVICE WITH AIGaN BUFFER LAYER AND THIN InGaN LAYER
3y 10m to grant Granted Sep 15, 2026
Patent 12733314
OPTOELECTRONIC SEMICONDUCTOR ELEMENT WITH CRACK NUCLEI AND METHOD FOR OPERATING AN OPTOELECTRONIC SEMICONDUCTOR ELEMENT WITH CRACK NUCLEI
4y 2m to grant Granted Sep 08, 2026
Patent 12733276
IMAGE SENSING DEVICE INCLUDING GRID STRUCTURE WITH AIR LAYER
4y 3m to grant Granted Sep 08, 2026
Patent 12733231
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
3y 7m to grant Granted Sep 08, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

5-6
Expected OA Rounds
92%
Grant Probability
99%
With Interview (+11.9%)
3y 5m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 60 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month