DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a Final office action based on application 18/147,999 in response to reply filed October 9, 2025. Claims 1-2 & 4-19 are currently pending and have been considered below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4, 6-8, 10, 11, & 18-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Salman (Pre-Grant Publication 2015/0187752).
Regarding claim 1, Salman discloses a ESD protection device comprising:
a semiconductor die (Fig. 5, 210) having an electronic component (121) integrated thereon, wherein the electronic component comprises regions in the semiconductor die, the regions comprising: a first region (122; Paragraph 0020]) of a first charge type configured to be electrically connected to a first device terminal (Fig. 3a, IN);
a second region (125;Paragraph [0020]) of a second charge type arranged adjacent to and forming a first PN junction with the first region;
a third region (124) of the first charge type arranged adjacent to and forming a second PN junction with the second region, the third region being spaced apart from the first region by the second region and being configured to be electrically connected to a second device terminal (Vss);
a fourth region (212) of the first charge type arranged adjacent to and forming a third PN junction with the second region, the fourth region being spaced apart from the first region and third region by the second region; and
a plurality of further regions comprising a first further region (130; Paragraph [0039]) of the first charge type;
a second further region (125) of the second charge type arranged adjacent to and forming a first further PN junction with the first further region, the second further region being configured to be electrically connected to the first device terminal (IN) via a conductive material such as (306/310);
a third further region (132; Paragraph [0039]) of the first charge type;
a fourth further region (125) of the second charge type arranged adjacent to and forming a second further PN junction with the third further region, the fourth further region being configured to be electrically connected to the second device terminal (Vss) via a conductive material such as (306/310);
wherein the first further region and the second further region are comprised in the semiconductor die or in a first further semiconductor die, and wherein the third further region and the fourth further region are comprised in the semiconductor die, the first further semiconductor die or a second further semiconductor die (Fig. 5); and
wherein the semiconductor device further comprises an electronic unit (130/132) configured to be electrically connected between the first device terminal (Fig. 3a), the second device terminal and the fourth region, wherein during operation, the electronic unit is configured to provide a first current path or a second current path in dependence of a polarity of a voltage across the first device terminal and the second device terminal (Paragraph [0025]).
wherein the first current path extends through the first further region and the second further region, and wherein the second current path extends through the third further region and the fourth further region (Fig. 3a).
Regarding claim 2, Salman further discloses:
the first charge type corresponds to an n-type doping, and wherein the first current path and the second current path extend from the first device terminal and the second device terminal, respectively, towards the fourth region (Paragraph [0020]).
Regarding claim 4 & 8, Salman further discloses:
the first region, the second region and the third region together form a bipolar junction transistor (BJT) (Paragraph [0020]).
Regarding claim 6, Salman further discloses:
the regions corresponding to the electronic component; and/or wherein the further regions corresponding to the electronic unit are ion-implanted regions (Paragraph [0030, 0038, 0039]).
Regarding claim 7, Salman further discloses:
the electronic unit comprises further regions comprised in the semiconductor die or one or more further semiconductor dies on which the electronic unit is integrated, the further regions comprising:
wherein the first current path extends through the first further region and the second further region, and wherein the second current path extends through the third further region and the fourth further region (Fig. 3a).
Regarding claim 10, Salman further discloses:
Silicide is formed on exposed silicon regions in which the regions (122, 124, 125, 212) are formed, therefore the substrate/semiconductor die (210) is formed of silicon (Paragraph [0041] & [0007]).
Regarding claim 11, Salman further discloses:
the first further region (130) and the third further region (132) are each electrically connected to the fourth region (212); wherein the first further region and the second further region together form a first diode (130), and wherein the third further region and the fourth further region together form a second diode (132).
Regarding claim 18, Salman further discloses:
protection device configured to be electrically connected to an electronic circuit (200/202) and to protect the electronic circuit from ESD events;
wherein the ESD protection device comprises one or more semiconductor devices as defined in claim 1; and wherein the ESD protection device is a packaged device (Fig. 5).
Regarding claim 19, Salman further discloses:
an electronic circuit integrated on a semiconductor die, and one or more semiconductor devices as defined in claim 1, wherein the one or more semiconductor devices are integrated on the semiconductor die and are electrically connected to the electronic circuit (200/202) to protect the electronic circuit from ESD events; and wherein the device is a packaged device (Fig. 5).
Allowable Subject Matter
Claims 5, 9, & 12-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 5 is considered allowable because none of the prior art either alone or in combination discloses wherein the second region comprises a first sub-region and a second sub- region, the first sub-region being relatively lowly doped with respect to the second sub-region, wherein the first region and the third region are arranged adjacent to the first sub-region and are spaced apart from the second sub- region by the first sub-region, and wherein the fourth region is arranged adjacent to the second sub-region and is spaced apart from the first sub- region by the second sub-region; and/or wherein the single further region comprises a first further sub-region and a second further sub-region, the first further sub-region being relatively lowly doped with respect to the second further sub-region, wherein the second further region and the third further region are arranged adjacent to the first further sub-region and are spaced apart from the second further sub-region by the first further sub-region, and wherein the fifth further region is arranged adjacent to the second further sub-region and is spaced apart from the first further sub-region by the second further sub- region.
Claim 9 is considered allowable because none of the prior art either alone or in combination discloses wherein the second region comprises a first sub-region and a second sub- region, the first sub-region being relatively lowly doped with respect to the second sub-region, wherein the first region and the third region are arranged adjacent to the first sub-region and are spaced apart from the second sub- region by the first sub-region, and wherein the fourth region is arranged adjacent to the second sub-region and is spaced apart from the first sub- region by the second sub-region and/or wherein the single further region comprises the first further sub-region and the second further sub-region, the first further sub-region being relatively lowly doped with respect to the second further sub-region, wherein the second further region and the third further region are arranged adjacent to the first further sub-region and are spaced apart from the second further sub-region by the first further sub-region, and wherein the fifth further region is arranged adjacent to the second further sub-region and is spaced apart from the first further sub-region by the second further sub-region.
Claim 12 is considered allowable because none of the prior art either alone or in combination discloses wherein the first through fourth further regions are all comprised in the semiconductor die or on the first further semiconductor die, and wherein the first further region and the third further region are adjacently arranged and form a single further region. Claims 13-17 are also allowed based on their dependency from claim 12.
Response to Arguments
Applicant's arguments filed September 4, 2025 have been fully considered but they are not persuasive. Applicant argument that Salman base region 125 does not establish an electrical connection to plug/interconnect (306/310) is not considered persuasive because the doped semiconductor regions (125, 122, 124, 132, 130) are themselves conductive materials and establish an electrical path to operate as the electronic component/transistor (121) and electronic unit/diodes (130 & 132). Therefore the regions of semiconductor regions of Salman are electrically connected to the first and second terminals via conductive materials.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON C FOX whose telephone number is (571)270-5016. The examiner can normally be reached M-F 9:00AM-6:00PM.
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/BRANDON C FOX/Examiner, Art Unit 2818
/DAVID VU/Primary Examiner, Art Unit 2818