Prosecution Insights
Last updated: October 02, 2026
Application No. 18/148,148

METHODS AND APPARATUS TO REDUCE SOLDER BUMP BRIDGING BETWEEN TWO SUBSTRATES

Non-Final OA §102§103
Filed
Dec 29, 2022
Examiner
BARZYKIN, VICTOR V
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
391 granted / 475 resolved
+14.3% vs TC avg
Minimal +4% lift
Without
With
+3.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
17 currently pending
Career history
502
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
50.2%
+10.2% vs TC avg
§102
25.0%
-15.0% vs TC avg
§112
19.5%
-20.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 475 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention I, claims 1-19 in the reply filed on 05/28/2026 is acknowledged. Claims 20-23 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 05/28/2026. Drawings The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: 112. Furthermore, the reference sign 104 points to both an array of bumps or balls and to a space near the die 108. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3, 6-7,14-15, 17, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et. al., U.S. Pat. Pub. 2021/0118803, hereafter Park. PNG media_image1.png 398 656 media_image1.png Greyscale Regarding claim 1, Park discloses (Figs. 1-5, see annotated Fig. 5 above) an apparatus comprising: a first substrate [100] including a first bump and a second bump spaced apart from the first bump, the first bump including a first base, the second bump including a second base; and a second substrate [210] including a third bump and a fourth bump spaced apart from the third bump, the third bump including a third base, the fourth bump including a fourth base, the first base electrically coupled to the third base by first solder, the second base electrically coupled to the fourth base by second solder, the first base having a first height [PH1] and the second base having a second height [PH2], the first height greater than the second height (par. [0051], [0066]) Regarding claim 2, Park further discloses (par. [0051]) wherein at least one of the first base, the second base, the third base, or the fourth base includes copper. Regarding claim 3, Park further discloses (annotated Fig. 5, par. [0058]) wherein at least one of the first solder [248-2] or the second solder [248-1] includes tin. Regarding claim 6, Park further discloses (Fig. 1, the first and second plurality of bumps are distributed over the entire chip/substrate area and are intermixed with one another) wherein the first substrate includes a first plurality of bumps and a second plurality of bumps, the first plurality of bumps including the first bump, the second plurality of bumps including the second bump, the first plurality of bumps having bases with the first height, the second plurality of bumps having bases with the second height, the first plurality of bumps distributed across a first area of the first substrate, the second plurality of bumps distributed across a second area of the first substrate, the second area overlapping the first area. Regarding claim 7, Park further discloses (Fig. 1) wherein the first bump is spaced apart from the second bump by a first distance, the first plurality of bumps including a fifth bump spaced apart from the first bump by a second distance, the second distance greater than the first distance (the bumps are intermixed over the same area and alternating, as seen in Fig. 1, so there is a fifth bump spaced apart from the first bump by a second distance, the second distance greater than the first distance)+. Regarding claim 14, Park discloses (Fig. 9, see also annotated version below) an apparatus comprising: a first substrate including first contacts [132], [132]+[242]; and a second substrate including second contacts[231], [231]+[242] the first and second substrates corresponding to different ones of a semiconductor die [200] (par. [0022]) and a package substrate [600] (par. [0022]) supporting the semiconductor die [200], the first contacts including first surfaces (top surfaces) to face towards the second contacts, the second contacts including second surfaces (bottom surfaces) to face towards the first contacts, the second contacts electrically coupled to respective ones of the first contacts by solder [248] disposed-between corresponding pairs of the first and second surfaces, a first one of the first surfaces being closer to the second substrate than a second one of the first surfaces is to the second substrate (see Fig. 9, closer by pillar thickness [242]). PNG media_image2.png 610 564 media_image2.png Greyscale Regarding claim 15, Park further discloses wherein the first contacts include bases (pads [132] or pads [132]+ pillars [242]) defining the first surfaces, a first one of the bases (pad [132]+ pillar [242]) protruding farther from a solder resist layer (par. [0084], solder resist layer (not illustrated on top of substrate body [610]) of the first substrate than a second one of the bases (just the pad [132]) protrudes from the solder resist layer. Regarding claim 17, Park further discloses (see annotated Fig. 9 above) wherein ones of a first plurality of the first surfaces (top surfaces of pads [132] + pillar [242]) are closer to the second substrate than ones of a second plurality (top surfaces of just the pads [132] of the first surfaces are to the second substrate, first ones of the first contacts associated with the first plurality being interspersed between second ones of the second contacts associated with the second plurality (see Fig. 9, the contacts are interspersed and alternate). Regarding claim 19, Park further discloses (annotated Fig. 9 above) wherein the first contacts include bases [130],[131], [140], [612] extending through openings in a solder resist layer of the first substrate (on top of [600], par. [0084], pads [612] are exposed through the solder resist layer), distal faces of the bases corresponding to the first surfaces of the first contacts, a first one of the bases extending farther through a corresponding first one of the openings than a second one of the bases extends through a corresponding second one of the openings (by the pillar thickness [242]). Claims 1-4 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lai et. al., U.S. Pat. 9,515,039, hereafter Lai. Regarding claim 1, Lai discloses (Fig. 3) an apparatus comprising: a first substrate [20] including a first bump [22] and a second bump [21] spaced apart from the first bump, the first bump including a first base [220], the second bump [21] including a second base [210]; and a second substrate [3] including a third bump [30] and a fourth bump [30] spaced apart from the third bump, the third bump including a third base [20], the fourth bump including a fourth base [30], the first base electrically coupled to the third base by first solder [221’], the second base electrically coupled to the fourth base by second solder [211’, the first base having a first height and the second base having a second height, the first height greater than the second height (Col. 4, lines 6-19). Regarding claim 2, Lai further discloses (Col. 3, line 66 – Col. 4, line 5) wherein at least one of the first base, the second base, the third base, or the fourth base includes copper. Regarding claim 3, Lai further discloses (Col. 3, line 66 – Col. 4, line 5) wherein at least one of the first solder or the second solder includes tin. Regarding claim 4, Lai further discloses (Fig. 3, Col. 5, lines 1-10) wherein the first solder [221’] has a first volume and the second solder [211’] has a second volume, the first volume less than the second volume. Regarding claim 11, Lai further discloses (Fig. 3, Col. 5, lines 1-10) wherein the first solder [221’] extends a first distance between the first bump [220] and the third bump [30], and the second solder [211’] extends a second distance between the second bump [210] and the fourth bump [30], the first distance less than the second distance (see Fig. 3, Col. 5, lines 1-10). Claims 1-3 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et. al., U.S. Pat. 9,679,862, hereafter Lin Regarding claim 1, Lin discloses (Fig. 4A) an apparatus comprising: a first substrate [102] including a first bump [114],[103c] and a second bump [113],[103p] spaced apart from the first bump, the first bump including a first base [103c], the second bump including a second base[103p]; and a second substrate [101] including a third bump [104] and a fourth bump [104] spaced apart from the third bump, the third bump including a third base [104], the fourth bump including a fourth base [104] (the base of the bump, which is a bond pad [104], is the bond pad [104] itself), the first base electrically coupled to the third base by first solder [107], the second base electrically coupled to the fourth base by second solder [107], the first base [103c] having a first height [Dc] and the second base having a second height [Dp], the first height greater than the second height (Col. 6, lines 27-30). Regarding claim 2, Lin further discloses (Claims 4,5) wherein at least one of the first base, the second base, the third base, or the fourth base includes copper. Regarding claim 3, Lin further discloses (Col. 3, lines 28-29) wherein at least one of the first solder or the second solder includes tin. Regarding claim 5, Lin further discloses (Fig. 4A) wherein the third base [104] has a third height and the fourth base [104] has a fourth height, the third height greater than the fourth height (Col. 6, lines 41-64). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Park et. al., U.S. Pat. Pub. 2021/0118803, hereafter Park. Regarding claim 13, Park discloses everything as applied above. Park further discloses (par. [0051]) the first height in a range of 5 to 13 um and (par. [0066]) the second height in a range of 1 to 3 um. Thus, Park discloses a height difference in a range of 2 to 12 um. It would have been obvious to one of ordinary skill in the art to arrive to the limitation of claim 13, “wherein a height difference between the first height and the second height is at least 10 microns”, because the range of Park overlaps the instant range of claim 13. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990) (MPEP, Latest Edition, 2144.05.I, and case law therein). Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Park et. al., U.S. Pat. Pub. 2021/0118803, hereafter Park, in view of Higashiguchi et. al., U.S. Pat. 5,828,128, hereafter Higashiguchi. Regarding claim 8, Park discloses everything as applied above. Park fails to explicitly disclose wherein the first area is smaller than the second area, and the first area is entirely contained within the second area. However, Higashiguchi discloses (Figs 3,4) wherein the first area is smaller than the second area, and the first area is entirely contained within the second area (the area where lower bumps [22], [23] are distributed overlaps the area where higher bumps [21] are distributed, one can choose the first area to be a circumferential including the bumps [21], the second area the entire surface area of the chip, so the limitation is satisfied). It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to modify bump height distribution of Park with the teachings of Higashiguchi because Higashiguchi teaches (Col. 2, lines 23-27) that such a modification simplifies inspection, so that the state of the BGA array can be easily checked by visual inspection. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Park et. al., U.S. Pat. Pub. 2021/0118803, hereafter Park, in view of Yu et. al., U.S. Pat. Pub. 2018/0233474, hereafter Yu. Regarding claim 9, Park discloses everything as applied above. Park fails to explicitly disclose wherein the first base has a first cross-sectional profile shape, and the second base has a second cross-sectional profile shape different than the first cross-sectional profile shape. However, Yu discloses (Figs 4A-4E, par. [0033]) wherein the first base has a first cross-sectional profile shape, and the second base has a second cross-sectional profile shape different than the first cross-sectional profile shape (Yu discloses that cross-sectional profiles can have different shapes shown in Figs 4A-4E). It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to modify pillar cross-sectional shapes of Park to ones taught by Yu. It would have been obvious to one of ordinary skill in the art to modify pillars and pads of Park with the teachings of Yu, because Yu teaches (par. [0034]) “when the resulting semiconductor package is bonded to a substrate, the second metal pad of the UBM stack may have improved mechanical strength (thick thickness and a larger diameter than the diameter of the conductive plug) to reduce the stress on the extra-low-k (ELK) dielectric layers of the semiconductor die. Therefore, the problem of cracks forming in the ELK dielectric layers can be avoided”. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Park et. al., U.S. Pat. Pub. 2021/0118803, hereafter Park, in view of Lai et. al., U.S. Pat. 9,515,039, hereafter Lai. Regarding claim 16, Park discloses everything as applied above. Park further discloses (solder has volume) wherein the solder electrically coupled to the first one of the first surfaces has a first volume, and the solder electrically coupled to the second one of the first surfaces has a second volume. Park fails to explicitly disclose the second volume being greater than the first volume. However, Lai Fig. 4, Col. 5, lines 26-34) discloses the second volume [40] being greater than the first volume [40’]. It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to modify the volume of solder for a connection of different size pillars because Lai teaches (Col. 5, lines 35-40) that this will meet coplanarity requirement when the pillars have a different width. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR V BARZYKIN whose telephone number is (571)272-0508. The examiner can normally be reached Monday-Friday, 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VICTOR V BARZYKIN/Examiner, Art Unit 2893 /Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Dec 29, 2022
Application Filed
Jul 14, 2023
Response after Non-Final Action
Aug 24, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
86%
With Interview (+3.7%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 475 resolved cases by this examiner. Grant probability derived from career allowance rate.

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