Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
FINAL OFFICE ACTION
This Office Action addresses U.S. Patent Application No. 18/148,230, entitled “MULTI-PHASE CLOCKING SCHEME FOR A MEMORY DEVICE”, filed December 29, 2022.
Claims 1-20 are pending.
REQUIREMENT FOR INFORMATION UNDER 37 CFR 1.105
The requirement for information is maintained and repeated from the previous Office action:
37 CFR 1.105(a)(1) states:
In the course of examining or treating a matter in a pending or abandoned application … the examiner or other Office employee may require the submission, from individuals identified under § 1.56(c), or any assignee, of such information as may be reasonably necessary to properly examine or treat the matter.
37 CFR 1.63(c) states:
A person may not execute an oath or declaration for an application unless that person has reviewed and understands the contents of the application, including the claims, and is aware of the duty to disclose to the Office all information known to the person to be material to patentability as defined in § 1.56.
(1) In the Declaration submitted August 24, 2023, applicant acknowledged, under oath, the duty to disclose to the Patent and Trademark Office all information known to be material to patentability of the subject matter claimed in this application, as “materiality” is defined in Title 37, Code of Federal Regulations, § 1.56.
(2) On January 30, 2026 a search of the prior art revealed several relevant patents and published patent applications by those having a duty to disclose under 37 CFR § 1.56 (each inventor named in the application; each attorney or agent who prepares or prosecutes the application; and every other person who is substantively involved in the preparation or prosecution of the application and who is associated with the inventor, the applicant, an assignee, or anyone to whom there is an obligation to assign the application).
Some examples of such prior art relevant to the present claims are:
U.S. Patent No. 8,619,931: “The resulting current clock signal (CURCLK) 110 output by the PI 104 may include four phases at the frequency of the multi-phase clock signal 64”
EP 1753143 A2: “One of the purposes of the multi-phase recovered clock outputs of CDR 20 is to provide multiple versions of a half-rate clock signal” and “The multi-phase recovered clock signals output by CDR circuitry 20 are also applied to local clock generator circuitry 110.”
U.S. Patent Application Pub. No. 20220200781: “The ones described herein are: and (1) Very wide frequency range (one-octave) quadrature clock generator i.e. generating 4-phases (e.g., 0, 90, 180 and 270 degrees) from two input phases (0 and 180 degrees), and (2) Very wide frequency range quadrature oscillator (direct 4-phase generation). They both function using the same underlying principal which is detailed herein. The clock buffer can also be used in other situations such as clock distribution network.”
U.S. Patent No. 9,252,743: “In one embodiment, an apparatus includes a clock generator to generate differential clock signals. The apparatus also includes a distributed polyphase filter to obtain phase-corrected multi-phase clock signals based on the differential clock signals.”
U.S. Patent No. 9,013,213: “The fractional frequency divider can use a multi-phase input to perform fractional division. FIG. 1A illustrates a 4-phase input clock signal P1-P4.”
U.S. Patent No. 8,194,811: “Multi-phase reference clock signals, such as four-phase reference clocks, are used in many processing systems”.
U.S. Patent No. 6,633,190: “The multi-phase clock generator 300 also includes a clock divider 370 that simply divides the reference, or input, clock by eight. Alternate implementations need not divide the reference clock or may divide it by any other suitable number.”
U.S. Patent Application Pub. No. 20220303034: “Circuits using the clock signal for synchronization may become active at either the rising edge, falling edge, or, in the case of double data rate, both in the rising and in the falling edges of the clock cycle.”
This list is not exhaustive.
Applicants have not satisfied the duty to disclose all information known to be material to patentability of the subject matter claimed in this application.
Related applications or publications by the applicant (inventors and/or assignee) suggest that applicant likely has access to information necessary to a more complete understanding of the invention and its context than has been disclosed. The record suggests that the details of such information may be relevant to the issue of patentability, and thus shows the need for information. See MPEP 704.11.
Applicant and the assignee of this application are required under 37 CFR 1.105 to provide the following information that the examiner has determined is reasonably necessary to the examination of this application.
The information is required to enter in the record the art suggested by the applicant as relevant to this examination, narrowed to the scope of technologies that generate, based on a first clock signal having a first frequency, multi-phase clock signals for a memory device having a second frequency, wherein the second frequency is a fraction of the first frequency and generate local clock signals for data channels of the memory device based on the multi-phase clock signals, wherein the local clock signals are synchronous with respective rising edges of the multi-phase clock signals.
(1) In response to this requirement, please provide copies of each publication which any of the inventors authored or co-authored and/or which was owned by the assignee and which describe the disclosed subject matter, narrowed to the scope of technologies that generate, based on a first clock signal having a first frequency, multi-phase clock signals for a memory device having a second frequency, wherein the second frequency is a fraction of the first frequency and generate local clock signals for data channels of the memory device based on the multi-phase clock signals, wherein the local clock signals are synchronous with respective rising edges of the multi-phase clock signals.
(2) In response to this requirement, please provide the title, citation and copy of each publication that is a source used for the description of the prior art in the disclosure, narrowed to “technologies that generate, based on a first clock signal having a first frequency, multi-phase clock signals for a memory device having a second frequency, wherein the second frequency is a fraction of the first frequency and generate local clock signals for data channels of the memory device based on the multi-phase clock signals, wherein the local clock signals are synchronous with respective rising edges of the multi-phase clock signals.” For each publication, please provide a concise explanation of that publication’s contribution to the description of the prior art.
(3) In response to this requirement, please provide the title, citation and copy of each publication that any of the inventors relied upon to develop and/or draft the disclosed subject matter that describes the invention, particularly as to technologies that generate, based on a first clock signal having a first frequency, multi-phase clock signals for a memory device having a second frequency, wherein the second frequency is a fraction of the first frequency and generate local clock signals for data channels of the memory device based on the multi-phase clock signals, wherein the local clock signals are synchronous with respective rising edges of the multi-phase clock signals.
For each publication, please provide a concise explanation of the reliance placed on that publication in the development of the disclosed subject matter.
(4) As demonstrated above, applicant’s own patents and publications appear to teach critical limitations of the present claims. In response to this requirement, please state the specific improvements of the subject matter in claims 1-20 over the disclosed prior art and indicate the specific elements in the claimed subject matter that provide those improvements.
The timing fee and certification requirements of 37 CFR 1.97 are waived for those documents submitted in reply to the requirement. This waiver extends only to those documents within the scope of this requirement under 37 CFR 1.105 that are included in the applicant’s first complete communication responding to this requirement. Any supplemental replies subsequent to the first communication responding to this requirement and any information disclosures beyond the scope of this requirement under 37 CFR 1.105 are subject to the fee and certification requirements of 37 CFR 1.97 where appropriate.
The applicant is reminded that the reply to this requirement must be made with candor and good faith under 37 CFR 1.56. Where the applicant does not have or cannot readily obtain an item of required information, a statement that the item is unknown or cannot be readily obtained may be accepted as a complete reply to the requirement for that item.
This requirement is an attachment of the following Office action. A complete reply to the Office action must include a complete reply to this requirement. The time period for reply to this requirement coincides with the time period for reply to the enclosed Office action.
A reply, or a failure to reply, to a requirement for information under 37 CFR 1.105(a)(1) will be governed by §§ 1.135 and 1.136.
RESPONSE TO REQUEST FOR INFORMATION
Applicant's response to the requirement for information under 37 CFR 1.105(a)(1) is incomplete. The reply filed on May 1, 2026 is not fully responsive to the prior Office action because of the following omission(s) or matter(s):
Applicant’s remarks filed with the amendment of May 1, 2026 address only requirement (4) of the request for information and only with respect to the prior art by those having a duty to disclose under 37 CFR § 1.56 that was listed in the Office action mailed February 4, 2026. Page 7 of the remarks state:
“Each of these patents or patent applications discloses generating a clock signal based on a reference clock, without further teaching or suggesting ‘generat[ing] local clock signals [that] are synchronous with respective rising edges of the multi-phase clock signals; and provid[ing] output data … based on the local clock signals’ as recited in independent claim 1 as amended.”
A complete reply is necessary since there may be other patents or publications by those having a duty to disclose under 37 CFR § 1.56 that do include “generat[ing] local clock signals [that] are synchronous with respective rising edges of the multi-phase clock signals; and provid[ing] output data … based on the local clock signals”, such as U.S. Patent No. 9,941,898 or U.S. Patent Application Publication No. 2022/0303034.
An incomplete reply to a 37 CFR 1.105 requirement in a pending application or reexamination proceeding is normally handled in the same manner as an amendment not fully responsive to a non-final Office action. See 37 CFR 1.135(c) and MPEP § 714.03. See 37 CFR 1.111.
However, since applicant has (a) made a bona fide attempt to address the other issues from the previous office action (drawings, specification, claims), (b) arranged a telephone interview to discuss the requirement for information, and (c) stated, “The Applicant's attorney will work with the Applicant to find whether there is any additional ‘information known to be material to patentability of the subject matter claimed in this application’ in compliance with the requirement for information under 37 CFR 1.105”, applicant will be given the opportunity to include the response to the requirement for information in the time period normally set forth for a response to a final rejection.
DRAWING OBJECTIONS
The previous objections to the drawings are withdrawn due to the corrected drawing sheets filed on May 1, 2026.
SPECIFICATION
The previous objection to the disclosure is withdrawn due to the amendment to the specification filed on May 1, 2026.
CLAIM OBJECTIONS
The previous objections to the claims are withdrawn due to the amendment filed on May 1, 2026.
CLAIM INTERPRETATION
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
An application may include one or more claim limitations that use the words “means for” and also limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) use(s) a generic placeholder.
Three Prong Analysis
To invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, a claimed phrase must meet the three prong analysis as set forth in MPEP § 2181, subsection I.
(A) Regarding Prong (A), the MPEP states:
the claim limitation uses the term "means" or "step" or a term used as a substitute for "means" that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function....
The claim limitations listed below do not use the language "means" or "step". However, each of these may be found to be a generic placeholder.
logic
memory controller
memory devices
Thus, these limitations meet Prong (A) of the analysis.
(B) Regarding Prong (B), the MPEP states:
the term "means" or "step" or the generic placeholder is modified by
functional language, typically, but not always linked by the transition word "for" (e.g., "means for") or another linking word or phrase, such as "configured to" or "so that"...
The claim limitations listed below may be modified by functional language, as shown.
logic (“configured to”)
memory controller (not modified by functional language)
memory devices (not modified by functional language)
Any limitations which have been marked “not modified by functional language” do not meet Prong (B) and will not be further considered in this analysis. All other limitations meet Prong (B) of the analysis and must be considered in the following step.
(C) Regarding Prong (C), the MPEP states:
the term "means" or "step" or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
With regard to where the limitations may be found in the disclosure:
logic (note “Some or all components or features of in the memory clocking system 200 (including, e.g., the clock divider/controller 220, the clock trees 230, and/or the local clock generators 240) can be implemented using a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), other hardware logic (e.g., logic circuitry), via a controller with software or firmware, and/or in a combination of a controller with software/firmware and logic, an FPGA or ASIC. More particularly, components of the memory clocking system 200 can be implemented in one or more modules as a set of program or logic instructions stored in a machine- or computer-readable storage medium such as random access memory (RAM), read only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., in hardware, or any combination thereof”, ¶ [0025]).
Thus, the logic could be hardware logic circuitry or it could be a set of instructions, for which sufficient structure is not shown, thus meeting Prong (C) of the analysis and thus 35 U.S.C. § 112, 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph is invoked.
CLAIM REJECTIONS - 35 USC § 112, 1st PARAGRAPH
The previous rejections of the claims under 35 U.S.C. 112(a) are withdrawn due to the arguments and corresponding citations to the disclosure presented with the amendment filed on May 1, 2026.
New rejections are under 35 U.S.C. 112(a) are required due to the amendment filed on May 1, 2026:
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
(1) Regarding claims 1-15, these are directed to logic “configured” to generate multi-phase signals for a memory device, generate local clock signals for data channels of the memory device and provide output data for the data channels of the memory device.
Note, “Some or all components or features of in the memory clocking system 200 (including, e.g., the clock divider/controller 220, the clock trees 230, and/or the local clock generators 240) can be implemented using a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), other hardware logic (e.g., logic circuitry), via a controller with software or firmware, and/or in a combination of a controller with software/firmware and logic, an FPGA or ASIC. More particularly, components of the memory clocking system 200 can be implemented in one or more modules as a set of program or logic instructions stored in a machine- or computer-readable storage medium such as random access memory (RAM), read only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., in hardware, or any combination thereof”, ¶ [0025]. There is no clear enablement for the claimed logic.
(2) Regarding claims 16-20, the steps of generating multi-phase clock signals for a memory device, generating local clock signals for data channels of the memory device and providing output data for data channels of the memory device do not explicitly mention “logic”, but must inevitably rely on ¶ [0025] of the disclosure. Thus, there is no clear enablement for the steps of claims 16-20.
CLAIM REJECTIONS - 35 USC § 112(b)
The previous rejections of claims 1-19 under 35 U.S.C. 112(b) are withdrawn due to the amendment filed on May 1, 2026.
The following rejection is maintained from the previous Office action:
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude
with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 20, “wherein the output data is clocked out at an effective rate equal to the first frequency based on the local clock signals” is unclear. Claim 16 requires that the first frequency is that of a first clock signal, not the local clock signals. Or perhaps this is meant to be worded as “wherein the output data is clocked out based on the local clock signals, at an effective rate equal to the first frequency”.
CLAIM REJECTIONS - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-15 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because, as explained above, the claimed “logic” may be merely a set of instructions, which does not fall within at least one of the four categories of patent eligible subject matter recited in 35 U.S.C. 101 (process, machine, manufacture, or composition of matter), i.e., the claim(s) is/are directed to mere instructions in the form of data. See MPEP § 2106.03.
PRIOR ART
Any rejections based on prior art (e.g., nonstatutory double patenting, 35 U.S.C. §102 or 35 U.S.C. §103) will be held in abeyance until applicant has satisfied the requirements for information under 37 CFR 1.105 set forth above and clarified the inventive concept to distinguish the invention from prior art systems that utilized multi-phase clock signals to access memory.
RESPONSE TO AMENDMENT
For the reasons set forth above, several of the objections and rejections have been withdrawn due to the amendment of May 1, 2026, some rejections have been maintained, and new rejections have been introduced in response to the amendment.
CONCLUSION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to B. James Peikari at telephone number (571) 272-4185. The examiner can normally be reached M-F 8:30am - 5:30pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Kosowski can be reached at (571) 272-3744. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B. James Peikari/
Primary Examiner, Art Unit 3992
Prosecution Insights