DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to applicant’s Election/Restriction filed on 03/31/2026.
Currently claims 1-14 and 21-26 are pending in the application.
Election/Restrictions
Applicant's election without traverse of Group I, claims 1-14, in the reply filed on 03/31/2026 is acknowledged. The examiner accepted the new claims 21-26 for prosecution.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/12/2023 was filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement was considered by the examiner.
Claim Rejections - 35 USC § 112 (b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 11-13 are rejected under 35 U.S.C. 112 (b), as being indefinite for failing to particularly pointing out and distinctly claim the subject matter which the inventor or a joint inventor, regard as their invention.
Regarding claim 11, the instant claim recites limitation in view of claim 9, where claim 11 recites “a roughened surface" (claim 11, line 2). There is insufficient antecedent basis for this limitation in the claim. It is unclear whether the first “one roughened surface” (claim 9, line 3) is being recalled or a new “roughened surface” is being introduced, rendering the claim indefinite. Clarification and/or correction are/is required. For the purpose of examination, the claim will be interpreted as “the roughened surface”.
Claims 12-13 are also rejected due to their dependence on a rejected base claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0284637 A1 (Ma) and further in view of US 2022/0102259 A1 (Kong).
Regarding claim 1, Ma discloses, an integrated circuit package substrate comprising:
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a core layer (150; core; Fig. 1E; [0035]) comprising Silicon and Oxygen (SiO2; [0029]), and
a plurality of metal vias (160; conductor; Fig. 1E; [0036]) in holes (165) of the core layer (150), the metal vias (160) electrically connecting a top side (152) of the core layer (150) and a bottom side (154) of the core layer (150) (Fig. 1C and 1E; [0036]); and
a plurality of build-up layers (130 and 140; first and second build-up layers; Fig. 1E; [0040]) on the core layer (150), the build-up layers (130 and 140) comprising interconnect structures (139a/b/c and 149a/b/c; vias; Fig. 1E; [0043] – [0045]) electrically connected to the metal vias (160) in the core layer (150).
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Ma further teaches, in a slightly different embodiment of Fig. 1F, at least one surface (on the surface of the hole 160 in core 150; Fig. 1F; [0051]) of the core layer (150) having a wetting layer 170 (Fig. 1F; [0051]);
But Ma fails to teach explicitly, at least one surface of the core layer having a roughened surface;
However, in analogous art, Kong discloses, one surface (213/214; top roughened surfaces; Fig. 2B; [0050]) of the core layer (traces 206 and 207) having a roughened surface;
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ma and Kong before him/her, to modify the teachings of a package substrate as taught by Ma and to include the teachings of one surface of the core layer having a roughened surface as taught by Kong since the roughened surface improves the adhesiveness of conductive materials to the core and absent this important teaching in Ma, a person with ordinary skill in the art would be motivated to reach out to Kong while forming a package substrate of Ma.
Regarding claim 2, the combination of Ma and Kong discloses, the integrated circuit package substrate of claim 1, wherein the roughened surface has an average roughness above 100nm ([0056]; Kong Ref.; Kong teaches roughness of > 200nm).
Regarding claim 7, the combination of Ma and Kong discloses, the integrated circuit package substrate of claim 1, wherein surfaces of the holes in the core layer are roughened (Fig. 1F; Ma’s wetting layer 170 can be a roughened layer as modified by Kong).
Regarding claim 8, the combination of Ma and Kong discloses, the integrated circuit package substrate of claim 1, wherein an outer edge (as annotated on Fig. 2B) of the top surface of the core layer (206/207; Fig. 2B; [0050]; Kong Ref.) is roughened.
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Claims 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Ma and Kong as applied to claim 1 and further in view of US 2020/0075470 A1 (Kuo).
Regarding claim 3, the combination of Ma and Kong fails to teach explicitly, the integrated circuit package substrate of claim 1, wherein a first portion of the top surface of the core layer has a roughened surface, and a second portion of the top surface is smooth.
However, in analogous art, Kuo discloses, the integrated circuit package substrate of claim 1, wherein a first portion of the top surface of the core layer has a roughened surface, and a second portion of the top surface is smooth (Fig. 7; [0103]). Kuo teaches that the top of the center portion of the lining layer LL below the metal feature MF has a smooth surface, while the top of the protruding edge portion of the lining layer LL outside of the metal feature MF has a rough and uneven surface.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ma, Kong and Kuo before him/her, to modify the teachings of a package substrate as taught by Ma and to include the teachings of top surface of the core layer having both roughened and smooth surfaces as taught by Kuo since in MPEP 2143 (I) (A), it is stated that Combining prior art elements according to known methods to yield predictable results is obvious. Absent this important teaching in Ma, a person with ordinary skill in the art would be motivated to reach out to Kuo while forming a package substrate of Ma.
Regarding claim 4, the combination of Ma, Kong and Kuo discloses, the integrated circuit package substrate of claim 3, wherein surfaces of the core layer in contact with the metal vias are smooth ([0103]; Kuo Ref.).
Regarding claim 5, the combination of Ma, Kong and Kuo fails to teach explicitly, the integrated circuit package substrate of claim 3, wherein surfaces of the core layer in contact with the metal vias are roughened.
However, in MPEP 2143 (I) (E), it is stated that it is "Obvious to try" – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success is obvious. In this instant case, the top surface of the core layer could be either smooth or roughened. Therefore, choosing surfaces of the core layer in contact with the metal vias being roughened is well within the purview of a person with ordinary skill in the art. Besides, since the applicant used both smooth and roughened surface in contact with the metal vias, therefore, using one over the other is not critical. Therefore, it can be considered that the limitation is taught by the prior art Kuo.
Regarding claim 6, Ma discloses, the integrated circuit package substrate of claim 5, wherein one or more surfaces of the core layer (150) not in contact with the metal interconnect structures are smooth (as annotated on Fig. 1E).
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Claims 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0284637 A1 (Ma) and further in view of US 2022/0102259 A1 (Kong).
Regarding claim 9, Ma discloses, a system comprising:
a package substrate comprising:
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a glass layer (150; core; Fig. 1E; [0035]); and
Ma further teaches, in a slightly different embodiment of Fig. 1F, at least one surface (on the surface of the hole 160 in core 150; Fig. 1F; [0051]) of the core layer (150) having a wetting layer 170 (Fig. 1F; [0051]);
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an integrated circuit die (210; integrated circuit die; Fig. 2; [0052]) coupled to the package substrate (100).
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But Ma fails to teach explicitly, the glass layer having at least one roughened surface with an average roughness above 100nm; a metal in contact with the roughened surface of the glass layer; and
However, in analogous art, Kong discloses, the glass layer (traces 206 and 207) having at least one roughened surface (213/214; top roughened surfaces; Fig. 2B; [0050]) with an average roughness above 100nm ([0056]; Kong teaches roughness of > 200nm);
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a metal (metal material of via 219; via; Fig. 2E; [0054]) in contact with the roughened surface (213/214) of the glass layer (206/207); and
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ma and Kong before him/her, to modify the teachings of a package substrate as taught by Ma and to include the teachings of one surface of the core layer having a roughened surface as taught by Kong since the roughened surface improves the adhesiveness of conductive materials to the core and absent this important teaching in Ma, a person with ordinary skill in the art would be motivated to reach out to Kong while forming a package substrate of Ma.
Regarding claim 10, the combination of Ma and Kong discloses, the system of claim 9, wherein an outer edge (as annotated on Fig. 2B) of a top surface or bottom surface (top surface) of the glass layer (206/207; Fig. 2B; [0050]) has a roughened surface (Kong Ref.).
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Regarding claim 11, the combination of Ma and Kong discloses, the system of claim 9, wherein the package substrate comprises a metal via (219) in the glass layer (206/207) and the metal via (219) is in contact with a roughened surface (213/214) of the glass layer (206/207) (Fig. 2E; [0054]; Kong Ref.).
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Regarding claim 12, the combination of Ma and Kong discloses, the system of claim 11, wherein the roughened surface (213/214) of the glass layer (206/207) in contact with the metal via (219) is a top surface of the glass layer (Fig. 2E; [0054]; Kong Ref.).
Regarding claim 13, the combination of Ma and Kong discloses, the system of claim 11, wherein the roughened surface (Fig. 1F; Ma’s wetting layer 170 can be a roughened layer as modified by Kong) of the glass layer (150) in contact with the metal via (160) is a surface inside a hole (165) of the glass layer (150) in which the metal via (160) is disposed (Fig. 1C and 1E; [0036]; Ma Ref.).
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Regarding claim 14, the combination of Ma and Kong fails to teach explicitly, the system of claim 9, wherein the package substrate comprises a metal via in the glass layer and the metal via is in contact with a smooth surface of the glass layer.
However, in MPEP 2143 (I) (E), it is stated that it is "Obvious to try" – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success is obvious. In this instant case, the top surface of the glass layer could be either smooth or roughened. Therefore, choosing the metal via is in contact with a smooth surface of the glass layer is well within the purview of a person with ordinary skill in the art. Therefore, it can be considered that the limitation is taught by the prior art Ma.
Claims 21-23 and 25-26 are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0284637 A1 (Ma) and further in view of US 2022/0102259 A1 (Kong).
Regarding claim 21, Ma discloses, the integrated circuit device assembly comprising:
a package substrate comprising:
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a glass core layer (150; core; Fig. 1E; [0035]);
build-up layers (130 and 140; first and second build-up layers; Fig. 1E; [0040]) on the glass core layer (150); and
metal interconnect structures (as annotated on Fig. 1E) in contact with the glass core layer (150);
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Ma further teaches, in a slightly different embodiment of Fig. 1F, at least one surface (on the surface of the hole 160 in core 150; Fig. 1F; [0051]) of the core layer (150) having a wetting layer 170 (Fig. 1F; [0051]);
But Ma fails to teach explicitly, wherein one or more surfaces of the glass core layer in contact with the metal interconnect structures are roughened with an average roughness above 100nm;
However, in analogous art, Kong discloses, wherein one or more surfaces (213/214; top roughened surfaces; Fig. 2B; [0050]) of the glass core layer (traces 206 and 207) in contact with the metal interconnect structures (metal material of via 219; via; Fig. 2E; [0054]) are roughened with an average roughness above 100nm ([0056]; Kong teaches roughness of > 200nm);
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ma and Kong before him/her, to modify the teachings of a package substrate as taught by Ma and to include the teachings of one surface of the core layer having a roughened surface as taught by Kong since the roughened surface improves the adhesiveness of conductive materials to the core and absent this important teaching in Ma, a person with ordinary skill in the art would be motivated to reach out to Kong while forming a package substrate of Ma.
Regarding claim 22, Ma discloses, the integrated circuit device assembly of claim 21, wherein the metal interconnect structures include metal vias (165) in the core layer (150).
Regarding claim 23, Ma discloses, the integrated circuit device assembly of claim 21, wherein the metal interconnect structures include metal traces (as evident in Fig. 1E) on the core layer (150).
Regarding claim 25, the combination of Ma and Kong discloses, the integrated circuit device assembly of claim 21, wherein an outer edge (as annotated on Fig. 2B) of the top surface of the core layer (206/207; Fig. 2B; [0050]; Kong Ref.) is roughened.
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Regarding claim 26, Ma discloses, the integrated circuit device assembly of claim 21, wherein one or more surfaces of the core layer (150) not in contact with the metal interconnect structures are smooth (as annotated on Fig. 1E).
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Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Ma and Kong as applied to claim 21 and further in view of US 2020/0075470 A1 (Kuo).
Regarding claim 24, the combination of Ma and Kong fails to teach explicitly, the integrated circuit device assembly of claim 21, wherein a first portion of a top surface of the core layer has a roughened surface, and a second portion of the top surface is smooth.
However, in analogous art, Kuo discloses, the integrated circuit package substrate of claim 21, wherein a first portion of the top surface of the core layer has a roughened surface, and a second portion of the top surface is smooth (Fig. 7; [0103]). Kuo teaches that the top of the center portion of the lining layer LL below the metal feature MF has a smooth surface, while the top of the protruding edge portion of the lining layer LL outside of the metal feature MF has a rough and uneven surface.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ma, Kong and Kuo before him/her, to modify the teachings of a package substrate as taught by Ma and to include the teachings of top surface of the core layer having both roughened and smooth surfaces as taught by Kuo since in MPEP 2143 (I) (A), it is stated that Combining prior art elements according to known methods to yield predictable results is obvious. Absent this important teaching in Ma, a person with ordinary skill in the art would be motivated to reach out to Kuo while forming a package substrate of Ma.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2021/0257309 A1 (Pietambaram) - Structures are disclosed that include multi-layered adhesion promotion films over a conductive structure in a microelectronic package. The multi-layered aspect provides adhesion to surrounding dielectric material without a roughened surface of the conductive structure. Furthermore, the multi-layered aspect allows for materials with different dielectric constants to be used, the average of which can provide a closer match to the dielectric constant of the surrounding dielectric material. According to an embodiment, a first dielectric layer that includes at least one nitride material can provide good adhesion with the underlying conductive structure, while one or more subsequent dielectric layers that include at least one oxide material can provide different dielectric constant values (e.g., typically lower) compared to the first dielectric layer to bring the overall dielectric constant closer to that of a surrounding dielectric material. The first and second layers may be discrete layers or a single continuous layer with grading.
US 2021/0193544 A1 (Lin) - Three-dimensional integrated circuit (3DIC) structures are disclosed. A 3DIC structure includes a semiconductor package, a first package substrate, a molded underfill layer and a thermal interface material. The semiconductor package is disposed over and electrically connected to the first package substrate through a plurality of first bumps. The semiconductor package includes at least one semiconductor die and an encapsulation layer aside the semiconductor die. The molded underfill layer surrounds the plurality of first bumps and a sidewall of the semiconductor package, and has a substantially planar top surface. The CTE of the molded underfill layer is different from the CTE of the encapsulation layer of the semiconductor package. The thermal interface material is disposed over the semiconductor package.
US 2020/0058567 A1 (Kim) - An integrated circuit package is disclosed. The package includes a substrate having a glass core layer, where the glass core layer includes a first major surface, a second major surface, and a cavity disposed between the first major surface and the second major surface of the glass core layer. The package also includes a die disposed in the cavity of the glass core layer, an encapsulant disposed in the cavity between the die and a sidewall of the cavity, a first patterned conductive layer disposed adjacent the first major surface of the glass core layer, and a second patterned conductive layer disposed adjacent the second major surface of the glass core layer. The die is electrically connected to at least one of the first and second patterned conductive layers.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
04/15/2026
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