DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8, 16, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dede et al (US Publication 20180025962).
Regarding claim 1, Dede teaches A semiconductor structure, comprising:
a substrate (Fig. 1, 110) having a front substrate surface (Fig. 1, 116);
a channel enclosed within the substrate for a fluid to flow through (Fig. 1 and 4, 150 enclosed within 110 and 146, para 27), the channel comprises:
a first channel portion having a first volume (Fig. 4, left most channel 160 by outlet channel 154);
a second channel portion having a second volume (Fig. 4, right most channel 160 by inlet channel 152); and
a third channel portion laterally connecting the first channel portion to the second channel portion (Fig. 4 center most channel 160 connected from the sides not pictured to other 160s), the third channel portion having a third volume smaller than the first volume and the second volume (channel sections near in/outlet have higher volume than inner channels, para 30); and
a semiconductor device over the substrate (Fig. 4, layers 140 [the layer that the pointer 140 is pointing to] and 148 encompassing semiconductor device above substrates 110, 130, and 146 ), the semiconductor device being vertically aligned with the channel (Fig. 1 and 4, 140 vertically aligned to 105 within 110) and spaced apart therefrom (Fig. 1 and 4, 140 spaced apart from 110), wherein the fluid flows in a direction laterally under the semiconductor device within the substrate.(Fig. 1 and 4, fluid flows into 112 through 150, 152, 160, 154 and 114 laterally from one side to the other under semiconductor device 140 and 148).
Regarding claim 2, Dede teaches the limitations of claim 1 upon which claim 2 depends. Dede teaches further comprising: a first opening partially through the substrate, the first opening vertically connecting to the channel at a first end thereof; and a second opening partially through the substrate, the second opening vertically connecting to the channel at a second end thereof, the second end is laterally opposite the first end (Fig. 4, 112 inlet port and 114 outlet port opposite ends laterally, para 18 states the inlet and outlets may vertically connect to 118 or 116 surfaces of 110).
Regarding claim 3, Dede teaches the limitations of claim 2 upon which claim 3 depends. Dede teaches wherein the third channel portion comprises: a first end having a maximum cross-sectional area laterally connecting to the first channel portion, the first end is proximate to the first opening of the channel; and a second end laterally opposite the first end, the second end having a minimum cross-sectional area connecting to the second channel portion, the second end is proximate to the second opening of the channel (Fig. 4, center 160 with lateral connections to other 160 not depicted in figures, para 26).
Regarding claim 4, Dede teaches the limitations of claim 3 upon which claim 4 depends. Dede teaches wherein the first opening of the channel is an inlet to allow the fluid to flow into the channel and the second opening is an outlet to allow the fluid to leave the channel (Fig. 1 and 4, channel system 150, para 26).
Regarding claim 5, Dede teaches the limitations of claim 2 upon which claim 5 depends. Dede teaches wherein the first opening comprising: a first opening portion vertically connecting to the channel (Fig. 4, 112 inlet port and 114 outlet port opposite ends laterally, para 18 states the inlet and outlets may vertically connect to 118 or 116 surfaces of 110), the first opening portion having a first width; and a second opening portion vertically aligned with first opening portion (para 18 states the inlet and outlets may vertically connect to 118 or 116 surfaces of 110), the second opening portion having a second width wider than the first width (Fig. 4, 114/112 first width, outermost channels 160 second width).
Regarding claim 6, Dede teaches the limitations of claim 5 upon which claim 6 depends. Dede teaches wherein the first opening portion is in the substrate and the second opening is over the substrate (Fig. 4, 114/112 open in substrate, outermost 160s open above substrate).
Regarding claim 7, Dede teaches the limitations of claim 1 upon which claim 7 depends. Dede teaches wherein the substrate further comprising: a base layer within which the channel is enclosed within (Fig. 4, 110 substrate ecloses channel system 150 and base thereof); and a device layer over the channel (Fig. 4, 120 over 150) and in contact with the base layer (Fig. 4, 110).
Regarding claim 8, Dede teaches the limitations of claim 7 upon which claim 8 depends. Dede teaches wherein the channel comprises: trenches spaced apart by a portion of the base layer (Fig. 4, 112/114); and a cavity under the trenches and connecting thereto (Fig. 4, cavity of 150 including 152/154).
Regarding claim 16, Dede teaches a method of forming a semiconductor structure, comprising:
forming a channel enclosed within a base layer of a substrate for a fluid to flow through (Fig. 4, system 150 in substrate 110), the base layer has an upper base surface (Fig. 1, 116), and the channel comprises:
a first channel portion having a first volume (Fig. 4, left most channel 160 by outlet channel 154);
a second channel portion having a second volume (Fig. 4, right most channel 160 by inlet channel 152); and
a third channel portion laterally connecting the first channel portion to the second channel portion (Fig. 4 center most channel 160 connected from the sides not pictured to other 160s), the third channel portion has a third volume smaller than the first volume and the second volume (channel sections near in/outlet have higher volume than inner channels);
forming a device layer over the base layer (Fig. 1, 120);
forming a semiconductor device over the substrate, the semiconductor device being vertically aligned with the channel (layers 140 [the layer where the pointer 140 is pointing to] and 148 encompassing semiconductor device above substrates 110, 130, and 146 vertically aligned to 105 within 110) and spaced apart therefrom (Fig. 1 and 4, 140 spaced apart from 110), wherein the fluid flows in a direction laterally under the semiconductor device within the substrate.(Fig. 1 and 4, fluid flows into 112 through 150, 152, 160, 154 and 114 laterally from one side to the other of device 140).
Regarding claim 17, Dede teaches the limitations of claim 16 upon which claim 17 depends. Dede teaches forming a first trench (Fig. 4, 112/114) and a second trench (Fig. 4, outer most channel 160s ) extending downwardly from an upper base surface (Fig. 4, 110), the first trench has a narrower width than the second trench (112/114 is narrower than outer most 160s); and forming a cavity under the first trench and the second trench (Fig. 4, cavity of 150 including 152/154), the cavity is spatially connecting thereto (Fig. 4, cavity of 150 including 152/154), wherein the portion of the cavity under the first trench extends to a shallower depth from the upper base surface than the portion of the cavity under the second trench (Fig. 4 center most channel 160s).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-11 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Dede et al (US Publication 20180025962) in view of Matioli et al (US Publication 20230037442).
Regarding claims 9 and 18-20, Dede teaches the limitations of claim 8 upon which claim 9 depends. Dede teaches the limitations of claims 16 and 17 upon which claims 18 and 20 depend.
Dede does not specifically teach:
[claim 9] further comprising plugs in the trenches and the plugs are in contact with the device layer.
[claim 18] further comprises forming a plug in at least the upper portions of the first trench and the second trench.
[claim 19] wherein forming the plug comprises: depositing a reflowable material over the upper base surface and conformally lining the surfaces of the channel; and performing a heat treatment to increase the temperature of the reflowable material to at least the reflow temperature thereof.
[claim 20] wherein forming the device layer comprises performing an epitaxy process at least over the upper base surface.
Matioli teaches:
[claim 9] further comprising plugs in the trenches and the plugs are in contact with the device layer (Fig. 3, 112, para 116 copper).
[claim 18] further comprises forming a plug in at least the upper portions of the first trench and the second trench (Fig. 3, 112, para 116 copper).
[claim 19] wherein forming the plug comprises: depositing a reflowable material over the upper base surface and conformally lining the surfaces of the channel; and performing a heat treatment to increase the temperature of the reflowable material to at least the reflow temperature thereof (Fig. 4, 170, para 31 copper).
[claim 20] wherein forming the device layer comprises performing an epitaxy process at least over the upper base surface (para 36).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Dede to include copper caps and device layer epitaxy process as taught by Matioli in order to facilitate increased thermal functionality and reliability of the system.
Regarding claim 10, Dede as modified discloses a liner in the cavity, the liner comprising the same material as the plugs (Dede - Fig. 4, 170, para 31 copper).
Regarding claim 11, Dede as modified discloses wherein the material is a semiconductor material (Dede - para 17).
Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Dede et al (US Publication 20180025962) in view of Yen et al (US Publication 20230058358).
Regarding claims 12 and 13, Dede teaches
[claim 12] A semiconductor structure, comprising:
a substrate (Fig. 1, 110), the substrate comprising:
a base layer (Fig. 1, 110), the base layer having an upper base surface (Fig. 1, 116); and
a device layer over the base layer (Fig. 1, 120);
a channel enclosed within the base layer with and inlet and an outlet for a fluid to flow through (Fig. 1 and 4, fluid channel 150 enclosed 110 with inlet 112 and outlet 114), the channel comprising:
a first channel portion at a first depth from the upper base surface (Fig. 4, left most channel 160 by outlet channel 154);
a second channel portion at the first depth from the upper base surface (Fig. 4, right most channel 160 by inlet channel 152); and
a third channel portion laterally connecting (Fig. 1 and 4, lateral connection of 160s not depicted in figure) the first channel portion to the second channel portion, the third channel portion is at a second depth from the upper base surface and the second depth is shallower than the first depth (Fig. 4 center most channel 160 with shallower depth that left or right most 160);
a semiconductor device over the substrate, the semiconductor device being vertically aligned with the channel (layers 140 [the layer where the pointer 140 is pointing to] and 148 encompassing semiconductor device above substrates 110, 130, and 146 vertically aligned to 105 within 110) and spaced apart therefrom (Fig. 1 and 4, 140 spaced apart from 110), wherein the fluid flows in a direction laterally under the semiconductor device within the substrate.(Fig. 1 and 4, fluid flows into 112 through 150, 152, 160, 154 and 114 laterally from one side to the other of device 140).
Dede does not specifically teach:
[claim 12] and a dielectric layer over the substrate, covering the semiconductor device.
[claim 13] wherein the inlet comprises a first opening extending vertically through the dielectric layer and the device layer connecting to the channel at a first end thereof; and the outlet comprises a second opening extending vertically through the dielectric layer and the device layer and connecting to the channel at a second end thereof, the second end is laterally opposite the first end, and the semiconductor device is between the first opening and the second opening.
Yen teaches:
[claim 12] and a dielectric layer over the substrate, covering the semiconductor device (para 30, dielectric encapsulant 170 and semiconductor device 151).
[claim 13] wherein the inlet comprises a first opening extending vertically through the dielectric layer and the device layer connecting to the channel at a first end thereof; and the outlet comprises a second opening extending vertically through the dielectric layer and the device layer and connecting to the channel at a second end thereof, the second end is laterally opposite the first end, and the semiconductor device is between the first opening and the second opening (openings in dielectric encapsulant as taught by Yen that correspond to Dede Fig. 4 openings 112/114).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Dede as modified to further include the dielectric encapsulant as taught by Yen in order to facilitate increased thermal functionality and reliability of the system.
Regarding claim 14, Dede as modified teaches limitations of claim 13 upon which claim 14 depends.
Dede teaches further comprising: a non-functional semiconductor device over the channel and adjacent to the semiconductor device; and a third opening through the non-functional semiconductor device connecting to the channel (Fig. 4, 146 over channel 160 and adjacent to device 140).
Regarding claim 15, Dede as modified teaches the limitations of claim 12 upon which claim 15 depends.
Dede teaches further comprising: a fourth channel portion, wherein the second opening connect thereto; and a fifth channel portion laterally connecting the second channel portion to the fourth channel portion, and the fifth channel portion is at a shallower depth than the fourth channel portion from the upper base surface (Fig, 1 and 4, fluid channel system 150 with center 160 shallower than outside 160s, para 27 microchannel size, shape, and depth variance all the different portions are described as having different height/depth variance, para 28 “one or more semiconductor fluid channels 160”).
Response to Arguments
Applicant's arguments filed on 30 July 2025 have been fully considered but they are not persuasive.
Regarding claims 1, 12, and 16, applicant argues that Dede fails to disclose a semiconductor device vertically aligned with a channel and spaced apart therefrom, and a fluid that flows in the channel in a direction laterally under the semiconductor device within the substrate.
Dede teaches a semiconductor device (Fig. 1 and 4, 140, only the layer that 140 is pointing to and layer 148 make up the interpretation of the semiconductor device) is vertically aligned with a channel and spaced apart therefrom (Fig. 1 and 4, 140/148 vertically aligned above and spaced apart from fluid channel system 150), and a fluid that flows in the channel in a direction laterally under the semiconductor device within the substrate (Fig. 1 and 4, fluid flows in fluid channel 150 including inlet 112, inlet channel 152, semiconductor fluid channels 160, fluid outlet channel 154, and outlet 114 under the semiconductor device 140 with in the substrate 110).
While Dede in the paragraphs referenced by the Applicant states that semiconductor 140 includes layers 148 and 146, there is a clear delineation in figure 2 between where 140 is point, where 148 is pointing, and where 146 is pointing as they each have interfaces between them. Therefore, based on broadest reasonable interpretation top layer 140 and second layer 148 can make up the claimed semiconductor device and be above the fluid channel.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS HUTSON whose telephone number is (571)270-1750. The examiner can normally be reached Mon-Fri 8am-5pm.
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/NICHOLAS LELAND HUTSON/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818