CTFR 18/148,577 CTFR 91297 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION Amendment filed on 4/29/26 has been entered. Response to Arguments Regarding claim 1. Applicant’s arguments with regard to the amendment have been fully considered but they are moot because the arguments do not apply to any of the references being used in the current rejection. Regarding claim 7. Applicant’s arguments directed to claim 1 have been considered but are not persuasive as to claim 7. Claim 7 is an independent claim and does not depend from claim 1. Applicant has not specifically traversed the rejection of claim 7 under 35. US.S.C. 102(a)(2) over Choi. Accordingly, the rejection of claim 7 is maintained and further clarified for completeness of the record. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim 7 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Choi (US 20230053379) . Regarding claim 7, Choi discloses a semiconductor device comprising: a nanosheet stack (NS1) disposed between a first source/drain region 150 and a second source/drain region 150 (Fig. 15). Choi further discloses a gate stack 120/130 wrapping around individual channel layers of the nanosheet stack (Fig. 15). Choi additionally discloses an interlayer dielectric (ILD) 145/156/191 covering the nanosheet stack, the first and second source/drain regions, and the gate stack (Fig. 15, [0065], [0098]-[0099]). Choi further discloses a source/drain contact 155/170 on the first source/drain region 150 and extending continuously from an upper surface of the first source/drain region to an upper surface of the ILD (Fig. 15, [0109]). In particular, silicide region 155 is disposed on the first source/drain region 150 and directly contacts conductive contact structure 170 to form a continuous conductive source/drain contact extending to the upper surface of ILD 156. Choi additionally discloses a recessed source/drain contact 155/170 on the second source/drain region 150, wherein upper surface 170_US of the recessed source/drain contact is recessed below upper surface 145_US of the surrounding dielectric structure (Fig. 15). Choi further discloses an isolation element 195 disposed on an upper end of the recessed source/drain contact and separating the recessed source/drain contact from the upper surface of the ILD (Fig. 15, [0131]). Accordingly, Choi discloses all the limitations of claim 7 . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Bi (US 20200287039) in view of Choi (US 20230053379) . Regarding claim 1. Fig 9 (an intermediate step of forming the Fig 11A) and Fig 11A of Bi discloses A semiconductor device comprises: a first source/drain 510 on an end of a first nanosheet stack 114/116/118, a second source/drain 520 on an end of a second nanosheet stack 114/116/118, and a third source/drain 530 on an end of the first nanosheet stack or the second nanosheet stack (Fig. 11A). Bi further discloses an interlayer dielectric (ILD) 702 comprising a monolithic dielectric material that covers the first and second nanosheet stacks and the source/drain regions (Fig. 9). Bi additionally discloses a first source/drain contact 1202/1204 contacting the first source/drain 510 and a second source/drain contact 1202/1204 contacting the second source/drain 520, the first and second source/drain contacts extending continuously from the first and second source/drain regions, respectively, to an upper surface of the ILD (Fig. 11A, [0053]). But Bi does not expressly disclose: a recessed source/drain contact contacting the third source/drain; and an isolation element separating the recessed source/drain contact from the upper surface of the ILD. However, Choi discloses a recessed source/drain contact 170 contacting a source/drain region 150, wherein an upper surface 170_US of the recessed source/drain contact is recessed below an upper surface 145_US of the surrounding dielectric structure (Fig. 15). Choi further discloses an isolation element 195 disposed above the recessed source/drain contact and separating the recessed source/drain contact from the upper surface of the ILD (Fig. 15, [0131]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify one of the source/drain contacts of Bi, such as the contact corresponding to third source/drain region 530, to include the recessed contact configuration and overlying isolation element taught by Choi in order to improve electrical isolation between conductive structures and adjacent device features and to improve device integration reliability. The modification merely applies a known contact topology technique of Choi to the known nanosheet transistor structure of Bi and would have yielded predictable results while preserving the operation of the semiconductor device of Bi. Regarding claim 2, Bi in view of Choi discloses the semiconductor device of claim 1. Bi further discloses that the first gate stack wraps around individual channels of the first nanosheet stack and the second gate stack wrap around individual channels of the second nanosheet stacks (Fig. 11A). Bi further discloses that ILD 702 directly contacts the first gate stack, the second gate stack, the first source/drain 510, the second source/drain 520, and the third source/drain 530 (Figs. 9 and 11A). Regarding claim 3, Bi in view of Choi discloses the semiconductor device of claim 2. Bi further discloses that each of the first and second source/drain contacts 1202/1204 extends from an upper surface of the respective first and second source/drain regions 510/520 to an opposing upper end at the upper surface of the ILD (Fig. 11A and [0053]). Further, Bi discloses the source/drain contacts as continuous conductive structures extending between the bottom end and the upper end without an intervening interface. Regarding claim 4, Bi in view of Choi discloses the semiconductor device of claim 3. Bi further discloses at least one gate contact 1202/1204 on at least one of the first and second gate stacks (Fig. 11A, [0052]; note that the gate contact label in Fig 11A appears to be mislabeled). Regarding claim 5, Bi in view of Choi discloses the semiconductor device of claim 4. Bi further discloses that the at least one gate contact extends continuously from at least one of the first and second gate stacks to the upper surface of ILD 702 (Fig. 11A). Regarding claim 6, Bi in view of Choi discloses the semiconductor device of claim 5. Choi further discloses isolation element 195 disposed between adjacent conductive contact structures in order to electrically isolate conductive features from one another (Figs. 15-16, [0131]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to position the isolation element between the at least one gate contact and the first source/drain contact, or between the at least one gate contact and the second source/drain contact, in order to improve electrical isolation between adjacent conductive structures and improve device integration reliability . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim 11-20 are allowed. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 11. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, in particular, the specific steps of forming ILD trench and further step, “ recessing at least one of target source/drain contact among the plurality of source/drain contacts without recessing one or more remaining source/drain contacts among the plurality of source/drain contacts to form at least one ILD trench in the ILD ; and depositing a dielectric material in the at least one ILD trench to form at least one isolation element that separates the at least one target source/drain contact from the upper surface of the ILD” . 12-151-08 AIA 07-43 12-51-08 Claim s 8-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 8. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the source/drain contact extends from a bottom end that contacts the upper surface of the first source/drain to an opposing upper end that is co-planar with the upper surface of the ILD, and the source/drain contact excludes an interface between the bottom end and the upper end ” . Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Changhyun Yi/Primary Examiner, Art Unit 2812 Application/Control Number: 18/148,577 Page 2 Art Unit: 2812 Application/Control Number: 18/148,577 Page 3 Art Unit: 2812
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