Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Objections
Claim 1 is objected to because of the following informalities: the “a first nanosheet stack a second source/drain” in line 2 should be “a first nanosheet stack, a second source/drain”.
Claim 7 is objected to because of the following informalities: the “a first nanosheet stack a second source/drain” in lines 4-5 should be “a first nanosheet stack, a second source/drain”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-6 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding claim 1, the claim recites the limitation “the first and second gate stacks” in line(s) 6. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the limitation is interpreted as “first and second gate stacks”. Thus, the examiner recommends amending the limitation as “[[the]] first and second gate stacks”.
Regarding claims 2-6, because of their dependency on claim 1, these claims are also rejected for the reasons set forth above with respect to claim 1. In particular, to overcome the 112(b) rejection, in the claim 2, the “a first gate stack” and “a second gate stack” should be appropriately amended.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Choi (US 20230053379).
Regarding claim 1. Fig 15 of Choi discloses A semiconductor device comprises:
a first source/drain 150 ([0067]: the very left 150) on an end (left end) of a first nanosheet stack ([0032]/[0042]: the right side NS1 from the first 150), a second source/drain 150 (the center 150) on an end (left end) of a second nanosheet stack (the right side NS1 from the center 150), and a third source/drain 150 (the very right 150) on an end (the right end of the second NS1) of the first nanosheet stack or the second nanosheet stack;
an interlayer dielectric (ILD) 145/156/191 [0065]/[0098]/[0099] covering the first and second nanosheet stacks, [[the]] first and second source/drains (refer to the above 112 rejection for the interpretation), and the first and second gate stacks 120/130 (Fig 15, [0070]); and
a first source/drain contact 155/170 (on the first source/drain, [0109]: 155 is contact silicide. Thus, being a part of source/drain contact) that contacts the first source/drain and a second source/drain contact 155/170 (on the second source/drain) that contacts the second source/drain, the first and second source/drain contacts extending continuously from the first and second source/drains, respectively, to an upper surface of the ILD (Fig 15, refer to the concave top 170);
a recessed source/drain contact 155/170 (on the third source/drain, refer to 170_US) that contacts the third source/drain; and
an isolation element 195 [0131] separating the recessed source/drain contact from the upper surface of the ILD (Fig 15).
Regarding claim 2. Choi discloses The semiconductor device of claim 1, further comprising a first gate stack 120/130 (in the first nanosheet stack) wrapping around individual channels of the first nanosheet stack and a second gate stack 120/130 (in the second nanosheet stack) wrapping around individual channels of the second nanosheet stack, wherein the ILD covers the first and second gate stacks (Fig 15).
Regarding claim 3. Choi discloses The semiconductor device of claim 2, wherein each of the first and second source/drain contacts extends from an upper surface of the first and second source/drains, respectively, to an opposing upper end (Fig 15), and
wherein each of the first and second source/drain contacts excludes an interface between the bottom end and the upper end (Fig 15).
Regarding claim 4. Choi discloses The semiconductor device of claim 3, further comprising at least one gate contact 175 on at least one of the first and second gate stacks (Fig 16, which discloses different view of Fig 15).
Regarding claim 5. Choi discloses The semiconductor device of claim 4, wherein the at least one gate contact extends continuously from at least one of the first and second gate stacks to the upper surface of the ILD (Fig 16).
Regarding claim 6. Choi discloses The semiconductor device of claim 5, wherein the isolation element is between the at least one gate contact and the first source/drain contact, or is between the at least one gate contact and the second source/drain contact (Fig 15/Fig 16).
Regarding claim 7. Fig 15 of Choi discloses A semiconductor device comprising:
a nanosheet stack (NS1, the left side NS1 from the center 150) between a first source/drain 150 (the center 150) and a second source/drain 150 (the very right 150);
a gate stack 120/130 wrapping around individual channels of the nanosheet stack;
an interlayer dielectric (ILD) 145/156/191 [0065]/[0098]/[0099] that covers the nanosheet stack, the first and second source/drains, and the gate stack (Fig 15);
a source/drain contact 155/170 (on the first source/drain, [0109]: 155 is contact silicide. Thus, being a part of source/drain contact) extending continuously from an upper surface (the top surface of 150) of the first source/drain to an upper surface (the upper surface of 156) of the ILD (Fig 15);
a recessed source/drain contact 155/170 (on the second source/drain, refer to 170_US) on an upper surface of the second source/drain; and
an isolation element 195 [0131] on an upper end of the recessed source/drain contact and separating the recessed source/drain contact from the upper surface of the ILD (Fig 15).
Allowable Subject Matter
Claim 11-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 11. Choi (US 20230053379) discloses some steps of forming A method of fabricating a semiconductor device including the method comprising:
forming a plurality of nanosheet stacks (NS1) above an upper surface of a semiconductor substrate 100 (Fig 34, [0038]);
forming a plurality of source/drains 150, each of the source/drains formed on an end of a respective nanosheet stack among the plurality of nanosheet stacks (Fig 34);
forming a plurality of gate stacks 120/130, each of the gate stacks wrapping around individual channels of a respective nanosheet stack among the plurality of nanosheet stacks (Fig 34);
depositing an interlayer dielectric (ILD) 145/156/191 [0065]/[0098]/[0099] on the semiconductor substrate that covers the plurality of nanosheet stacks, the plurality of source/drains, and the plurality of gate stacks (Fig 34);
forming a plurality of source/drain contacts 155/170 that contact the plurality of source/drains, each of the source/drain contacts extending continuously from the plurality of source/drains to an upper surface of the ILD (Fig 36).
However, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, in particular, the specific steps of forming ILD trench and further step, “recessing at least one of target source/drain contact among the plurality of source/drain contacts without recessing one or more remaining source/drain contacts among the plurality of source/drain contacts to form at least one ILD trench in the ILD; and depositing a dielectric material in the at least one ILD trench to form at least one isolation element that separates the at least one target source/drain contact from the upper surface of the ILD”.
Claims 8-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 8. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the source/drain contact extends from a bottom end that contacts the upper surface of the first source/drain to an opposing upper end that is co-planar with the upper surface of the ILD, and the source/drain contact excludes an interface between the bottom end and the upper end”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812