DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
As of October 5, 2026, no information disclosure statement has been made of record.
The listing of references in the specification is not a proper information disclosure statement. 37 CFR 1.98(b) requires a list of all patents, publications, or other information submitted for consideration by the Office, and MPEP § 609.04(a) states, "the list may not be incorporated into the specification but must be submitted in a separate paper." Therefore, unless the references have been cited by the examiner on form PTO-892, they have not been considered. See specification at ¶ 0020.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 1 and 12,
Applicant has amended claims 1 and 12 to include the limitation:
the first one and the second one of the first transistor banks are conductively coupled to each other and conductively isolated from the first one and the second one of the second transistor banks
The limitation lacks written description support.
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The limitation lacks written description support because as shown in Examiner figure 1 the limitation runs counter to Applicant’s disclosure. As stated in the remarks dated September 18, 2026 on page 1 of 6, Applicant is relying on figure 3. Paragraph 0026 of the specification states that one half of the banks of figure 1 are connected together to make up transistor 310 in figure 3, and the other half are connected together to make up transistor 320 in figure 3. Looking at figure 3 in Examiner figure 1 above, we see that transistor 310 and transistor 320 are conductively (electrically) connected together. Therefore, transistor 310 and transistor 320 cannot be conductively isolated from each other. Since transistor 310 and transistor 320 are comprised of the first transistor bank and second transistor bank then the first transistor bank and second transistor bank cannot be conductively isolated from each other. Therefore, the amendments to claims 1 and 12 lack written description support as it is directly counter to Applicant’s specification and stated support for their amendment.
For purposes of examination only, Examiner will treat the limitation above as allowing the resulting transistor to be conductively connected together.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6, 8, 10, 12-17, 19, and 21 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Arai et al. (US 2006/0175635 A1) (“Arai”).
Regarding claims 1 and 12, Arai teaches at least in figures 8A, and 13A-16B:
a first transistor array (described below) in or over a semiconductor substrate (¶ 0003) and distributed among a first plurality (A1) of first transistor banks (a plurality of sets of CC/EC/BC; hereinafter A; therefore a first transistor array is a plurality of As; hereinafter As); and
a second transistor array (described below) in or over the semiconductor substrate (¶ 0003) and distributed among a second plurality (B2) of second transistor banks (a second set of CC/EC/BC; hereinafter B; therefore a second transistor array is a plurality of Bs; hereinafter Bs),
wherein a first one (A1) of the first transistor banks (As) is located between a first one (a first one of B; hereinafter B1) and a second one (a second one of B; hereinafter B2) of the second transistor banks (Bs), and
the second one (B2) of the second transistor banks (B) is located between the first one (A1) of the first transistor banks (As) and a second one (A2) of the first transistor banks (As),
the first one (A1) of the first transistor banks (As) includes a first number of blocks (a subset of the plurality of CC/EC/BC; hereinafter A1a), and
the second one (A2) of the first transistor banks (As) includes a second smaller number of blocks (a second subset of the plurality of CC/EC/BC; hereinafter A2a).
Examiner note: Applicant’s first transistor banks and second transistor banks along with their corresponding subsets are broad to the extend that Examiner can just keep creating subsets of the first transistor bank and second transistor bank. Applicant needs to add either more structure, or add more relational restrictions between the first transistor banks, second transistor banks, and their subsets such that Examiner cannot keep subdividing the banks. In addition, Applicant may want to start picture claiming figure 1B.
Referring to figure 8 of Arai, and Examiner figure 2:
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the first one (Z1) and the second one (Z2) of the first transistor banks (Z) are conductively coupled to each other (X) and conductively isolated from the first one (Y1) and the second one (Y2) of the second transistor banks (Y) (This is ignoring V in Examiner figure 2, as it appears Applicant is ignoring the same feature in their figure 3. See 35 USC § 112(a) above.
Regarding claims 2 and 13, Arai teaches at least in figures 13A-16B:
Wherein the second one (B2) of the second transistor banks (B) includes a second smaller number of blocks (either part of the subset A2 or all of the subset A2 can be grouped with B2, a subset of the plurality of CC/EC/BC; hereinafter B; Please see note at the end of claim 1).
Regarding claims 3 and 14, Arai teaches at least in figures 13A-16B:
wherein the blocks (A’ and B’) are individually isolated (See figure 15A).
Regarding claims 4 and 15, Arai teaches at least in figures 13A-16B:
wherein the blocks (A’ and B’) include deep trench isolation structures that surround corresponding blocks (2b so surrounds).
Regarding claims 5 and 16, Arai teaches at least in figures 13A-16B:
wherein the second one (A2) of the first transistor banks (As) is located between the second one (B2) of the second transistor banks (Bs) and a third one (B3) of the second transistor banks (Bs);
the first one (A1) of the first transistor banks (As) and the second one (B2) of the second transistor banks (Bs) laterally extend over the semiconductor substrate (¶ 0003) a first distance in a first direction (This is so shown in the figures); and
the first one (B1) of the second transistor banks (Bs) and the second one (A2) of the first transistor banks (As) laterally extend a greater second distance in the first direction (This is so shown in the figures).
Regarding claims 6 and 17, Arai teaches at least in figures 13A-16B:
wherein the first (A1) and second ones (A2) of the first transistor banks (As) and the first (B1) and second ones (B2) of the second transistor banks (Bs) bound a central region of the integrated circuit located directly between the first one of the second transistor banks and the second one of the first transistor banks (Based upon the breath of the claimed pluralities Arai teaches this at least in figure 16A-B).
Regarding claims 8 and 19, Arai teaches at least in figures 13A-16B:
wherein the first plurality of first transistor bank is configured as a high-side transistor of a voltage converter circuit and the second plurality of second transistor bank is configured as a low-side transistor of the voltage converter circuit (This is considered a relabeling of the banks of claim 1. This claim adds no new structure and carries no patentable weight. The banks of claim 1 can be so configured simply by relabeling them), the high-side transistor configured to operate at a first voltage and the low-side transistor is configured to operate at a second voltage that is less than the first voltage (this is considered a use of the device. There is nothing structural different being claimed from the use of the term “configured”. The term “configured” is being used to describe how the claimed transistor will be used. Therefore, this limitation does not add patentable weight to the claims.).
Regarding claims 10 and 21, Arai teaches at least in figures 13A-16B:
wherein the first (As) and second transistor arrays (Bs) include a plurality of isolated sub-banks, each sub-bank including a plurality of vertical trench transistor segments (this is shown in figure 15A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7, and 18-19, is/are rejected under 35 U.S.C. 103 as being unpatentable over Arai.
Regarding claims 7 and 18, Arai does not expressly teach:
further comprising active circuit components configured to control the first and second transistor banks, wherein the active circuit components are located in the central region.
However, it would have been obvious that one of ordinary skill in the art using routine skill in the art could wire up, i.e. connect, the transistor array as claimed. This is because transistors are active circuit components, and they can be “configured”, or connected together, to control a subset of the other transistors arbitrarily grouped together as banks. Therefore, while Arai does not expressly teach the above limitation this would have bene obvious to one of ordinary skill in the art before the effective filing date of the current application.
Regarding claim 19, Arai does not expressly teach:
wherein the first transistor banks are configured as a high-side transistor of a voltage converter circuit and the second transistor banks are configured as a low-side transistor of the voltage converter circuit (This is an intended use of the device. One of ordinary skill in the art can hook “configure” or use the device of the prior art as claimed. Further, nothing in the claim prevents one set of transistors from being used as, or called, high-side transistors, nor prevents another set of transistors from being used as, or called, low-side transistors. Further, voltage converter circuits are well-known in the art, and one of ordinary skill in the art using routine skill in the art would have been able to make the claimed device using only routine skill in the art. In addition, there is no structure in claim 1 which distinguishes a high-side transistor from a low-side transistor. Therefore, this limitation would have been obvious to one of ordinary skill in the art before the effective filing date of the current application using routine skill in the art.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arai, in view of Oshima et al. (US 2018/0211898 A1) (“Oshima”)
Regarding claims 9, Arai does not expressly teach:
wherein a first spacing between sub-banks in the first one of the first transistor banks is greater than a second spacing between sub-banks in the second one of the first transistor banks.
Oshima teaches
wherein a first spacing between sub-banks in the first one of the first transistor banks is greater than a second spacing between sub-banks in the second one of the first transistor banks (Oshima teaches that one would want different spacing 401-404 between the banks 201-205 in order to change, increase or decrease, the heat dissipation between the banks. ¶ 0035).
It would have been obvious to one of ordinary skill in the art to adjust the spacing between the banks and/or sub-banks of the first transistor banks and/or second transistor banks in order to adjust and optimize the heat dissipation generated by the active (transistor) elements of the banks.
Claim(s) 11, and 22, is/are rejected under 35 U.S.C. 103 as being unpatentable over Arai, in view Yang (US 7,535,057 B2) (“Yang”)
Regarding claims 11 and 22, Arai does not expressly teach:
wherein a first block of the first one of the second transistor banks has a first number of vertical trench transistor segments and a second block of the second one of the second transistor banks has a lesser second number of vertical trench transistor segments.
This is because Arai does not teach vertical transistors. Arai teaches planar transistors. In this case planar BJT transistors.
In regards to the number of transistors in each block the prior art can be arbitrarily grouped together in the same manner.
Yang teaches:
That one can use MOSFETs instead of BJTs. Col. 1 at lines 20-45, were BJTs were commonly used. Col. 1 at lines 45-67, where one could use MOSFETs to improve performances. The replacement of BJTs with MOSFETs would have been an obvious substitution for one of ordinary skill in the art because by doing so they could improve the performance of the device of Arai.
Allowable Subject Matter
Claim 23 is allowed.
The following is an examiner’s statement of reasons for allowance: see below.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Regarding claim 23, Arai teaches at least in figures 8, and 13A-16B all of the limitations of claim 23 with the exception of
a density of the transistor fingers is greater at a periphery of the integrated circuit than at a central region of the integrated circuit, the density decreasing toward the central region both in a direction along the rows and in a direction along the columns.
Response to Arguments
Applicant’s amendments field September 18, 2026 do not overcome the art of record.
Applicant’s amendments have introduced 35 USC § 112(a) written description issues in to claims, and are rejected for the reasons stated above in the 35 USC § 112(a) section. In regards to the prior art rejection Examiner has included Examiner figure 2 to show how the prior art reads upon the amendments to the claims.
Conclusion
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/VINCENT WALL/ Primary Examiner, Art Unit 2898
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