3DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 5/29/2026 is acknowledged.
Claims 14-26 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 5/29/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8, 11-13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kwon et al (US 2023/0061418; hereinafter Kwon).
Regarding claim 1, Fig 4 of Kwon discloses an apparatus comprising:
a substrate (110; Fig 4; ¶ [0023]);
integrated circuitry (120; Fig 4; ¶ [0025]) on a first side (Bottom side; Fig 4) of the substrate (110; Fig 4; ¶ [0023]); and
an array of pins (140/132; Fig 4; ¶ [0022]) extending through the substrate (110; Fig 4; ¶ [0023]), the pins (140/132; Fig 4; ¶ [0022]) including first ends (Bottom ends; Fig 4) on the first side (Bottom side; Fig 4) of the substrate (110; Fig 4; ¶ [0023]) and second ends (132; Fig 4) protruding beyond a second side (Top side; Fig 4) of the substrate opposite the first side.
Regarding claim 2, Fig 4 of Kwon discloses the integrated circuitry (120; Fig 4; ¶ [0025]) includes an application-specific integrated circuit (ASIC) with active semiconductor components (¶ [0087]).
Regarding claim 3, Fig 4 of Kwon discloses the integrated circuitry includes passive circuitry (¶ [0026]) to enable electrical coupling of the array of pins to external processor circuitry. (¶ [0026], [0087])
Regarding claim 4, Fig 4 of Kwon discloses the second ends (132; Fig 4) of the pins (140/132; Fig 4; ¶ [0022]) are exposed to enable the pins ((140/132; Fig 4; ¶ [0022]) to contact structural features of semiconductor components (220; Fig 4; ¶ [0034]) fabricated on a semiconductor wafer (210; Fig 4; ¶ [0034]), the semiconductor wafer (210; Fig 4; ¶ [0034]) distinct from the substrate (110; Fig 4; ¶ [0023]).
Regarding claim 5, Fig 4 of Kwon discloses the semiconductor components (220; Fig 4; ¶ [0034]) correspond to transistors (¶ [0026]) not yet completely fabricated on the semiconductor wafer.
Regarding claim 6, Fig 4 of Kwon discloses portions of the pins (140/132; Fig 4; ¶ [0022]) extending between the second side (Top side; Fig 4) of the substrate (110; Fig 4; ¶ [0023]) and the exposed second ends are covered by a dielectric material (231; Fig 4; ¶ [0046]).
Regarding claim 7, Fig 4 of Kwon discloses first ones of the pins are to provide an excitation signal to the structural features and second ones of the pins are to capture a response signal based on a path of the excitation signal through the structural features. (¶ [0084])
Regarding claim 8, Fig 4 of Kwon discloses the pins (140/132; Fig 4; ¶ [0022]) are distributed across a first area, the semiconductor wafer (210; Fig 4; ¶ [0034]) including regions corresponding to a plurality of semiconductor chips (220; Fig 4), a first one of the semiconductor chips corresponding to a second area of the semiconductor wafer, a size of the first area of approximately equal the second area (Fig 4).
Regarding claim 11, Fig 4 of Kwon discloses the pins (140/132; Fig 4; ¶ [0022]) include cobalt (¶ [0025]).
Regarding claim 12, Fig 4 of Kwon discloses the substrate (110; Fig 4; ¶ [0023]) is a semiconductor substrate (Fig 4).
Regarding claim 13, Fig 4 of Kwon discloses the substrate is a dielectric substrate (Fig 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al (US 2023/0061418; hereinafter Kwon).
Regarding claim 9, Kwon does not expressly disclose adjacent ones of the pins are spaced less than 1 µm apart.
However, the ordinary artisan would have recognized the size and width of the pins to be a result effective variable affecting pitch or spacing between the pins. Thus, it would have been obvious to vary the size and width of the pins in order to achieve the desired spacing within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B
Regarding claim 10, Kwon does not expressly disclose the array of pins include more than 10000 pins.
However, the ordinary artisan would have recognized the number of the pins to be a result effective variable affecting the electrical performance. Thus, it would have been obvious to vary the number of the pins within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Jang (US 2022/0102245)
Nakamura et al (US 2022/0053648)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RATISHA MEHTA whose telephone number is (571)270-7473. The examiner can normally be reached Monday-Friday: 9:00am - 5:00 pm.
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/RATISHA MEHTA/Primary Examiner, Art Unit 2817
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