DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 12, 2026 was considered by the examiner.
Drawings
Examiner withdraws the drawing objection based upon the cancelation of claims 2 and 16.
Claim Rejections - 35 USC § 112(b)
Examiner withdraws the previous 35 USC § 112(b) rejection based upon Applicant’s amendments to claims 1 and 15.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-4, 11, 13-15, and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1 and 15,
Applicant has amended claims 1 and 15 to include “a major part…of the active layer on the substrate”. Applicant’s specification does not define what constitutes “a major part”. The term major part is not a term of art. Any part of the active layer can be considered a major part. This is because the active layer includes the channel, the source region, and the drain region. Each of these is a major part and the device will not work without all three regions. Therefore, it is unclear what “major part” Applicant is referring to in the claims. As such, the metes and bounds of the claim cannot be determined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-4, 11, 13-15, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable by Hirao et al. (US 2007/0187678 A1) (“Hirao”), in view of Luo et al. (CN 111180466 A) by means of (US 2021/0408295 A1) (“Lou”), in view of Singer, Pete, “Scaling the BEOL: A toolbox filled with new processes, boosters, and conductors”, Semiconductor Digest, https://www.semiconductor-digest.com/scaling-the-beol-a-toolbox-filled-with-new-processes-boosters-and-conductors/, Feb. 8, 2020 (“Singer”)
Regarding claims 1, and 15 Hirao teaches at least in figure 1:
a substrate (1);
a first conductive layer (2), disposed on the substrate (1), comprising a sub-source electrode (left 2) and a sub-drain electrode (right 2);
an active layer (3), disposed on a side of the first conductive layer (2) away from the substrate (1), comprising (detailed below)
a source contact portion (part of 3 over left2), a drain contact portion (part of 3 over right 2), and a channel portion (middle part of 2) connected to the source contact portion and the drain contact portion (all of 2 is connected),
wherein the source contact portion covers part of the sub-source electrode, the drain contact portion covers part of the sub-drain electrode, and the channel portion covers a gap between the sub-source electrode and the sub-drain electrode (this is clearly shown in figure 1);
an insulating layer (6), disposed on a side of the first conductive layer away from the substrate, covering the first conductive layer and the active layer (6 covers 2 and 4); and
a second conductive layer (7/2a/5a), disposed on a side of the insulating layer away (6) from the substrate (1), comprising (detailed below)
a gate electrode (7) and a main drain electrode (5a on the right) connected to the sub-drain electrode (2 on the right),
wherein an orthographic projection of the gate electrode on the substrate at least overlaps an orthographic projection of the channel portion on the substrate (7 so overlaps 3).
Hirao does not teach:
a third conductive layer located on a side of the second conductive layer away from the substrate, comprising a protective electrode and a connecting electrode connected to the sub-source electrode,
wherein the protective electrode is not connected to the connecting electrode and is not connected to the main-source electrode wherein an orthographic projection of the protective electrode on the substrate at least overlaps an orthographic projection of the active layer on the substrate.
Lou teaches at least in figure 1:
a third conductive layer (121) located on a side of the second conductive layer (119) away from the substrate (111),
-the third conductive layer (121) comprising a connecting electrode (the via below 121)
It would have been obvious to one of ordinary skill in the art to combine Hirao and Lou in order to have an electrode connection to a pixel, as the third conductive layer 121 of Lou acts as a pixel electrode).
The combination of Hirao and Lou teach:
a connecting electrode ( Lou via in the dashed rectangular box on the right) connected to the sub-source electrode (Hirao 2).
Hirao and Lou do not teach:
the third conductive layer comprising a protective electrode and a connecting electrode connected to a main-source electrode,
wherein the protective electrode is not connected to the connecting electrode and is not connected to a main-source electrode wherein an orthographic projection of the protective electrode on the substrate at least overlaps an orthographic projection of the active layer on the substrate.
Singer teaches in figure 6, and Examiner’s annotated figure 1 below:
PNG
media_image1.png
506
710
media_image1.png
Greyscale
the third conductive layer comprising (detailed below)
a protective electrode (Z) and a connecting electrode (Y) connected to the sub-source electrode (X),
wherein the protective electrode (Z) is not connected to the connecting electrode (Y)and is not connected to a main-source electrode (the main-source electrode is considered the grouping of all “source” electrodes being claimed; In the figure above it could the via above Y);
wherein an orthographic projection of the protective electrode (Z) on the substrate (FEOL) at least overlaps an a major part of (the term major part is not a term of art. Any part of the transistor and of the active layer can be considered a major part. This is because the active layer includes the channel, the source region, and the drain region. Each of these is a major part and the device will not work without all three regions. As can be seen in the figure above the protective electrode Z overlaps with a drain region of the active layer. Therefore, it overlaps with a major part of the active layer) orthographic projection of the active layer (W) on the substrate (FEOL).
It would have been obvious to one of ordinary skill in the art to combine Singer with the previous prior art as singer shows that in a semiconductor device there can be a plurality of different metal layers which are not connected a transistor, and these metal layers can be routed around the semiconductor device. Anyone of these metal layers not connected to the transistor at issue can be considered a protective electrode. Therefore, it would have been obvious to one of ordinary skill in the art to combine said references as this appears to be the standard, conventional, routine, ordinary way one of ordinary skill in the art creates a semiconductor chip.
Regarding claims 3, and 17 Hirao teaches at least in figure 1:
wherein the orthographic projection of the gate electrode on the substrate overlaps at least part of an orthographic projection of the sub- source electrode on the substrate, and the orthographic projection of the gate electrode on the substrate overlaps at least part of an orthographic projection of the sub-drain electrode on the substrate (this is clearly shown in figure 1).
Regarding claim 4, Hirao teaches at least in figure 1:
wherein the orthographic projection of the gate electrode on the substrate overlaps the orthographic projection of the channel portion on the substrate (this is clearly shown in figure 1);
the source contact portion comprises a first doped region, and the drain contact portion comprises a second doped region (¶ 0033, where 3 can be doped, thus left part of 3 and right part of 3 would comprise a first and second doped portion with the structure required by the claim).
Regarding claim 11, the combination of references teaches:
a light-shielding layer (Lou 112), disposed on a side of the first conductive layer (Hirao 2) near the substrate (Lou 111; Hirao 1), comprising (detailed below)
a light-shielding element (Lou 112),
wherein an orthographic projection of the light-shielding element on the substrate overlaps an orthographic projection of the active layer on the substrate (This is shown in Lou figure 1);
the insulating layer (Lou 118; Hirao 6) is provided with a third through hole penetrating through the insulating layer (Lou the via extending from 119) and extending to the light-shielding element (Lou 112);
a side surface of the light-shielding element away from the substrate is exposed from the third through hole (this is shown in Lou figure 1), and
the light-shielding element (Lou 112) is connected to the main drain electrode (Hirao 5a on the right; Lou via in 131) through the third through hole (This is shown in figure 1 of Lou).
Regarding claim 13,
The thickness of the active layer and the thickness of the channel region, and the effects of changing these values are well-known in the art. It would have been obvious to one of ordinary skill in the art to use their routine skill in the art and adjust these variables to adjust the characteristics of the transistor. With respect to the T-shaped active region examiner proffers Chang (US 2009/0114910 A1) for the assertion that adjusting these variables was known to those of ordinary skill in the art before the effective filing date of the current application.
Regarding claim 14,
Claim 14 is obvious/inherent as it is based upon the material of the first conductive layer and second conductive layer. As the prior art teaches the claimed materials of these layers it would have been inherent/obvious that it would have the same claimed characteristics.
Response to Arguments
Applicant’s amendments and arguments with respect to the rejections of claims have been fully considered and are not persuasive.
Applicant’s arguments surround the term “a major part…of the active layer on the substrate.” As shown above the term “major part” is indefinite as it is not defined in the specification, nor in the claims.
In addition, Applicant asserts that Singer Z is staggered from the active layer. However, Singer Z is still above the drain region of the transistor, and as stated in the 35 USC § 112(b) rejection above this is a major part of the active layer.
For all the above reasons, Applicant’s arguments are not persuasive.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT WALL whose telephone number is (571)272-9567. The examiner can normally be reached Monday to Thursday at 7:30am to 2:30pm PST. Interviews can be scheduled on Tuesday thru Thursday at 10am PST or 2pm PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VINCENT WALL/Primary Examiner, Art Unit 2898