DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Non-Compliant Amendment 3
III. Claim Rejections - 35 USC § 103 3
A. Claims 13, 14, 20, 21, 25, 26, 31 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0284814 (“Grivna-814”), as evidenced by US 2017/0084705 (“Grivna-705”). 4
B. Claims 15, 16, 22, 27, 28, and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Grivna-814 in view of Grinva-705. 8
C. Claims 18 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Grivna-814 as evidenced by Grivna-705, as applied to claims 13 and 25 above, and further in view of US 2015/0263114 (“Nakazawa”). 10
D. Claims 19 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Grivna-814 as evidenced by Grivna-705, as applied to claims 13 and 25 above, and further in view of US 2005/0139952 (“Koh”). 11
IV. Allowable Subject Matter 11
V. Response to Arguments 12
Conclusion 12
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Non-Compliant Amendment
The amendment to the claims filed 01/02/2026 fails to comply with 37 C.F.R. 1.121(c)(4)(i) which requires that “[n]o claim text shall be present for any claim … with the status of “cancelled” …”. Here, claims 17 and 23 have been given a status of “Cancelled” but includes text with a line through the text.
Examination will continue without delay, in the interest of expediting prosecution. Future submissions by Applicant, however, should be compliant 37 C.F.R. 1.121(c)(4)(i).
III. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 13, 14, 20, 21, 25, 26, 31 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0284814 (“Grivna-814”), as evidenced by US 2017/0084705 (“Grivna-705”).
With regard to claim 13, Grivna-814 discloses,
13. (Currently Amended) A method of forming an integrated circuit, comprising:
[1] forming a GaN layer [e.g. 15/14/16/18/19] over a semiconductor substrate 13 [i.e. to make a GaN/Si FET (¶¶ 23, 54-56, 76, 100); Fig. 4];
[2] decreasing conductivity of the GaN layer [e.g. 15/14/16/18/19] in a passive device region [by forming the pluralities of first and second voids (features [4a]-[4e], infra)]; and
[3] forming a GaN transistor [i.e. GaN/Si FET (¶¶ 76, 100)] in an active device region 35 [¶ 18] of the GaN layer 15/14/16/18/19.
[4a] the decreasing the conductivity of the GaN layer 15/14/16/18/19 including:
[4b] forming a plurality of first voids 47 in a first dielectric layer 27 that overlies the GaN layer 15/14/16/18/19 [¶¶ 26, 32; Figs. 4-5],
[4b-1] the first voids 47 extending through the first dielectric layer 27 and into the GaN layer 15/14/16/18/19;
[4c] filling a top portion of the first voids 47 with a first dielectric filler 32, while leaving an unfilled lower portion of the first voids 47 [¶ 33; Fig. 6];
[4d] forming a plurality of second voids 52 in a second dielectric layer 32 that overlies the first dielectric layer 27 [¶¶ 34-35; Fig. 7]; and
[4e] filling the second voids 52 with a second dielectric filler [i.e. gas and TEOS oxide 51 (¶ 35)] [Figs. 7-8; ¶¶ 35-36].
With regard to features [1] and [3] of claim 13, Grivna-814 states,
As will be appreciated by those skilled in the art, the example form of IGBT 10 is used as a vehicle to explain the one example method of forming the semiconductor device. However, the method is directly applicable to other devices and other transistor structures. For example, although the descriptions illustrate semiconductor device materials that include silicon, other semiconductor material[s] such as GaAs, GaN, SiC, diamond, Ge, CdTe, and the like may also be used. The material can be bulk substrate, homo-epitaxy or hetero-epitaxy of dissimilar semiconductors. Additionally the described trenches and methods therefor including doped regions 15, 16, 18, and 19, may be a portion of one of a thyristor, a JFET, a MOSFET, a bipolar junction transistor, a SiC FET, or a GaN/Si FET instead of an IGBT or RB-IGBT.
(Grivna-814: ¶ 100; emphasis added)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form a GaN layer (from which the “doped regions 15, 16, 18, and 19,” (id.) are formed) using “hetero-epitaxy” (id.) on the bulk silicon substrate 13, in order to form a “GaN/Si FET” (id.) because Grivna-814 suggests this option.
So done, the FET is formed in the GaN layer 15, 16, 18, and 19, on the bulk Si substrate 13.
With regard to feature [2] of claim 13, Grivna-814 does not indicate that the “termination region 36” (¶ 18) where the voids 47, 52 are formed is a “passive device region”. However, there is no claimed requirement that a passive device be formed in the passive device region. Consequently, the termination region 36 in Grivna-814 need only be capable of being used as a passive device region. Grivna-705 provides evidence that the termination region around the active region can be used as a passive device region.
In this regard, Grivna-705 (14 in Fig. 1), like Grivna-814 (35 in Fig. 2), teaches an active device region 14 surrounded by a termination region 12, i.e. “insulating structure 12” (Grivna-705 ¶ 30), that has the same void configuration as that formed in the termination region 36 in Grivna-814 as evidenced by comparing Figs. 1, 2, and 12-17 of Grivna-705 with Figs. 8 and 12 of Grivna-814. Also like Grivna-814, Grivna-705 teaches that the substrate 92 can be GaN (Grivna-705: ¶ 38). Grivna-705 further shows that the insulating structure region 12 can be used as a passive device region for, e.g. a variety of inductors, as shown in Figs. 21-24 (Grivna-705: ¶¶ 62-67). Therefore, Grivna-705 shows that the termination region 36 in Grivna-814 is inherently capable of being used as a passive device region, which is all that is required by the claim. As such, the burden of proof is shifted to Applicant to prove the contrary. (See MPEP 2112(I)-(V).)
This is all of the limitations of claim 1.
Claims 14 and 20 read,
14. (Currently Amended) The method of Claim 13, wherein the first dielectric layer comprises SiN.
20. (Currently Amended) The method of Claim 13, wherein the second dielectric layer includes silicon oxide.
Grivna-814 does not provides a material for the “insulator 27”, i.e. the claimed “first dielectric layer” or the “insulator 32”, i.e. the claimed “second dielectric layer”, but discloses that the “insulator 57” can be any of silicon dioxide, silicon nitride, or silicon oxynitride (¶ 36).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the insulator 27 from silicon nitride and the insulator 32 from silicon dioxide because it would be compatible with the other insulators used in the device, as evidenced by the use of silicon dioxide or silicon nitride for another insulator 57 in the device that on formed on each of insulators 27 and 32. As such the selection of silicon nitride for the first dielectric and silicon oxide as the second dielectric amounts to obvious material choice. (See MPEP 2144.07.)
With regard to claim 21, Grivna-814 further discloses,
21. (Currently Amended) The method of Claim 13, wherein the first voids 47 include parallel trenches [as shown in Figs. 5 and 12].
With regard to new claim 25, Grivna discloses,
25. (New) A method of forming an integrated circuit, comprising:
[1] forming a GaN layer [e.g. 15/14/16/18/19] over a semiconductor substrate 13 [i.e. to make a GaN/Si FET (¶¶ 54-56, 76, 100); Fig. 4];
[2a] forming a plurality of first voids 47 in a first dielectric layer 27 that overlies the GaN layer 15/14/16/18/19 [¶¶ 26, 32; Figs. 4-5],
[2b] the first voids 47 extending through the first dielectric layer 27 and into the GaN layer 15/14/16/18/19;
[3] filling a top portion of the first voids 47 with a first dielectric filler 32, while leaving an unfilled lower portion of the first voids 47 [¶ 33; Fig. 6];
[4] forming a plurality of second voids 52 in a second dielectric layer 32 that overlies the first dielectric layer 27 [¶¶ 34-35; Fig. 7];
[5] filling the second voids 52 with a second dielectric filler [i.e. gas and TEOS oxide 51 (¶ 35)] decreasing conductivity of the GaN layer 15/14/16/18/19 in a passive device region [Figs. 7-8; ¶¶ 35-36]; and
[6] forming a GaN transistor [i.e. GaN/Si FET (¶¶ 76, 100) in an active device region 35 [¶ 18] of the GaN layer 15/14/16/18/19.
Claims 26, 31, and 32 read,
26. (New) The method of Claim 25, wherein the first dielectric layer comprises SiN.
31. (New) The method of Claim 25, wherein the second dielectric layer includes silicon oxide.
32. (New) The method of Claim 25, wherein the first voids include parallel trenches.
See the discussions under claims 14, 20, and 21, respectively.
B. Claims 15, 16, 22, 27, 28, and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Grivna-814 in view of Grinva-705.
Claims 15, 16, 27, and 28 read,
15. (Currently Amended) The method of Claim 14, further comprising forming a passive device between the plurality of first voids and the plurality of second voids.
16. (Currently Amended) The method of Claim 15, wherein the passive device includes an inductive coil.
27. (New) The method of Claim 26, further comprising forming a passive device over the plurality of first voids.
28. (New) The method of Claim 27, wherein the passive device includes an inductive coil.
The prior art of Grivna-814 as evidenced by Grivna-705, as explained above, discloses each of the features of claims 13, 14, 25, and 26.
As explained above, Grivna-814 does not disclose forming a passive device in the termination region 36 where the voids 47, 52 are formed.
As also explained above, Grivna-705 teaches that a variety of inductors can be formed between the first and second pluralities of void, as shown in Figs. 21-24 (Grivna-705: ¶¶ 62-67).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form an inductor in the region 35 in Grivna-814 because Grivna-705 teaches that the insulating structure region 12 surrounding an active device region can be used to form a variety of types of inductor (supra). The benefit, before the filing of the claimed invention, would have been to enable the inclusion of integrated circuits including inductors. (See MPEP 2143.)
Claims 22 and 33 read,
22. (Currently Amended) The method of Claim 13, wherein the first voids include round holes.
33. (New) The method of Claim 25, wherein the first voids include round holes.
Grivna-814 does not indicate that the first voids 47 include round holes.
Grivna-705 teaches that the first voids and second voids include round opening portions, such as shown with examples 62 and 64 in Figs. 6 (Grivna-705: ¶ 36).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the first voids 47 in Grivna-814 include round opening portions as shown in Fig. 6 of Grivna-705 because Grivna-705 teaches that these shapes for openings can be used for the identical purpose of forming first and second voids for an insulating structure in a semiconductor device.
Moreover, it has been held that changes in shape are an obvious matter of design choice unless there is evidence that the shape is significant. See In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.)
Here there is no evidence that the round hole to form the openings in the first dielectric layer is significant.
C. Claims 18 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Grivna-814 as evidenced by Grivna-705, as applied to claims 13 and 25 above, and further in view of US 2015/0263114 (“Nakazawa”).
Claims 18 and 29 read,
18. (Currently Amended) The method of Claim 13, wherein the first dielectric filler includes hydrogen-silsesquioxane or methyl-silsesquioxane.
29. (New) The method of Claim 25, wherein the first dielectric filler includes hydrogen-silsesquioxane or methyl-silsesquioxane.
The prior art of Grivna-814 as evidenced by Grivna-705, as explained above, discloses each of the features of claims 13 and 25.
Grivna-814 does not teach that the first dielectric filler 32 that may be silicon dioxide is made from hydrogen-silsesquioxane (HSQ) or methyl-silsesquioxane (MSQ).
Nakazawa uses an insulating layer 17 formed from, e.g., HSQ to seal voids, i.e. isolation trenches 22, etched in a silicon substrate 1 (Nakazawa: ¶¶ 19, 32, 37).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use HSQ, as taught by Nakazawa, as the silicon oxide material 32 to seal the voids of Grivna-814 because Grivna-814 is silent as to the material used to seal the first voids 47 such that one having ordinary skill in the art would use known materials such as the silicon oxide formed from HSQ, as taught in Nakazawa. As such, the used of HSQ amounts to obvious material choice. (See MPEP 2144.07.)
D. Claims 19 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Grivna-814 as evidenced by Grivna-705, as applied to claims 13 and 25 above, and further in view of US 2005/0139952 (“Koh”).
Claims 19 and 30 read,
19. (Currently Amended) The method of Claim 13, wherein the first dielectric filler includes a high-density plasma oxide.
30. (New) The method of Claim 25, wherein the first dielectric filler includes a high-density plasma oxide.
The prior art of Grivna-814 as evidenced by Grivna-705, as explained above, discloses each of the features of claims 13 and 25.
Grivna-814 does not teach that the first dielectric filler 32 that may be silicon dioxide is a high-density plasma (HDP) oxide.
Koh teaches forming an isolation by sealing a void G etched in a semiconductor substrate 21 using a HDP oxide 25a (Koh: ¶ 33; Figs. 3E-3F) .
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use HDP oxide as the silicon oxide, as taught by Koh, as the silicon oxide material 32 to seal the voids of Grivna-814 because Grivna-814 is silent as to the material used to seal the first voids 47 such that one having ordinary skill in the art would use known materials such as the silicon oxide formed from high-density plasma, as taught in Koh. As such, the used of high-density plasma oxide amounts to obvious material choice. (See MPEP 2144.07.)
IV. Allowable Subject Matter
Claims 24 and 34 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 24 and 34 read,
24. (Original) The method of Claim 13, further comprising amorphizing the GaN layer in the passive device region.
34. (New) The method of Claim 25, further comprising amorphizing the GaN layer in the passive device region.
The prior art does not reasonably teach or suggest—in the context of the claims— amorphizing the GaN layer in the passive device region.
V. Response to Arguments
Applicant’s amendments to claim 13 render the rejections premised on US 2015/0137135 (“Green”) alone and Green in view of US 2009/0148998 (“Tischler-998”) moot.
Applicant’s arguments filed 01/02/2026 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814