Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1, 3-12 and 15-21, and new claims 23-24 are pending in this application.
Claims 16-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on February 7, 2025.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed February 3, 2026. Claims 1, 3, 4, 7, 15-18, 20, and 21 are amended. Claims 2 and 22 are cancelled. Claims 16-19 remain withdrawn. Claims 23 and 24 are newly added. The Examiner notes that claims 1, 3-12, 15, 20-21, and 23-24 are examined.
Response to Arguments
Applicant's arguments filed February 3, 2026 have been fully considered but they are not persuasive.
Applicant argues that the limitation “and wherein an operating voltage of the first type of transistor is lower than an operating voltage of the second type of transistor” (currently claims 1 and 20, previously claims 2 and 22) is allegedly not obvious over Xie because while Xie teaches that the operating voltages of the transistors are different, Xie does not teach specific or relative values of the operating voltages or that adjusting the operating voltages leads to a reduced bulk effect as taught by the instant application.
Upon reconsideration of the prior art, the Examiner takes the position that in view of the teaching of Xie that the “voltage of each device of the structure can be fine-tuned or adjusted separately from one another” (para. 96) a person of ordinary skill in the art would contemplate that there are advantages to choosing different operating voltages and that the teaching includes both cases in which the first operating voltage is higher or that the second operating voltage is higher. It would therefore be obvious to try making a device in which the first operating voltage is lower as claimed through routine experimentation of optimizing the parameters of the device.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the reduced bulk effect) are not recited in the rejected claims. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Although Xie does not mention the bulk effect, “Mere recognition of latent properties in the prior art does not render nonobvious an otherwise known invention. In re Wiseman, 596 F.2d 1019, 201 USPQ 658 (CCPA 1979)” (MPEP 2145(II))
The arguments are therefore found unpersuasive and the rejection is upheld.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 12, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Gomes (US 2023/0197654 A1) in view of in view of Xie (US 2023/0299085 A1) and Chauhan (International Research Journal of Engineering and Technology, 2016) as evidenced by Topol (IEEE International Electron Devices Meeting, 2005).
With respect to claim 1, Gomes teaches in Fig. 4:
a first chip (IC structure 401’) including a first type of transistor (TFT 382) that is planar transistor (para. 44, The TFTs may be planar channel device);
and a second chip (IC structure 401) bound on the first chip (401’) in a first direction (z), wherein the second chip includes a second type of transistor (FETs 381) that is a fin transistor (para. 42, “FETS 381 are finFETs”) including at least one fin,
Gomes fails to teach:
and further includes an insulating layer,
wherein a thickness of the insulating layer is between 3 to 5 micrometers,
and wherein the second type of transistor is located on a side of the insulating layer away from the first chip
and wherein an operating voltage of the first type of transistor is lower than an operating voltage of the second type of transistor.
Xie teaches:
and further includes an insulating layer (bonding layers 132 and 136k which form an oxide-to-oxide bond) on which the first chip is bound (portion under 132)
and wherein the second type of transistor is located on a side of the insulating layer away from the first chip (see Fig. 21 of Xie)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Xie into the device of Gomes to create a device with an insulating layer between the first and second chips. The ordinary artisan would have been motivated to modify Gomes in the manner set forth above for the purpose of bonding the two chips together with an oxide-oxide bond (para. 51 of Xie).
Xie further teaches in Fig. 20:
wherein an operating voltage of the first type of transistor (nanosheet stack transistor on bottom of stack of Xie) differs from that of the second type of transistor (finFET transistors on top of stack of Xie).
Although Xie does not specifically state which transistor has a higher threshold voltage, Xie teaches that it is desirable to tune the transistors to have different voltages (para. 96 “stacked devices having multiple threshold voltages. Even more specifically, the threshold voltage of each device of the structure 100 can be fine-tuned or adjusted separately from one another”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further incorporate the teachings of Xie into the device of Gomes/Xie to create a device in which two transistors of different types have different operating voltages and the first type has a higher operating voltage than the second type. The ordinary artisan would have been motivated to modify Gomes/Xie in the manner set forth above so that the “voltage of each device of the structure 100 can be fine-tuned or adjusted separately from one another” (para. 96 of Xie) and/or because it would be obvious to tune the operating voltages to have the claimed relationship with reasonable expectation of success
Xie does not specify the thickness of the insulating layer. Chauhan teaches that for silicon on insulator structures, it is known to use a buried oxide layer (BOX) under the transistor with the oxide layer several microns thick:
“It is common to use a BOX several microns thick both for MEMS, in which case the mechanical parts are made in the SOI layer, and for high-power applications, which must withstand high voltages of several tens or hundreds of volts”
It would be obvious to modify the oxide bonding layer of the Gomes/Xie as taught by Chauhan to be several microns thick, therefore teaching the limitation:
wherein a thickness of the insulating layer is between 3 to 5 micrometers,
Although Xie does not refer to the structure as a “silicon on insulator” structure as Chauhan teaches, evidence that the structure of Xie can be considered an SOI structure analogous to the teaching of Chauhan is found in Topol. Topol teaches a stacked SOI structure in which chips are bonded by oxide fusion bonding similar to the bonding of Xie. Therefore, it would be obvious to the ordinary artisan that the benefits of the thickness of a BOX layer taught by Chauhan for a SOI device would apply to the oxide layers of Xie.
Gomes/Xie discloses the claimed invention except for the thickness of the insulating layer. Chauhan teaches that it is known to use an insulating layer in the range of several microns thick for a SOI device. Topol provides evidence that the bonding structure of Xie can be considered an SOI 3D integrated circuit by teaching a similar structure. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention make an insulating layer several microns thick because Chauhan teaches in section “3. STRUCTURE AND EQUIVALENT CIRCUIT OF PD/FD SOI” that such a structure would allow the device to withstand high voltages and that a SOI structure suppresses floating body effects in the circuit (abstract). See MPEP 2144. It would be further obvious to the ordinary artisan to adjust the thickness of “several microns thick” to fall in the claimed range of 3 to 5 micrometers, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
With respect to claim 12, Gomes teaches in Figs. 4, 7, 8 and 9:
wherein the semiconductor device further includes a third chip (Fig. 9, para 66 third chip can include multiple levels of TFT/RCAT access transistors and/or multiple levels of FE capacitors as taught in Figs. 7, 8) bound on a surface of the second chip (401 connected to third chip at interconnect metallization 305) away from the first chip (401’), and one transistor of the second type of transistor (FET 381) and one transistor of the first type of transistor (TFT 382) are connected with the third chip respectively (electrically connected through interconnects 305), wherein the third chip includes a memory structure (para. 66, chips are part of multi-level embedded memory 930.)
With respect to claim 20, Gomes teaches in Figs. 4 and 9:
A memory system, comprising: a semiconductor device including:
a first chip (IC structure 401’) including a first type of transistor (TFT 382) that is planar transistor (para. 44, The TFTs may be planar channel device);
and a second chip (IC structure 401) bound on the first chip (401’) in a first direction (z), wherein the second chip includes a second type of transistor (FETs 381) that is a fin transistor (para. 42, “FETS 381 are finFETs”)
and a controller (para. 65 “mobile computing platform 905”) connected with the semiconductor device (para. 65, “networked together for electronic data processing, which in the exemplary embodiment includes an IC 960 with multiple levels of eDRAM with FE capacitors, for example as described elsewhere herein”, the IC 960 includes the embodiment of Fig. 4) and configured to control the semiconductor device.
Gomes fails to teach:
and further includes an insulating layer,
wherein a thickness of the insulating layer is between 3 to 5 micrometers,
and wherein the second type of transistor is located on a side of the insulating layer away from the first chip
Xie teaches:
and further includes an insulating layer (bonding layers 132 and 136k which form an oxide-to-oxide bond) on which the first chip is bound (portion under 132)
and wherein the second type of transistor is located on a side of the insulating layer away from the first chip (see Fig. 21 of Xie)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Xie into the device of Gomes to create a device with an insulating layer between the first and second chips. The ordinary artisan would have been motivated to modify Gomes in the manner set forth above for the purpose of bonding the two chips together with an oxide-oxide bond (para. 51 of Xie).
wherein an operating voltage of the first type of transistor (nanosheet stack transistor on bottom of stack of Xie) differs from that of the second type of transistor (finFET transistors on top of stack of Xie).
Although Xie does not specifically state which transistor has a higher threshold voltage, Xie teaches that it is desirable to tune the transistors to have different voltages (para. 96 “stacked devices having multiple threshold voltages. Even more specifically, the threshold voltage of each device of the structure 100 can be fine-tuned or adjusted separately from one another”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further incorporate the teachings of Xie into the device of Gomes/Xie to create a device in which two transistors of different types have different operating voltages and the first type has a higher operating voltage than the second type. The ordinary artisan would have been motivated to modify Gomes/Xie in the manner set forth above so that the “voltage of each device of the structure 100 can be fine-tuned or adjusted separately from one another” (para. 96 of Xie) and/or because it would be obvious to tune the operating voltages to have the claimed relationship with reasonable expectation of success.
Xie does not specify the thickness of the insulating layer. Chauhan teaches that for silicon on insulator structures, it is known to use a buried oxide layer (BOX) under the transistor with the oxide layer several microns thick:
“It is common to use a BOX several microns thick both for MEMS, in which case the mechanical parts are made in the SOI layer, and for high-power applications, which must withstand high voltages of several tens or hundreds of volts”
It would be obvious to modify the oxide bonding layer of the Gomes/Xie as taught by Chauhan to be several microns thick, therefore teaching the limitation:
wherein a thickness of the insulating layer is between 3 to 5 micrometers,
Although Xie does not refer to the structure as a “silicon on insulator” structure as Chauhan teaches, evidence that the structure of Xie can be considered an SOI structure analogous to the teaching of Chauhan is found in Topol. Topol teaches a stacked SOI structure in which chips are bonded by oxide fusion bonding similar to the bonding of Xie. Therefore, it would be obvious to the ordinary artisan that the benefits of the thickness of a BOX layer taught by Chauhan for a SOI device would apply to the oxide layers of Xie.
Gomes/Xie discloses the claimed invention except for the thickness of the insulating layer. Chauhan teaches that it is known to use an insulating layer in the range of several microns thick for a SOI device. Topol provides evidence that the bonding structure of Xie can be considered an SOI 3D integrated circuit by teaching a similar structure. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention make an insulating layer several microns thick because Chauhan teaches in section “3. STRUCTURE AND EQUIVALENT CIRCUIT OF PD/FD SOI” that such a structure would allow the device to withstand high voltages and that a SOI structure suppresses floating body effects in the circuit (abstract). See MPEP 2144. It would be further obvious to the ordinary artisan to adjust the thickness of “several microns thick” to fall in the claimed range of 3 to 5 micrometers, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claims 21, 3-4, 7-9, 11, and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Gomes (US 2023/0197654 A1), Xie (US 2023/0299085 A1) and Chauhan (International Research Journal of Engineering and Technology, 2016) as evidenced by Topol (IEEE International Electron Devices Meeting, 2005) as applied to independent claim 1 above and further in view of Giacomini (Journal of The Electrochemical Society, 2008).
With respect to claim 21, Gomes/Xie/Chauhan teaches all limitations of claim 1 upon which claim 21 depends. Xie further teaches:
Wherein the fin transistor further includes at least one fin,
wherein the fin (fin 138) includes a first surface (top) and a second surface (bottom) arranged opposite to each other along the first direction (z direction),
Gomes/Xie/Chauhan fails to teach:
wherein a length of the first surface is less than a length of the second surface along a third direction
Giacomini teaches in Fig. 3(a):
and wherein a length of the first surface (top) is less than a length of the second surface (bottom) along a third direction (trapezoidal FinFet cross-sectional shape)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Giacomini into the device of Gomes/Xie/Chauhan to create a device with a tapered fin such that the first surface is shorter than the second surface. The ordinary artisan would have been motivated to modify Gomes/Xie/Chauhan in the manner set forth above for the purpose of tuning the threshold voltage of the finFET (Conclusions of Giacomini).
With respect to claim 3, Gomes and Xie further teach:
wherein: the at least on fin (fins 138 plus source and drain regions 144 of Xie) extends in a second direction (x-direction) and include a source region, a channel region, and a drain region (see annotated Fig. 20 below),
wherein the source region (top source drain region 144 of Xie on left), the channel region (fin 138), and the drain region (top source drain region 144 on right) on the at least one fin are distributed in sequence in the second direction (Fig. 20 of Xie);
and a gate layer (functional gates 164 of Xie) is located at a side (top side) of a first fin (138) away from the first chip (the top side of FET 381 of Gomes is away from first chip 401’), and the gate layer (164) includes gates,
wherein each of the gates extends in a third direction (y-direction) that intersects with the second direction (x) and is perpendicular to the first direction (z) and spans a second fin (see annotated Fig. 21 of Xie below),
and a projection of each of the gates (see annotated Fig. 4 of Gomes. Gomes is modified by Xie such that the finFETs of Xie take the footprint of the FET that includes source drain material 310 and contact metallization 375. Per Xie Fig. 21 the gate 164 fully covers the channel 138) on the first chip (401’) covers a projection of one of the channel regions (semiconductor layer 302 of Gomes) corresponding to a gate on the first chip, (per annotated Fig. 4 the projection of FET 381 covers the projection of FET 382)
wherein one transistor of the second type of transistor transistors includes the channel region (138), the source region (source drain 144, see annotated Fig. 20 of Xie), and the drain region (source drain region 144, see annotated Fig. 20 of Xie below) on one of the fins (138 of Xie) and a part of the gate corresponding to the channel region (part of gate 164 of Xie above fin 138).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Gomes in view of Xie, Chuahan, and Giacomini as explained above.
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With respect to claim 4, Gomes and Xie further teach:
wherein the channel region (fin 138 of Xie) of each of the fins (fins 138 plus source/drains 144 of Xie) includes a top face (top of fin 138 of Xie) away from the first chip (401’ of Gomes) that is located on two side faces (left and right) connected with the top face in the third direction, respectively,
wherein each of the gates (164 of Xie) covers the top face and the two side faces of the channel region (138) corresponding to each of the gates (164).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Gomes in view of Xie, Chuahan, and Giacomini as explained above.
With respect to claim 7, Gomes and Xie further teach:
wherein the second chip (401 of Gomes) includes a plurality of the fins (138 of Xie) distributed with spacings (area between fins 138), and each of the gates (164 of Xie) includes a body and a plurality of branches fixed on the body (see annotated Fig. 21), the body extends in the third direction (y), and the plurality of branches extend towards the first chip (401’ of Gomes) in the first direction (z) from the body respectively,
wherein the plurality of branches are located between two adjacent ones of the fins, respectively (annotated Fig. 21).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Gomes in view of Xie, Chuahan, and Giacomini as explained above.
With respect to claim 8, Gomes and Xie further teach:
wherein each transistor of the second type of transistor (FETs 381 of Gomes modified to use the finFETs of Xie) further includes an oxidation layer (dielectric layer 162 of Xie that includes an oxide layer 156, para. 85) located between the channel region (fin 138) and a gate (164) of each transistor of the second type of transistor.
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Gomes in view of Xie, Chuahan, and Giacomini as explained above.
With respect to claim 9, Gomes and Xie further teach:
wherein each transistor of the second type of transistor (FETs 381 of Gomes modified to include the finFETs of Xie) further includes sidewalls (top gate spacers 142) formed on opposite sides of a gate of each transistor (Fig. 20 of Xie) of the second type of transistor in the second direction (x) and extending in the third direction (y, although extension in the y direction is not directly shown in Fig. 20, the examiner takes the position that the spacer must extend in the y direction to have finite width in order to perform its function).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Gomes in view of Xie, Chuahan, and Giacomini as explained above.
With respect to claim 11, Gomes and Xie further teach:
wherein the second chip (401 of Gomes) further includes a first spacer (top gate cut insulators 148 of Xie) located between an adjacent two of the gates (gates 164 of Xie).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Gomes in view of Xie, Chuahan, and Giacomini as explained above.
With respect to claim 23, Gomes/Xie/Chauhan teaches all limitations of claim 20 upon which claim 23 depends. Xie further teaches:
Wherein the fin transistor further includes at least one fin,
wherein the fin (fin 138) includes a first surface (top) and a second surface (bottom) arranged opposite to each other along the first direction (z direction),
Gomes/Xie/Chauhan fails to teach:
wherein a length of the first surface is less than a length of the second surface along a third direction
Giacomini teaches in Fig. 3(a):
and wherein a length of the first surface (top) is less than a length of the second surface (bottom) along a third direction (trapezoidal FinFet cross-sectional shape)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Giacomini into the device of Gomes/Xie/Chauhan to create a device with a tapered fin such that the first surface is shorter than the second surface. The ordinary artisan would have been motivated to modify Gomes/Xie/Chauhan in the manner set forth above for the purpose of tuning the threshold voltage of the finFET (Conclusions of Giacomini).
With respect to claim 24, Gomes and Xie further teach:
wherein: the at least on fin (fins 138 plus source and drain regions 144 of Xie) extends in a second direction (x-direction) and include a source region, a channel region, and a drain region (see annotated Fig. 20 below),
wherein the source region (top source drain region 144 of Xie on left), the channel region (fin 138), and the drain region (top source drain region 144 on right) on the at least one fin are distributed in sequence in the second direction (Fig. 20 of Xie);
and a gate layer (functional gates 164 of Xie) is located at a side (top side) of a first fin (138) away from the first chip (the top side of FET 381 of Gomes is away from first chip 401’), and the gate layer (164) includes gates,
wherein each of the gates extends in the third direction (y-direction) that intersects with the second direction (x) and is perpendicular to the first direction (z) and spans a second fin (see annotated Fig. 21 of Xie below),
and a projection of each of the gates (see annotated Fig. 4 of Gomes. Gomes is modified by Xie such that the finFETs of Xie take the footprint of the FET that includes source drain material 310 and contact metallization 375. Per Xie Fig. 21 the gate 164 fully covers the channel 138) on the first chip (401’) covers a projection of one of the channel regions (semiconductor layer 302 of Gomes) corresponding to a gate on the first chip, (per annotated Fig. 4 the projection of FET 381 covers the projection of FET 382)
wherein one transistor of the second type of transistor transistors includes the channel region (138), the source region (source drain 144, see annotated Fig. 20 of Xie), and the drain region (source drain region 144, see annotated Fig. 20 of Xie below) on one of the fins (138 of Xie) and a part of the gate corresponding to the channel region (part of gate 164 of Xie above fin 138).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Gomes in view of Xie, Chuahan, and Giacomini as explained above.
Claims 5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Gomes (US 2023/0197654 A1) in view of Xie (US 2023/0299085 A1), Chauhan (International Research Journal of Engineering and Technology, 2016) and Giacomini (Journal of The Electrochemical Society, 2008) as evidenced by Topol (IEEE International Electron Devices Meeting, 2005) as applied to claim 3 above and further in view of Liu (CN 114556565 A).
With respect to claim 5, Gomes/Xie/Chauhan/Giacomini teach all limitations of claim 3 upon which claim 5 depends. Gomes/Xie/Chauhan/Giacomini fails to teach:
wherein the source region and the drain region of the first type of transistor are arranged on opposite sides of the channel region in the second direction.
Liu teaches in Figs. 5 and 10:
wherein the source region and the drain region (pair of source and drain electrodes 506) of the first type of transistor (planar transistor 500) are arranged on opposite sides of the channel region in the second direction (into the page in Fig. 10 and 5b which corresponds to the y-direction of Gomes, x-direction of Xie, and y-direction of the instant application)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Liu into the device of Gomes/Xie/Giacomini to include source and drain electrodes arranged in the second direction. The ordinary artisan would have been motivated to modify Gomes/Xie/Chauhan/Giacomini in the manner set forth above for the purpose of allowing space for trench isolation structures to be formed in the third direction to reduce current leakage (para. 81 of Liu.)
With respect to claim 10, Xie further teaches:
wherein the second type of transistor includes a plurality of transistors of the second type of transistor (finFETs defined by fins 138 of Xie) sharing one of the gates (164 of Xie).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Gomes in view of Xie, Chuahan, Giacomini, and Liu as explained above.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Gomes (US 2023/0197654 A1) in view of Xie (US 2023/0299085 A1), Chauhan (International Research Journal of Engineering and Technology, 2016) and Giacomini (Journal of The Electrochemical Society, 2008) as evidenced by Topol (IEEE International Electron Devices Meeting, 2005) as applied to claim 3 above and further in view of Oh (US 2022/0122932 A1).
With respect to claim 6, Gomes/Xie/Chauhan/Giacomini teach all limitations of claim 3 upon which claim 5 depends. Gomes/Xie/Chauhan/Giacomini fails to teach:
wherein the source region and the drain region of the first type of transistor are arranged on opposite sides of the channel region in the third direction
Oh teaches:
wherein the source region (para. 56, junction JC11 which may be used as a source region of transistor TR1) and the drain region (JC12) of the first type of transistor (transistor TR1) are arranged on opposite sides of the channel region in the third direction (Fig. 3, direction FD).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Oh into the device of Gomes/Xie/Chauhan/Giacomini to include source and drain regions in the third direction. The ordinary artisan would have been motivated to modify Gomes/Xie/Chauhan/Giacomini in the manner set forth above for the purpose of making a plurality of transistors on a logic circuit (para. 56 of Oh)
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Gomes (US 2023/0197654 A1) in view of Xie (US 2023/0299085 A1), Chauhan (International Research Journal of Engineering and Technology, 2016) and Giacomini (Journal of The Electrochemical Society, 2008) as evidenced by Topol (IEEE International Electron Devices Meeting, 2005) as applied to claim 3 above and further in view of Tsai (US 2014/0319623 A1).
With respect to claim 15, Gomes/Xie/Chauhin/Giacomini teach all limitations of claim 3 upon which claim 5 depends. Gomes/Xie/Chauhin/Giacomini fails to teach:
wherein a thickness of the fins in the first direction is 24.5 angstroms to 69.0 angstroms.
Tsai teaches in Fig. 1A:
wherein a thickness of the fins (fins 112) in the first direction is 20 to 100 Å (the height of fins 112 above isolation regions 114 ranges from 20 to 100 Å)
The claimed range falls entirely within the range taught in Tsai. "A prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." (MPEP 2144.05 (I)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Tsai into the device of Gomes/Xie/Giacomini to include a fin height in the claimed range. The ordinary artisan would have been motivated to modify Gomes/Xie/Chauhan/Giacomini in the manner set forth above for the purpose of “fabricating a multiple fin-based devices with varied gate structures on the same chip.” (para. 1 of Tsai).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.M.W./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
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