Prosecution Insights
Last updated: August 18, 2026
Application No. 18/148,849

SEMICONDUCTOR COMPONENTS, FABRICATION METHODS THEREOF AND MEMORY SYSTEMS

Final Rejection §102§103
Filed
Dec 30, 2022
Priority
Dec 09, 2022 — CN 202211577764.8
Examiner
KARIMY, TIMOR
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Yangtze Memory Technologies Co., Ltd.
OA Round
2 (Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
854 granted / 1039 resolved
+14.2% vs TC avg
Moderate +10% lift
Without
With
+9.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
41 currently pending
Career history
1084
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
50.0%
+10.0% vs TC avg
§102
20.1%
-19.9% vs TC avg
§112
22.1%
-17.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1039 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 12 & 18 are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by Kreupl et al. (US Pub. 2009/0026524). Regarding claim 12, Kreupl teaches a semiconductor component, comprising: a first wafer 24 including memory cells (Fig. 2 and Para [0013 & 0016]); and a second wafer 12 bonded with the first wafer 24 to form a bonding interface (note the interface between the first wafer12 and the second wafer 24 in Fig. 2 below), the second wafer 12 including a device layer 16 on a first side of the first wafer 24 (see Fig. 2 below) in contact with the bonding interface, wherein a first dielectric layer 38 is on a second side of the first wafer 24 opposite the first side, and a material of the first dielectric layer includes at least one of nitride, polysilicon, or carbonitride (Kreupl teaches in Para [0013], wherein the material for a wiring/ILD layer can be nitride). PNG media_image1.png 716 1004 media_image1.png Greyscale Regarding claim 18, Kreupl teaches a memory system, comprising: a semiconductor component including: a first wafer 24 including memory cells (Fig. 2 and Para [0013 & 0016]); and a second wafer 12 bonded with the first wafer 24 to form a bonding interface (note the interface between the first wafer12 and the second wafer 24 in Fig. 2 below), the second wafer 12 including a device layer 16 on a first side of the first wafer 24 (see Fig. 2 below) in contact with the bonding interface, wherein a first dielectric layer 38 is on a second side of the first wafer 24 opposite the first side, and a material of the first dielectric layer includes at least one of nitride, polysilicon, or carbonitride (Kreupl teaches in Para [0013], wherein the material for a wiring/ILD layer can be nitride); and a controller to control the semiconductor component (Para [0022 & 0064] and Fig. 14). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kreupl as applied to claim 12 above, and in further view of Chen et al. (US Pub. 2020/0027509). Regarding claim 13, perhaps in the interest of brevity, Kreupl is silent on the semiconductor component of claim 12, wherein a thickness of the first dielectric layer is in a range of 2 um to 10 um. However, Chen does disclose a thickness in the range of 0.1 um to 50 um for a similar dielectric layer 304 in Fig. 3A and Para [0053]). These claim dimensions would have been obvious to one of the ordinary skill in the art in view of Chen. One of the ordinary skill in the art is motivated to form device features as small as possible with large enough thickness to allow proper device operation, in order to save on material and processing costs. As such, it would have been obvious to use a thickness of 2 um to 10 um for the dielectric layer. The claim is prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir.1996)(claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955)(selection of optimum ranges within prior art general conditions is obvious). Response to Arguments Applicant’s arguments with respect to claims 12 & 18 have been considered but are moot in view of new grounds of rejection. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOR KARIMY whose telephone number is (571)272-9006. The examiner can normally be reached Monday - Friday: 8:30 AM -5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TIMOR KARIMY/Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Dec 30, 2022
Application Filed
Aug 08, 2023
Response after Non-Final Action
Jan 27, 2026
Non-Final Rejection mailed — §102, §103
Apr 08, 2026
Interview Requested
Apr 20, 2026
Examiner Interview Summary
Apr 20, 2026
Applicant Interview (Telephonic)
Apr 22, 2026
Response Filed
Jun 29, 2026
Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12701719
MEMORY DEVICE STRUCTURE AND FABRICATION METHOD
3y 7m to grant Granted Aug 04, 2026
Patent 12696769
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
3y 2m to grant Granted Jul 28, 2026
Patent 12696793
SEMICONDUCTOR DEVICE PACKAGE WITH OPEN SENSOR CAVITY
3y 3m to grant Granted Jul 28, 2026
Patent 12690198
SEMICONDUCTOR DEVICE STRUCTURE
3y 3m to grant Granted Jul 21, 2026
Patent 12677426
SEMICONDUCTOR DEVICE STRUCTURE
2y 10m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
92%
With Interview (+9.5%)
2y 5m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1039 resolved cases by this examiner. Grant probability derived from career allowance rate.

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