DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 12-13 & 18 without traverse in the reply filed on 11/20/2025 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 12 & 18 are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by Chen et al. (US Pub. 2020/0027509).
Regarding claim 12, Chen teaches a semiconductor component, comprising:
a first wafer 160 including memory cells (120 and/or 114, Fig. 1); and
a second wafer 162 bonded with the first wafer to form a bonding interface 158, the second wafer 162 including a device layer (see Fig. 1 below), wherein a first dielectric layer is on a side of the first wafer facing the bonding interface 158 (see Fig. 1 below), and a material of the first dielectric layer includes at least one of nitride, polysilicon, or carbonitride (see Para [0044], wherein Chen teaches nitride for the dielectric layer of the interconnect layer 142).
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Regarding claim 18, Chen teaches a memory system, comprising:
a semiconductor component including:
a first wafer 160 including memory cells (120 or 114); and
a second wafer 162 bonded with the first wafer 160 to form a bonding interface 158 (Fig. 1), the second wafer 162 including a device layer (see Fig. 1 above), wherein a first dielectric layer is on a side of the first wafer 160 facing the bonding interface 158 (see Fig. 1 above), and a material of the first dielectric layer includes at least one of nitride, polysilicon, or carbonitride (see Para [0044], wherein Chen teaches nitride for the dielectric layer of the interconnect layer 142); and a controller to control the semiconductor component (Para [0041], wherein GLS 134 is taught as a controller to control the semiconductor component and/or Para [0039], wherein memory string 114 is taught as a controller to control the semiconductor component).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al.
Regarding claim 13, perhaps in the interest of brevity, Chen is silent on the semiconductor component of claim 12, wherein a thickness of the first dielectric layer is in a range of 2 um to 10 um. However, Chen does disclose a thickness in the range of 0.1 um to 50 um for a similar dielectric layer 304 in Fig. 3A and Para [0053]). These claim dimensions would have been obvious to one of the ordinary skill in the art in view of Chen. One of the ordinary skill in the art is motivated to form device features as small as possible with large enough thickness to allow proper device operation, in order to save on material and processing costs. As such, it would have been obvious to use a thickness of 2 um to 10 um for the dielectric layer.
The claim is prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir.1996)(claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955)(selection of optimum ranges within prior art general conditions is obvious).
Conclusion
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818