DETAILED ACTION
Claims 1, 3-11, and 15-24 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 19, 2025, has been entered.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections/Recommendations
Claim 22 is objected to because of the following informalities:
In the 2nd to last line, replace “include” with --included--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 3-11, and 15-24 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Referring to claims 1, 10, and 19, applicant now claims selecting/overwriting data independent of data maintained in a mask register. However, the examiner cannot find support for such a limitation, including in paragraphs [0013]-[0018] as pointed out by applicant on page 16 of the response. Instead, at least paragraphs [0013], [0058], and [0061], applicant appears to identify bit 7, which controls the selecting/overwriting, as a mask. A destination register storing bit 7 is, thus, a mask register. As such, the selecting/overwriting appears to be dependent on data maintained in a mask register and to claim otherwise would be new matter unsupported by the original disclosure.
All dependent claims are rejected due to their dependence on a claim lacking adequate written description.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Sazegari, U.S. Patent No. 6,446,198, in view of Moyer, U.S. Patent Application Publication No. 2009/0100253 A1.
Referring to claims 1, Sazegari has taught a system comprising:
a destination register (see FIG.6, VR, and column 5, line 38) and at least two source registers (see FIG.6, V1-V4, and column 4, lines 10-11) storing lookup tables (see the abstract, background, and FIG.3 (which shows an example of a permute operation used in FIG.6). Registers V1-V4 store table data that is looked up via indices in mask register 26); and
a processor (column 3, lines 24-28) configured to perform a register-based lookup by:
retrieving a first result from a first lookup table based on a subset of bits included in an index (see FIGs.3 and 6, where V1-V2 would, during a first permute operation, correspond to data1 and data2 (at least one of which stores a first lookup table). A first result would be obtained using an index in mask 26 and stored in register V12. Only the least significant five bits (bits [4:0]) of the 8-bit index are used to retrieve a given result (because there are 32 total results to choose from across V1 and V2, and five bits allows for selection of one of 32 values (since 25 = 32)));
retrieving a second result from a second lookup table based on the subset of bits included in the index (see FIGs.3 and 6, where V3-V4 would, during a second permute operation, correspond to data1 and data2 (at least one of which stores a second lookup table). A second result would be obtained using the index in mask 26 and stored in register V34 (see column 5, lines 10-11, which set forth that the same index value is used for both retrieval of the first result and second result). Again, only a subset of five bits are used for this retrieval);
selecting the first result or the second result, independent of data maintained in a mask register, by using a bit in the index of the destination register that is excluded from the subset of bits (as explained, only a subset of five bits of the index are used for each retrieval. Thus, the remaining three bits of an index are unused for the permute operations. Bit [5] (just to the left of the subset of bits [4:0]) is used to select the first or second result from V12 and V34 for final storage in to VR (see column 5, lines 1-40). Note that even though bit [5] is in a mask register 26, it is only bit [5] that selects the first or second result. Thus, the selection is independent of data maintained in the mask register, i.e., bits other than bit [5]. Additionally, from FIG.12 and column 7, line 1, there are multiple mask registers in the system and the selection would only be based on mask register 26, and not any of the other mask registers (hence, the selecting is also independent of the data maintained in these other mask registers)); and
storing a selected one of the first result or the second result into the destination register (again, see column 5, lines 1-40 and FIG.6. The selected retrieved first or second result is stored into destination register VR).
Sazegari has not taught that the index is of the destination register, nor that the storing of the selected one of the first result or the second result comprises overwriting data included in the index of the destination register. In other words, Sazegari has not taught that the index register 26 is the same as destination register VR. However, Moyer, who has similarly taught register-based lookups (FIG.8), has also taught that the index register and the destination register for looked-up results can be the same register, and that these looked-up results can overwrite the indices in the destination register (note how FIG.8 shows that register rD holds the indices and also serves as the destination with lookup values replacing the indices). One of ordinary skill in the art would have recognized that if the indices are no longer needed at the end of this lookup operation, it is efficient to simply overwrite the indices as opposed to keeping the indices in one register and writing the lookup result to a separate register (utilizing more registers than necessary). As a result, it would have been obvious to one of ordinary skill in the art to modify Sazegari such that VR is both the index register and the destination register such that the indices therein are overwritten by lookup values at the end of the operation of FIG.6. This would constitute efficient register utilization where the indices are no longer needed after the operation of FIG.6.
Referring to claim 3, Sazegari, as modified, has taught the system of claim 1, wherein the index of the destination register includes a byte lane of eight bits (see FIG.3, which shows byte fields in the registers (each index is a byte). Also, see column 4, lines 18-19), and wherein overwriting the data included in the index of the destination register comprises:
overwriting the byte lane with the first result in response to the bit in the index of the destination register that is excluded from the subset of bits including a first value (see column 5, lines 1-40. Bit [5] of the index (which is not part of the subset), when set to a first value, will select the first result to overwrite the index); or
overwriting the byte lane with the second result in response to the bit in the index of the destination register that is excluded from the subset of bits including a second value (see column 5, lines 1-40. Bit [5] of the index, when set to a second value, will select the second result to overwrite the index).
Referring to claim 5, Sazegari, as modified, has taught the system of claim 1, wherein the retrieving the first result from the first lookup table and retrieving the second result from the second lookup table comprises retrieving the first result by executing a first instruction and retrieving the second result by executing a second instruction (see the abstract and column 5, lines 1-20. Basically, there are two permute instructions/operations executed, a first to retrieve a first result from V1 and V2, and a second to retrieve a second result from V3 and V4).
Referring to claim 6, Sazegari, as modified, has taught the system of claim 5, wherein retrieving the first result from the first lookup table by executing the first instruction and retrieving the second result from the second lookup table by executing the second instruction comprises:
while executing the first instruction (the first instruction carries out the operation of FIG.3 on V1 and V2 in FIG.6, with V1 being data1 and V2 being data2):
selecting, as the first lookup table, a first source register or a second source register from the at least two source registers based on one bit of the subset of bits included in the index of the destination register (from FIG.3, note that the fifth bit of a 5-bit subset (bit [4] of subset bits [4:0]) of an 8-bit index selects V1 or V2. That is, if the fifth bit of an index is 0, then it selects V1. If the fifth bit of an index is 1, then it selects V2);
selecting a first byte lane of the selected first source register or the selected second source register based on a remainder of the subset of bits included in the index of the destination register, the remainder excluding the one bit (the lower four bits of the subset (bits [3:0] of the subset) of the index select one of 16 lanes of the selected one of V1 and V2); and
retrieving the first result from the first byte lane (from FIG.3, an index selects a lane and the value therein is retrieved for storage. For example, the rightmost index in register 26 is 0E (which in binary is 00001110). The subset of bits (bits [4:0]) are the five least significant bits, i.e., 01110. The leftmost bit of 0 selects V1 (data1). Then, the remaining bits 1110 select lane E (or lane 14 or the lanes numbers 0 to 15) in V1 to retrieve the value therein to ultimately store that value in a result register 32); and
while executing the second instruction (the second instruction carries out the operation of FIG.3 on V3 and V4 in FIG.6, with V3 being data1 and V4 being data2):
selecting, as the second lookup table, a third source register or a fourth source register from the at least two source registers based on the one bit of the subset of bits included in the index of the destination register (from FIG.3, note that the fifth bit of a 5-bit subset (bit [4] of subset bits [4:0]) of an 8-bit index selects V3 or V4. That is, if the fifth bit of an index is 0, then it selects V3. If the fifth bit of an index is 1, then it selects V4);
selecting a second byte lane of the selected third source register or the selected fourth source register based on the remainder of the subset of bits included in the index of the destination register (the lower four bits of the subset (bits [3:0] of the subset) of the index select one of 16 lanes of the selected one of V3 and V4); and
retrieving the second result from the second byte lane (again, the result is retrieved from the selected lane of the selected register (see the example given above)).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Sazegari in view of Moyer and Valentine et al., U.S. Patent Application Publication No. 2014/0372727 A1.
Referring to claim 4, Sazegari, as modified, has taught the system of claim 1, but has not taught wherein selecting the first result or the second result comprises the steps of claim 4. However, Valentine has taught selecting between two values by using an index value input into a multiplexer select line (e.g. see FIG.14 and paragraph [0133]), where, for example, bit 1421 is used to control multiplexer 1426 to select between values 1463 and 1464 (other bits are used to control other multiplexers to select between other corresponding values). One of ordinary skill in the art would have recognized that Valentine’s simplistic selection using a multiplexer and the controlling bit (bit [5] of each index) could be substituted for Sazegari’s selection involving various shifting steps (column 5, lines 1-40, and FIGs.7a-9). The results of the substitution would have been predictable due to the known operation of a multiplexer, which would allow selection of either a value in V12 or a corresponding value in V34 by using bit [5] of the corresponding index as a select line to a multiplexer. An additional benefit of using Valentine’s approach would be the elimination of all of the shifting performed by Sazegari to perform the selection. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have substituted Valentine’s use of a bit as a select line to a multiplexer to select one of two values for Sazegari’s shifting for selection. Given this modification, Sazegari, as modified, has taught wherein selecting the first result or the second result comprises:
inputting the first result and the second result to a multiplexer (this is how a multiplexer works to select between two values and is shown in FIG.124 of Valentine);
providing the bit in the index of the destination register that is excluded from the subset of bits as a select line to the multiplexer (again, see FIG.14 of Valentine); and
causing the multiplexer to output the first result in response to the bit in the index of the destination register that is excluded from the subset of bits being a first value; or causing the multiplexer to output the second result in response to the bit in the index of the destination register that is excluded from the subset of bits being a second value (as explained, this is how the multiplexer would work based on bit [5] of an index).
Claims 7-8, 10, 19, 21, and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Sazegari in view of Moyer, and Brown, et al., U.S. Patent Application Publication No. 2018/0321937 A1.
Referring to claim 7, Sazegari, as modified, has taught the system of claim 6, but has not taught wherein the subset of bits included in the index of the destination register includes bits [6:0] of an eight-bit index, wherein: the one bit of the subset of bits is bit six of the eight-bit index; and the remainder of the subset of bits include bits [5:0] of the eight-bit index. Instead, as explained above, Sazegari’s subset includes bits [4:0] of an 8-bit index, wherein the one of the subset of bits is bit [4] of the index, and the remainder of the subset of bits includes bits [3:0] of the index. However, this is because each register is only 128-bits wide, with each register storing 16 bytes. However, Brown has taught implementing registers of various sizes with varying element sizes therein. For instance, Brown has taught 512-bit registers with 64 bytes (see FIG.8 and paragraph [0069] and note the 512-bit zmm registers). The examiner notes that by increasing the size of the registers in Sazegari, larger lookup tables could be implemented with more efficiency because more values can be looked up at once. In addition, a change in size is deemed by the court(s) to constitute a routine expedient and not a patentable distinction, particularly absent some demonstration of the criticality of the claimed size (see MPEP 2144.04, including section IV(A)). As a result, to allow for larger lookup tables, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sazegari such that the registers involved with a permute instruction are 512-bit registers holding 64 bytes as opposed to 128-bit registers holding 16 bytes. With larger registers and more bytes, the subset of the index also has to be changed. That is, the subset would be bits [6:0] (to identify one of 128 total lanes among two registers), with bit [6] selecting a first 512-bit register (V1) or a second 512-bit register (V2). Bits [5:0] of the index would select one of the 64 bytes in the register corresponding to the value of bit [6].
Referring to claim 8, Sazegari, as modified, has taught the system of claim 6, wherein the index of the destination register includes an eight-bit index (again, from FIG.3, each index includes eight bits), and wherein overwriting the data included in the index of the destination register using the selected one of the first result or the second result comprises:
overwriting the data included in the index of the destination register with the first result in response to bit six of the eight-bit index being a first value while executing the first instruction (see column 5, lines 1-40. While the first permute instruction related to V1 and V2 in FIG.6 is being executed, the index’s 6th bit, i.e., bit [5], when equal to a first value, will cause a corresponding value from V1/V2 to overwrite a corresponding index in VR); or
overwriting the data included in the index of the destination register with the second result in response to the bit six of the eight-bit index being a second value while executing the second instruction (see column 5, lines 1-40. While the second permute instruction related to V3 and V4 in FIG.6 is being executed, the index’s 6th bit, i.e., bit [5], when equal to a second value, will cause a corresponding value from V3/V4 to overwrite a corresponding index in VR).
Sazegari has not taught that the overwriting is based on bit seven of the eight-bit index. However, for similar reasoning as set forth for claim 7, it is obvious to increase the register size to 512 bits (for holding 64 bytes). Then, the first unused bit is bit [7] (the leftmost bit of the index), not bit [5].
Referring to claim 10, Sazegari has taught a system comprising:
a mask register storing indices (see FIG.6, VR, and column 5, line 38) and at least two source registers (see FIG.6, V1-V4, and column 4, lines 10-11) storing lookup tables (see the abstract, background, and FIG.3 (which shows an example of a permute operation used in FIG.6). Registers V1-V4 store table data that is looked up via indices in mask register 26)); and
a processor (column 3, lines 24-36) configured to execute instructions (abstract) to:
access the mask register and the at least two source registers (see FIG.3. Note that this operation is what is performed on registers V1 and V2 in FIG.6 and again on registers V3 and V4 in FIG.6 (see column 5, lines 1-40)); and
for an index of the mask register:
identify a byte lane of the at least two source registers based on bits [4:0] of the index of the mask register (again, see FIG.3 and FIG.6 and column 5, lines 1-40. When performing a lookup on V1 (data1) and V2 (data2), the five least significant bits (bits [4:0]) of an 8-bit index in register 26 identify a single lane of the 32 lanes in V1 and V2); and
storing a lookup entry defined in the identified byte lane, independent of data maintained in a mask register, and based on a value of bit five of the index of the mask register (again, see column 5, lines 1-40, and FIG.6. The lookup entry identified by the five least significant bits (bits [4:0]) of the index, is then stored to VR based on bit [5] of the index (which is the sixth bit of the index since the numbering starts with bit 0). Note that even though bit [5] is in a mask register 26, it is only bit [5] that controls the storage of the lookup entry. Thus, the storage is independent of data maintained in the mask register, i.e., independent of bits other than bit [5]. Additionally, from FIG.12 and column 7, line 1, there are multiple mask registers in the system and the storage would only be based on mask register 26, and not any of the other mask registers (hence, the storing is also independent of the data maintained in these other mask registers)).
Sazegari has not taught that the mask register is also the destination register, nor that the storing of the lookup entry defined in the identified byte lane comprises overwriting data included in the index of the destination register. In other words, Sazegari has not taught that index register 26 (column 4, lines 10-11) is the same as destination register VR (FIG.6). However, Moyer, who has similarly taught register-based lookups (FIG.8), has also taught that the index register and the destination register for looked-up results can be the same register, and that these looked-up results can overwrite the indices in the destination register (note how FIG.8 shows that register rD holds the indices and also serves as the destination with lookup values replacing the indices). One of ordinary skill in the art would have recognized that if the indices are no longer needed at the end of this lookup operation, it is efficient to simply overwrite the indices as opposed to keeping the indices in one register and writing the lookup result to a separate register (utilizing more registers than necessary). As a result, it would have been obvious to one of ordinary skill in the art to modify Sazegari such that VR is both the index register and the destination register such that the indices therein are overwritten by lookup values at the end of the operation of FIG.6. This would constitute efficient register utilization where the indices are no longer needed after the operation of FIG.6.
Sazegari has also not taught that the byte lane is identified based on bits [6:0] of the index, nor that the overwriting is based on a value of bit seven of the index. However, this is because each register in Sazegari is only 128-bits wide, with each register storing 16 bytes. However, Brown has taught implementing registers of various sizes with varying element sizes therein. For instance, Brown has taught 512-bit registers with 64 bytes (see FIG.8 and paragraph [0069] and note the 512-bit zmm registers). The examiner notes that by increasing the size of the registers in Sazegari, larger lookup tables could be implemented with more efficiency because more values can be looked up at once. In addition, a change in size is deemed by the court(s) to constitute a routine expedient and not a patentable distinction (absent some demonstration of the criticality of the claimed size). See MPEP 2144.04, including section IV(A). As a result, to allow for larger lookup tables, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sazegari such that the registers involved with a permute instruction are 512-bit registers holding 64 bytes as opposed to 128-bit registers holding 16 bytes. With larger registers and more bytes, the bits used in the index also have to be changed. That is, the bits identifying the byte lane would be bits [6:0] (to identify one of 128 total lanes among two registers), with bit #6 selecting a first 512-bit register (V1) or a second 512-bit register (V2). Bits [5:0] of the index would select one of the 64 bytes in the register corresponding to the value of bit #6. This means that bit seven (among bits [7:0] in the index) is responsible for controlling which value overwrites the index.
Referring to claim 19, Sazegari has taught a method comprising:
accessing a destination register (see FIG.3, register 26 and column 4, lines 10-11. This register is a destination for indices to be written) and a plurality of source registers (see FIG.3, source registers data1 and data2, and column 4, lines 11-12. Also, see FIG.6 and column 5, lines 1-40, and source registers V1, V2, V3, and V4, which correspond to data1, data2, data1, and data2, respectively), the destination register storing indices for retrieving a combination of entries from the plurality of source registers (again, see FIG.3 and the description thereof. Also, see FIG.6 and the description thereof); and
for at least one of the indices of the destination register:
retrieving a first entry identified by bits [4:0] of an index in the destination register from a first lookup table that is stored in the plurality of source registers (again, see FIG.3 and FIG.6 and column 5, lines 1-40. The least significant five bits, i.e., bits [4:0] of an 8-bit index in register 26 identifies a single entry from a first lookup table stored in the two source registers (in FIG.6, the two source registers are V1 and V2). If V1 includes the values shown in data1 from FIG.3, V2 includes the values shown in data2 in FIG.3, and the indices for the operation of FIG.6 are the values shown in FIG.3, then an example of retrieving the first entry would be taking the rightmost index of 0E (00001110 in binary) in FIG.3. Bits [4:0] of this index are 01110. The leftmost bit indicates the source register (0 = V1/data1, 1 = V2/data2). The rightmost 4 bits indicate the exact entry in the indicated source register (1110 = 14, so choose entry #14 (E) among entries numbered 0 to 15));
retrieving a second entry identified by the bits [4:0] of the index in the destination register from a second lookup table that is stored in the plurality of source registers (again, see column 5, lines 1-40. The second permute instruction/operation involving V3 and V4 uses the same index register used by the first permute instruction/operation involving V1 and V2. Thus, bits [4:0] of the same index will retrieve second entry from a second lookup table stored in V3 and V4); and
storing, in a result register, the first entry or the second entry, independent of data maintained in a mask register and based on a value of bit five of the index in the destination register (again, see column 5, lines 1-40 and FIG.6. The first or second entry is stored to result register VR based on bit [5] (the bit just to the left of bits [4:0]) of the index. Note that even though bit [5] is in a mask register 26, it is only bit [5] that controls the storage of the lookup entry. Thus, the storage is independent of data maintained in the mask register, i.e., independent of bits other than bit [5]. Additionally, from FIG.12 and column 7, line 1, there are multiple mask registers in the system and the storage would only be based on mask register 26, and not any of the other mask registers (hence, the storing is also independent of the data maintained in these other mask registers)).
Sazegari has not taught the storing comprises overwriting data included in the index in the destination register with the first entry or the second entry. In other words, Sazegari has not taught that register 26 is the same as register VR. However, Moyer, who has similarly taught register-based lookups (FIG.8), has also taught that the index register and the destination register for looked-up results can be the same register, and that these looked-up results can overwrite the indices in the destination register (note how FIG.8 shows that register rD holds the indices and also serves as the destination with lookup values replacing the indices). One of ordinary skill in the art would have recognized that if the indices are no longer needed at the end of this lookup operation, it is efficient to simply overwrite the indices as opposed to keeping the indices in one register and writing the lookup result to a separate register (utilizing more registers than necessary). As a result, it would have been obvious to one of ordinary skill in the art to modify Sazegari such that VR is both the index register and the destination register such that the indices therein are overwritten by lookup values at the end of the operation of FIG.6. This would constitute efficient register utilization where the indices are no longer needed after the operation of FIG.6.
Sazegari has also not taught that the first entry and the second entry are identified by the bits [6:0] of the index, nor that the overwriting is based on a value of bit seven of the index. However, this is because each register in Sazegari is only 128 bits wide, with each register storing 16 bytes. However, Brown has taught implementing registers of various sizes with varying element sizes therein. For instance, Brown has taught 512-bit registers with 64 bytes (see FIG.8 and paragraph [0069] and note the 512-bit zmm registers). The examiner notes that by increasing the size of the registers in Sazegari, larger lookup tables could be implemented with more efficiency because more values can be looked up at once. In addition, a change in size is deemed by the court(s) to constitute a routine expedient and not a patentable distinction, particularly absent some demonstration of the criticality of the claimed size (see MPEP 2144.04, including section IV(A)). As a result, to allow for larger lookup tables, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sazegari such that the registers involved with a permute instruction are 512-bit registers holding 64 bytes as opposed to 128-bit registers holding 16 bytes. With larger registers and more bytes, the bits used in the index also have to be changed. That is, the bits identifying the byte lane would be bits [6:0] (to identify one of 128 total lanes among two registers), with bit #6 selecting a first 512-bit register (V1) or a second 512-bit register (V2). Bits [5:0] of the index would select one of the 64 bytes in the register corresponding to the value of bit #6. This means that bit seven (among bits [7:0] in the index) is responsible for controlling which value overwrites the index.
Referring to claim 21, Sazegari, as modified, has taught the method of claim 19, wherein overwriting the data included in the index in the destination register with the first entry or the second entry based on the value of bit seven of the index in the destination register comprises:
overwriting the data included in the index in the destination register with the first entry in response to the value of bit seven of the index in the destination register being a first value (as modified, the first entry overwrites data in register VR based on bit [7] being a particular (first) value); or
overwriting the data included in the index in the destination register with the second entry in response to the value of bit seven of the index in the destination register being a second value (this limitation, though not required due to the “or” language, is still taught by Sazegari, as modified, where the first entry overwrites data in register VR based on bit [7] being the opposite of the first vale, i.e., a second value).
Referring to claim 23, Sazegari, as modified, has taught the method of claim 19, wherein retrieving the first entry identified by bits [6:0] of the index in the destination register from the first lookup table that is stored in the plurality of source registers comprises:
selecting, as the first lookup table, a first source register or a second source register of the plurality of source registers based a value of bit six of the index in the destination register (again, as modified, Sazegari’s registers are 512-bit registers with 64 bytes each. To carry out the first permute of FIG.6, bit [6] is used to select the first lookup table among V1 and V2);
selecting a first byte lane of the first lookup table based on bits [5:0] of the index in the destination register (as modified, to select one of 64 bytes from the selected one of V1 and V2, a 6-bit value is required (since 26 = 64). Thus, bits [5:0] of the index select a byte lane); and
retrieving the first entry from the first byte lane (from the selected byte lane, the byte value (the first entry) is retrieved).
Referring to claim 24, Sazegari, as modified, has taught the method of claim 23, wherein retrieving the second entry identified by the bits [6:0] of the index in the destination register from the second lookup table that is stored in the plurality of source registers comprises:
selecting, as the second lookup table, a third source register or a fourth source register of the plurality of source registers based on the value of bit six of the index in the destination register (again, as modified, Sazegari’s registers are 512-bit registers with 64 bytes each. To carry out the second permute of FIG.6, which uses the same index as the first permute, bit [6] is used to select the second lookup table among V3 and V4);
selecting a second byte lane of the second lookup table based on the bits [5:0] of the index in the destination register (as modified, to select one of 64 bytes from the selected one of V3 and V4, a 6-bit value is required (since 26 = 64). Thus, bits [5:0] of the index select a byte lane); and
retrieving the second entry from the second byte lane (from the second byte lane, the byte value (the second entry) is retrieved).
Claims 11, 20, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Sazegari in view of Moyer, Brown, and Valentine.
Referring to claim 11, Sazegari, as modified, has taught the system of claim 10, but has not taught a multiplexer positioned in a data path between the at least two source registers and the index of the destination register, the multiplexer configured to: receive two inputs and the select line; and output one of the two inputs based on the select line. However, Valentine has taught outputting a selected one of two input values by using an index value on a multiplexer select line (e.g. see FIG.14 and paragraph [0133]), where, for example, bit 1421 is used to control multiplexer 1426 to output a selected one of values 1463 and 1464 (other bits are used to control other multiplexers to select between other corresponding values). One of ordinary skill in the art would have recognized that Valentine’s simplistic selection using a multiplexer and the controlling bit (bit seven of each index) could be substituted for Sazegari’s selection involving various shifting steps (column 5, lines 1-40, and FIGs.7a-9). The results of the substitution would have been predictable due to the known operation of a multiplexer, which would allow selection of either a value in V12 or a corresponding value in V34 by using bit seven of the corresponding index as a select line to a multiplexer. An additional benefit of using Valentine’s approach would be the elimination of all of the shifting performed by Sazegari to perform the selection. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have substituted Valentine’s use of a bit as a select line to a multiplexer to output one a selected one of two values for storage into the destination for Sazegari’s shifting for selection. Given this modification, Sazegari, as modified, has taught:
a multiplexer positioned in a data path between the at least two source registers and the index of the destination register (such positioning is required to select among multiple values to write the selected value to the destination register), the multiplexer configured to: receive two inputs and the select line; and output one of the two inputs based on the select line (see FIG.14 of Valentine).
Referring to claim 20, Sazegari, as modified, has taught the method of claim 19, but has not taught the steps of claim 20. However, Valentine has taught selecting between two values by using an index value input into a multiplexer select line (e.g. see FIG.14 and paragraph [0133]), where, for example, bit 1421 is used to control multiplexer 1426 to select between values 1463 and 1464 (other bits are used to control other multiplexers to select between other corresponding values). One of ordinary skill in the art would have recognized that Valentine’s simplistic selection using a multiplexer and the controlling bit (bit seven of each index) could be substituted for Sazegari’s selection involving various shifting steps (column 5, lines 1-40, and FIGs.7a-9). The results of the substitution would have been predictable due to the known operation of a multiplexer, which would allow selection of either a value in V12 or a corresponding value in V34 by using bit seven of the corresponding index as a select line to a multiplexer. An additional benefit of using Valentine’s approach would be the elimination of all of the shifting performed by Sazegari to perform the selection. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have substituted Valentine’s use of a bit as a select line to a multiplexer to select and output one of two values for Sazegari’s shifting for selection. Given the modification, Sazegari, as modified, has taught:
providing the first entry and the second entry as inputs to a multiplexer and providing the value of bit seven of the index in the destination register as a select line to the multiplexer (this is how Sazegari works as modified, with a multiplexer taking in first and second entries and outputting the entry, which is selected based on bit seven, to be written to the destination);
selecting the first entry (see paragraph [0133] and FIG.14 of Valentine. Note that when bit seven contains a particular value, the multiplexer will select the first entry); or
selecting the second entry for overwriting the data included in the index in the destination register based on an output of the multiplexer (see paragraph [0133] and FIG.14 of Valentine. Note that when bit seven contains a different value, the multiplexer will select the second entry. To select this entry for overwriting, the multiplexer must output the value; thus, the selecting for overwriting is based on the output).
Referring to claim 22, Sazegari, as modified, has taught the method of claim 19, but has not taught wherein overwriting the data included in the index in the destination register with the first entry or the second entry based on the value of bit seven of the index in the destination register comprises the steps of claim 22. However, Valentine has taught selecting between two values by using an index value input into a multiplexer select line (e.g. see FIG.14 and paragraph [0133]), where, for example, bit 1421 is used to control multiplexer 1426 to select between values 1463 and 1464 (other bits are used to control other multiplexers to select between other corresponding values). One of ordinary skill in the art would have recognized that Valentine’s simplistic selection using a multiplexer and the controlling bit (bit seven of each index) could be substituted for Sazegari’s selection involving various shifting steps (column 5, lines 1-40, and FIGs.7a-9). The results of the substitution would have been predictable due to the known operation of a multiplexer, which would allow selection of either a value in V12 or a corresponding value in V34 by using bit seven of the corresponding index as a select line to a multiplexer. An additional benefit of using Valentine’s approach would be the elimination of all of the shifting performed by Sazegari to perform the selection. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have substituted Valentine’s use of a bit as a select line to a multiplexer to select and output one of two values for Sazegari’s shifting for selection. Given the modification, Sazegari, as modified, has taught:
inputting the first entry and the second entry to a multiplexer (again, see Valentine’s FIG.14. As modified, Sazegari’s entries would be sent to the multiplexer);
providing the value of bit seven of the index in the destination register as a select line to the multiplexer (as modified, since bit seven controls the selection, this is the bit sent to the multiplexer);
causing the multiplexer to output the first entry in response to the value of bit seven of the index being a first value (see FIG.14 and paragraph [0133] of Valentine. Note that this is how selection via a multiplexer works. Bit seven, when containing one value, will cause the multiplexer to select and output the first entry);
causing the multiplexer to output the second entry in response to the value of bit seven of the index being a second value (see FIG.14 and paragraph [0133] of Valentine. Again, note that this is how selection via a multiplexer works. Bit seven, when containing another value, will cause the multiplexer to select and output the second entry); and
overwriting the data include in the index in the destination register based on an output of the multiplexer (see FIG.14 of Valentine and the explanations above. Sazegari, as modified, would overwrite the data in the index with the entry selected and outputted by the multiplexer based on bit seven control).
Claims 15-16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Sazegari in view of Moyer, Brown, Valentine, and Cheng, U.S. Patent No. 6,243,804.
Referring to claim 15, Sazegari, as modified, has taught the system of claim 11, wherein to overwrite the data included in the index of the destination register, the processor is further configured to execute the instructions to: provide the lookup entry to the multiplexer as a first input of the two inputs (again, see FIG.14 of Valentine (the multiplexer 1426 will receive the lookup entry as a first input); provide the value of bit seven as the select line to the multiplexer (again, from the rejection of claim 11, bit seven would be provided for multiplexer control); and overwrite the data included in the index of the destination register with an output of the multiplexer (again, see the rejection of claim 11).
Sazegari, as modified, has not taught the instructions to: provide an original value of
the index of the destination register to the multiplexer as a second input of the two inputs. However, Valentine also shows a multiplexer selecting between a lookup value and an original value of the destination register to selectively provide the original value in masking situations. See FIG.14, multiplexer 1446, for instance, which can choose between a lookup value or an original value from element 1465 of the destination in response to control 1416 (see paragraph [0134]). Allowing selection of the original value provides additional flexibility to the system to only update the destination where desired. As a result, it would have first been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sazegari to allow for selection of an original value instead of a lookup value for writing to the destination. Thus, in the combination of prior art, there are three selectable options for writing to the register. From FIG.6 of Sazegari and column 5, lines 1-40, either a first lookup entry from V12 or a second lookup entry from V34 may be selected. In addition, the original value in the destination may be selected for re-write to keep that element of the destination register unchanged. To implement such a selection, Cheng has taught a 3-to-1 multiplexer, which selects between three inputs based on two control signals (see FIG.7B and the description thereof). Again, a multiplexer is a known simple component that is used to select among multiple inputs. For a multiplexer with three inputs, at least two control bits are needed for the multiplexer (since one bit can only take on two states and thus only select from among two inputs). One of the control inputs would be bit seven of the index, which selects between the first and second lookup entry. Another control bit needs to be implemented to select between the original value and the selected lookup entry. As a result, to allow for selection among three inputs, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Sazegari’s instructions to provide an original value of the index of the destination register to the multiplexer as a second input of the two inputs.
Referring to claim 16, Sazegari, as modified, has taught the system of claim 15, wherein the lookup entry includes a first lookup entry retrieved while executing a first instruction of the instructions and a second lookup entry retrieved while executing a second instruction of the instructions (see column 5, lines 1-40, of Sazegari and the rejection of claim 15. A first permute instruction provides the first lookup entry to the multiplexer and a second permute instruction provides the second lookup entry to the multiplexer), and wherein the processor is configured to execute the first instruction and the second instruction in combination (see column 5, lines 1-40, and FIG.6. The first and second instructions are executed in combination to start the process to determine VR).
Referring to claim 18, Sazegari, as modified, has taught the system of claim 16, wherein to execute the first instruction and the second instruction in combination, the processor is further configured to: identify the byte lane from a first lookup pair that includes a first source register and a second source register of the at least two source registers while executing the first instruction (see column 5, lines 1-40. A first permute instruction identifies a byte lane from the pair of V1 and V2); and identify the byte lane from a second lookup pair that includes a third source register and a fourth source register of the at least two source registers while executing the second instruction (see column 5, lines 1-40. A second permute instruction identifies a byte lane from the pair of V3 and V4).
Allowable Subject Matter
Claims 9 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
On page 15 of applicant’s response, applicant notes the indication of allowability of claims 9, 17, and 21. However, the examiner notes that claim 21 is no longer indicated as allowable due to amendment thereto.
On pages 16-17 of applicant’s response, applicant has essentially argued that the prior art combination has not taught the claims as amended.
The examiner respectfully disagrees for reasons set forth in the rejections above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183