DETAILED ACTION
Claims 1, 3-11, and 15-24 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 4 is objected to because of the following informalities:
The claim is grammatically incorrect and must be reworded. Specifically, “during” should be used in conjunction with some time/action. A first/second instruction a thing, not a time/action. Thus, during an instruction does not make grammatical sense. Is applicant trying to claim during execution of a first/second instruction?
The examiner also asserts the “wherein…causing…is during” could be improved grammatically to improve readability. The examiner recommends claiming “…wherein: the multiplexer is configured to output the first result in response to the select line being the first value during execution of a first instruction; and…”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 16-24 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Referring to claim 16, there is a positively recited step of overwriting data with a lookup entry by using a value of bit seven (from parent claim 10). Claim 16 sets forth that the lookup entry is both the first lookup entry and the second lookup entry (depending on which instruction is executing). Because bit 7 can only be one value (0 or 1), only one of the first and second lookup entries can be the lookup entry that overwrites the data (because only one would be selected by the mux in response to bit 7 (now in claim 10)). Thus, it is new matter to claim that the lookup entry used in an overwrite includes both lookup entries (meaning, both are written to the index).
Referring to claim 19, applicant now claims overwriting data without using a mask register. However, the examiner cannot find support for such a limitation. Instead, based on at least paragraphs 12-13, 58, and 61 of the specification, applicant appears to explain bit 7 as a mask bit that controls the overwriting (bit 7 masks a value from being used in an overwrite). A destination register storing bit 7 is, thus, a mask register. As such, the overwriting appears to be dependent on using a mask register and to claim otherwise would be new matter unsupported by the original disclosure.
Claims 17-18 and 20-24 are rejected due to their dependence on a claim lacking adequate written description.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 15, line 4, “the lookup entry”, because there is a lookup entry, a first lookup entry, and a second lookup entry in claim 15, i.e., three lookup entries, and it is not clear which applicant is referring to. If applicant is referring to the instance in claim 10, line 11, then a unique word should be used with “lookup entry” in claim 10, line 11, that distinguishes it from the others (e.g. applicant could claim a “lookup table entry”, or “a given lookup entry”).
Claims 16-18 are rejected due to their dependence on an indefinite claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Sazegari (US 6,446,198), in view of Moyer (US 2009/0100253 A1) and Valentine et al. (US 2014/0372727 A1).
Referring to claims 1, Sazegari has taught a system comprising:
a destination register (see FIG.6, VR, and column 5, line 38) and at least two source registers (see FIG.6, V1-V4, and column 4, lines 10-11) storing lookup tables (see the abstract, background, and FIG.3 (which shows an example of a permute operation used in FIG.6). Registers V1-V4 store table data that is looked up via indices in mask register 26); and
a processor (column 3, lines 24-28) configured to perform a register-based lookup by:
retrieving a first result from a first lookup table based on a subset of bits included in an index (see FIGs.3 and 6, where V1-V2 would, during a first permute operation, correspond to data1 and data2 (at least one of which stores a first lookup table). A first result would be obtained using an index in mask 26 and stored in register V12. Only the least significant five bits (bits [4:0]) of the 8-bit index are used to retrieve a given result (because there are 32 total results to choose from across V1 and V2, and five bits allows for selection of one of 32 values (since 25 = 32)));
retrieving a second result from a second lookup table based on the subset of bits included in the index (see FIGs.3 and 6, where V3-V4 would, during a second permute operation, correspond to data1 and data2 (at least one of which stores a second lookup table). A second result would be obtained using the index in mask 26 and stored in register V34 (see column 5, lines 10-11, which set forth that the same index value is used for both retrieval of the first result and second result). Again, only a subset of five bits are used for this retrieval);
selecting the first result or the second result by using a bit in the index of the destination register that is excluded from the subset of bits (as explained, only a subset of five bits of the index are used for each retrieval. Thus, the remaining three bits of an index are unused for the permute operations. Bit [5] (just to the left of the subset of bits [4:0]) is used to select the first or second result from V12 and V34 for final storage in to VR (see column 5, lines 1-40)); and
storing a selected one of the first result or the second result into the destination register (again, see column 5, lines 1-40 and FIG.6. The selected retrieved first or second result is stored into destination register VR).
Sazegari has not taught that the index is of the destination register, nor that the storing of the selected one of the first result or the second result comprises overwriting data included in the index of the destination register. In other words, Sazegari has not taught that the index register 26 is the same as destination register VR. However, Moyer, who has similarly taught register-based lookups (FIG.8), has also taught that the index register and the destination register for looked-up results can be the same register, and that these looked-up results can overwrite the indices in the destination register (note how FIG.8 shows that register rD holds the indices and also serves as the destination with lookup values replacing the indices). One of ordinary skill in the art would have recognized that if the indices are no longer needed at the end of this lookup operation, it is efficient to simply overwrite the indices as opposed to keeping the indices in one register and writing the lookup result to a separate register (utilizing more registers than necessary). As a result, it would have been obvious to one of ordinary skill in the art to modify Sazegari such that VR is both the index register and the destination register such that the indices therein are overwritten by lookup values at the end of the operation of FIG.6. This would constitute efficient register utilization where the indices are no longer needed after the operation of FIG.6.
Sazegari, as modified, has also not taught using the bit in the index of the destination register that is excluded from the subset of bits as a select line to a multiplexer configured to:
receive the first result and an original value of the index as inputs and output the first result in response to the select line being a first value; and
receive the second result and the original value of the index as the inputs and output the second result in response to the select line being a second value.
However, Valentine has taught a 3-to-1 multiplexer selecting between three values (a first value from 1413, a second value from 1414, and an original value from a destination 1415). The 3-to-1 mux comprises two 2-to-1 muxes (e.g. 1426 and 1446) and is controlled by two control bits (e.g. bit 1421 that controls selection of the first or second value, and a bit from 1416 that controls selection of the selected first or second value or the original value) (e.g. see FIG.14 and paragraph [0133]). A 3-to-1 mux would exist for each location of the operands. Valentine provides a way to preserve a destination element, if so desired, thereby increasing flexibility of the system. Further, one of ordinary skill in the art would have recognized that Valentine’s simplistic selection using a multiplexer and a controlling bit (bit [5] of each index) could be substituted for Sazegari’s selection involving various shifting steps (column 5, lines 1-40, and FIGs.7a-9). The results of the substitution would have been predictable due to the known operation of a multiplexer, which would allow selection of either a value in V12 or a corresponding value in V34 by using bit [5] of the corresponding index as a select line to a multiplexer. An additional benefit of using Valentine’s approach would be the elimination of all of the shifting performed by Sazegari to perform the selection. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have substituted Valentine’s use of a bit as a select line to a multiplexer configured to receive the data as claimed. Note that switch network 1403 of Valentine is unnecessary to carry out the operation of Sazegari and would not be part of the prior art combination. In the combination, multiple 3-to-1 multiplexers would exist (one being the combination of 1426 and 1446, another being the combination of 1425 and 1445, and so on). Each 3-to-1 multiplexer would receive as inputs, a first value from Sazegari’s register V12, a second value from Sazegari’s register V34, and an original value from Sazegari’s destination register VR. Bit 5 of a corresponding index would be used as a select line for the 3-to-1 multiplexer, as would an overwrite bit. When the overwrite bit = 0, the original value would be selected by the multiplexer and written back to the destination, thereby preserving the value in the destination. However, when the overwrite bit = 1, bit 5 would dictate which of the first value and second value would be stored to the destination. When bit 5 is a first value, the first result is selected and outputted by the mux. When bit 5 is a second value, the second result is selected and outputted by the mux. This is how Valentine’s 3-to-1 mux would operate when applied to Sazegari.
Referring to claim 3, Sazegari, as modified, has taught the system of claim 1, wherein the index of the destination register includes a byte lane of eight bits (see FIG.3, which shows byte fields in the registers (each index is a byte). Also, see column 4, lines 18-19), and wherein overwriting the data included in the index of the destination register comprises:
overwriting the byte lane with the first result in response to the bit in the index of the destination register that is excluded from the subset of bits including a first value (see column 5, lines 1-40. Bit [5] of the index (which is not part of the subset), when set to a first value, will select the first result to overwrite the index); or
overwriting the byte lane with the second result in response to the bit in the index of the destination register that is excluded from the subset of bits including a second value (see column 5, lines 1-40. Bit [5] of the index, when set to a second value, will select the second result to overwrite the index).
Referring to claim 5, Sazegari, as modified, has taught the system of claim 1, wherein the retrieving the first result from the first lookup table and retrieving the second result from the second lookup table comprises retrieving the first result by executing a first instruction and retrieving the second result by executing a second instruction (see the abstract and column 5, lines 1-20. Basically, there are two permute instructions/operations executed, a first to retrieve a first result from V1 and V2, and a second to retrieve a second result from V3 and V4).
Referring to claim 6, Sazegari, as modified, has taught the system of claim 5, wherein retrieving the first result from the first lookup table by executing the first instruction and retrieving the second result from the second lookup table by executing the second instruction comprises:
while executing the first instruction (the first instruction carries out the operation of FIG.3 on V1 and V2 in FIG.6, with V1 being data1 and V2 being data2):
selecting, as the first lookup table, a first source register or a second source register from the at least two source registers based on one bit of the subset of bits included in the index of the destination register (from FIG.3, note that the fifth bit of a 5-bit subset (bit [4] of subset bits [4:0]) of an 8-bit index selects V1 or V2. That is, if the fifth bit of an index is 0, then it selects V1. If the fifth bit of an index is 1, then it selects V2);
selecting a first byte lane of the selected first source register or the selected second source register based on a remainder of the subset of bits included in the index of the destination register, the remainder excluding the one bit (the lower four bits of the subset (bits [3:0] of the subset) of the index select one of 16 lanes of the selected one of V1 and V2); and
retrieving the first result from the first byte lane (from FIG.3, an index selects a lane and the value therein is retrieved for storage. For example, the rightmost index in register 26 is 0E (which in binary is 00001110). The subset of bits (bits [4:0]) are the five least significant bits, i.e., 01110. The leftmost bit of 0 selects V1 (data1). Then, the remaining bits 1110 select lane E (or lane 14 or the lanes numbers 0 to 15) in V1 to retrieve the value therein to ultimately store that value in a result register 32); and
while executing the second instruction (the second instruction carries out the operation of FIG.3 on V3 and V4 in FIG.6, with V3 being data1 and V4 being data2):
selecting, as the second lookup table, a third source register or a fourth source register from the at least two source registers based on the one bit of the subset of bits included in the index of the destination register (from FIG.3, note that the fifth bit of a 5-bit subset (bit [4] of subset bits [4:0]) of an 8-bit index selects V3 or V4. That is, if the fifth bit of an index is 0, then it selects V3. If the fifth bit of an index is 1, then it selects V4);
selecting a second byte lane of the selected third source register or the selected fourth source register based on the remainder of the subset of bits included in the index of the destination register (the lower four bits of the subset (bits [3:0] of the subset) of the index select one of 16 lanes of the selected one of V3 and V4); and
retrieving the second result from the second byte lane (again, the result is retrieved from the selected lane of the selected register (see the example given above)).
Claims 7-8, 10-11, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Sazegari in view of Moyer, Valentine, and Brown et al. (US 2018/0321937 A1).
Referring to claim 7, Sazegari, as modified, has taught the system of claim 6, but has not taught wherein the subset of bits included in the index of the destination register includes bits [6:0] of an eight-bit index, wherein: the one bit of the subset of bits is bit six of the eight-bit index; and the remainder of the subset of bits include bits [5:0] of the eight-bit index. Instead, as explained above, Sazegari’s subset includes bits [4:0] of an 8-bit index, wherein the one of the subset of bits is bit [4] of the index, and the remainder of the subset of bits includes bits [3:0] of the index. However, this is because each register is only 128-bits wide, with each register storing 16 bytes. However, Brown has taught implementing registers of various sizes with varying element sizes therein. For instance, Brown has taught 512-bit registers with 64 bytes (see FIG.8 and paragraph [0069] and note the 512-bit zmm registers). The examiner notes that by increasing the size of the registers in Sazegari, larger lookup tables could be implemented with more efficiency because more values can be looked up at once. In addition, a change in size is deemed by the court(s) to constitute a routine expedient and not a patentable distinction, particularly absent some demonstration of the criticality of the claimed size (see MPEP 2144.04, including section IV(A)). As a result, to allow for larger lookup tables, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sazegari such that the registers involved with a permute instruction are 512-bit registers holding 64 bytes as opposed to 128-bit registers holding 16 bytes. With larger registers and more bytes, the subset of the index also has to be changed. That is, the subset would be bits [6:0] (to identify one of 128 total lanes among two registers), with bit [6] selecting a first 512-bit register (V1) or a second 512-bit register (V2). Bits [5:0] of the index would select one of the 64 bytes in the register corresponding to the value of bit [6].
Referring to claim 8, Sazegari, as modified, has taught the system of claim 6, wherein the index of the destination register includes an eight-bit index (again, from FIG.3, each index includes eight bits), and wherein overwriting the data included in the index of the destination register using the selected one of the first result or the second result comprises:
overwriting the data included in the index of the destination register with the first result in response to bit six of the eight-bit index being a first value while executing the first instruction (see column 5, lines 1-40. While the first permute instruction related to V1 and V2 in FIG.6 is being executed, the index’s 6th bit, i.e., bit [5], when equal to a first value, will cause a corresponding value from V1/V2 to overwrite a corresponding index in VR); or
overwriting the data included in the index of the destination register with the second result in response to the bit six of the eight-bit index being a second value while executing the second instruction (see column 5, lines 1-40. While the second permute instruction related to V3 and V4 in FIG.6 is being executed, the index’s 6th bit, i.e., bit [5], when equal to a second value, will cause a corresponding value from V3/V4 to overwrite a corresponding index in VR).
Sazegari has not taught that the overwriting is based on bit seven of the eight-bit index. However, for similar reasoning as set forth for claim 7, it is obvious to increase the register size to 512 bits (for holding 64 bytes). Then, the first unused bit is bit [7] (the leftmost bit of the index), not bit [5].
Referring to claim 10, Sazegari has taught a system comprising:
a mask register storing indices (see FIG.6, VR, and column 5, line 38) and at least two source registers (see FIG.6, V1-V4, and column 4, lines 10-11) storing lookup tables (see the abstract, background, and FIG.3 (which shows an example of a permute operation used in FIG.6). Registers V1-V4 store table data that is looked up via indices in mask register 26)); and
a processor (column 3, lines 24-36) configured to execute instructions (abstract) to:
access the mask register and the at least two source registers (see FIG.3. Note that this operation is what is performed on registers V1 and V2 in FIG.6 and again on registers V3 and V4 in FIG.6 (see column 5, lines 1-40)); and
for an index of the mask register:
identify a byte lane of the at least two source registers based on bits [4:0] of the index of the mask register (again, see FIG.3 and FIG.6 and column 5, lines 1-40. When performing a lookup on V1 (data1) and V2 (data2), the five least significant bits (bits [4:0]) of an 8-bit index in register 26 identify a single lane of the 32 lanes in V1 and V2); and
storing a lookup entry defined in the identified byte lane by using a value of bit five of the index of the mask register (again, see column 5, lines 1-40, and FIG.6. The lookup entry identified by the five least significant bits (bits [4:0]) of the index, is then stored to VR based on bit [5] of the index (which is the sixth bit of the index since the numbering starts with bit 0). Note that even though bit [5] is in a mask register 26, it is only bit [5] that controls the storage of the lookup entry. Thus, the storage is independent of data maintained in the mask register, i.e., independent of bits other than bit [5]. Additionally, from FIG.12 and column 7, line 1, there are multiple mask registers in the system and the storage would only be based on mask register 26, and not any of the other mask registers (hence, the storing is also independent of the data maintained in these other mask registers)).
Sazegari has not taught that the mask register is also the destination register, nor that the storing of the lookup entry defined in the identified byte lane comprises overwriting data included in the index of the destination register. In other words, Sazegari has not taught that index register 26 (column 4, lines 10-11) is the same as destination register VR (FIG.6). However, Moyer, who has similarly taught register-based lookups (FIG.8), has also taught that the index register and the destination register for looked-up results can be the same register, and that these looked-up results can overwrite the indices in the destination register (note how FIG.8 shows that register rD holds the indices and also serves as the destination with lookup values replacing the indices). One of ordinary skill in the art would have recognized that if the indices are no longer needed at the end of this lookup operation, it is efficient to simply overwrite the indices as opposed to keeping the indices in one register and writing the lookup result to a separate register (utilizing more registers than necessary). As a result, it would have been obvious to one of ordinary skill in the art to modify Sazegari such that VR is both the index register and the destination register such that the indices therein are overwritten by lookup values at the end of the operation of FIG.6. This would constitute efficient register utilization where the indices are no longer needed after the operation of FIG.6.
Sazegari has also not taught that the byte lane is identified based on bits [6:0] of the index, nor that the overwriting is based on a value of bit seven of the index. However, this is because each register in Sazegari is only 128-bits wide, with each register storing 16 bytes. However, Brown has taught implementing registers of various sizes with varying element sizes therein. For instance, Brown has taught 512-bit registers with 64 bytes (see FIG.8 and paragraph [0069] and note the 512-bit zmm registers). The examiner notes that by increasing the size of the registers in Sazegari, larger lookup tables could be implemented with more efficiency because more values can be looked up at once. In addition, a change in size is deemed by the court(s) to constitute a routine expedient and not a patentable distinction (absent some demonstration of the criticality of the claimed size). See MPEP 2144.04, including section IV(A). As a result, to allow for larger lookup tables, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sazegari such that the registers involved with a permute instruction are 512-bit registers holding 64 bytes as opposed to 128-bit registers holding 16 bytes. With larger registers and more bytes, the bits used in the index also have to be changed. That is, the bits identifying the byte lane would be bits [6:0] (to identify one of 128 total lanes among two registers), with bit #6 selecting a first 512-bit register (V1) or a second 512-bit register (V2). Bits [5:0] of the index would select one of the 64 bytes in the register corresponding to the value of bit #6. This means that bit seven (among bits [7:0] in the index) is responsible for controlling which value overwrites the index.
Finally, Sazegari, as modified, has also not taught using bit seven of the index of the destination register as a select line to a multiplexer configured to:
receive a first lookup entry and an original value of the index as inputs and output the first lookup entry in response to the select line being a first value; and
receive a second lookup entry and the original value of the index as the inputs and output the second lookup entry in response to the select line being a second value.
However, Valentine has taught a 3-to-1 multiplexer selecting between three values (a first value from 1413, a second value from 1414, and an original value from a destination 1415). The 3-to-1 mux comprises two 2-to-1 muxes (e.g. 1426 and 1446) and is controlled by two control bits (e.g. bit 1421 that controls selection of the first or second value, and a bit from 1416 that controls selection of the selected first or second value or the original value) (e.g. see FIG.14 and paragraph [0133]). A 3-to-1 mux would exist for each location of the operands. Valentine provides a way to preserve a destination element, if so desired, thereby increasing flexibility of the system. Further, one of ordinary skill in the art would have recognized that Valentine’s simplistic selection using a multiplexer and a controlling bit (bit [5] of each index) could be substituted for Sazegari’s selection involving various shifting steps (column 5, lines 1-40, and FIGs.7a-9). The results of the substitution would have been predictable due to the known operation of a multiplexer, which would allow selection of either a lookup entry in V12 or a corresponding lookup entry in V34 by using bit [5] of the corresponding index as a select line to a multiplexer. An additional benefit of using Valentine’s approach would be the elimination of all of the shifting performed by Sazegari to perform the selection. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have substituted Valentine’s use of a bit as a select line to a multiplexer configured to receive the data as claimed. Note that switch network 1403 of Valentine is unnecessary to carry out the operation of Sazegari and would not be part of the prior art combination. In the combination, multiple 3-to-1 multiplexers would exist (one being the combination of 1426 and 1446, another being the combination of 1425 and 1445, and so on). Each 3-to-1 multiplexer would receive as inputs, a first lookup entry from Sazegari’s register V12, a second lookup entry from Sazegari’s register V34, and an original value from Sazegari’s destination register VR. Bit 5 of a corresponding index would be used as a select line for the 3-to-1 multiplexer, as would an overwrite bit. When the overwrite bit = 0, the original value would be selected by the multiplexer and written back to the destination, thereby preserving the value in the destination. However, when the overwrite bit = 1, bit 5 would dictate which of the first lookup entry and second lookup entry would be stored to the destination. When bit 5 is a first lookup entry, the first result is selected and outputted by the mux. When bit 5 is a second lookup entry, the second result is selected and outputted by the mux. This is how Valentine’s 3-to-1 mux would operate when applied to Sazegari.
Referring to claim 11, Sazegari, as modified, has taught the system of claim 10, wherein the multiplexer is positioned in a data path between the at least two source registers and the index of the destination register (see Valentine (FIG.14)).
Referring to claim 15, Sazegari, as modified, has taught the system of claim 11, wherein to overwrite the data included in the index of the destination register, the processor is further configured to execute the instructions to:
provide the lookup entry to the multiplexer as a first input (again, the combination will include a 3-to-1 mux that receives a lookup entry as a first input);
provide the original value of the index of the destination register to the multiplexer
as a second input (again, in the combination, the mux will receive an original value from the destination);
provide the value of bit seven as the select line to the multiplexer (again, from the rejection of claim 11, bit seven would be provided for multiplexer control); and
overwrite the data included in the index of the destination register with an output of the multiplexer (again, see the rejection of claim 11).
Claims 19, 21, and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Sazegari in view of Moyer and Brown, and, optionally in view of Valentine and Le et al. (US 2006/0184767).
Referring to claim 19, Sazegari has taught a method comprising:
accessing a destination register (see FIG.3, register 26 and column 4, lines 10-11. This register is a destination for indices to be written) and a plurality of source registers (see FIG.3, source registers data1 and data2, and column 4, lines 11-12. Also, see FIG.6 and column 5, lines 1-40, and source registers V1, V2, V3, and V4, which correspond to data1, data2, data1, and data2, respectively), the destination register storing indices for retrieving a combination of entries from the plurality of source registers (again, see FIG.3 and the description thereof. Also, see FIG.6 and the description thereof); and
for at least one of the indices of the destination register:
retrieving a first entry identified by bits [4:0] of an index in the destination register from a first lookup table that is stored in the plurality of source registers (again, see FIG.3 and FIG.6 and column 5, lines 1-40. The least significant five bits, i.e., bits [4:0] of an 8-bit index in register 26 identifies a single entry from a first lookup table stored in the two source registers (in FIG.6, the two source registers are V1 and V2). If V1 includes the values shown in data1 from FIG.3, V2 includes the values shown in data2 in FIG.3, and the indices for the operation of FIG.6 are the values shown in FIG.3, then an example of retrieving the first entry would be taking the rightmost index of 0E (00001110 in binary) in FIG.3. Bits [4:0] of this index are 01110. The leftmost bit indicates the source register (0 = V1/data1, 1 = V2/data2). The rightmost 4 bits indicate the exact entry in the indicated source register (1110 = 14, so choose entry #14 (E) among entries numbered 0 to 15));
retrieving a second entry identified by the bits [4:0] of the index in the destination register from a second lookup table that is stored in the plurality of source registers (again, see column 5, lines 1-40. The second permute instruction/operation involving V3 and V4 uses the same index register used by the first permute instruction/operation involving V1 and V2. Thus, bits [4:0] of the same index will retrieve second entry from a second lookup table stored in V3 and V4); and
storing, in a result register, the first entry or the second entry based on a value of bit five of the index in the destination register (again, see column 5, lines 1-40 and FIG.6. The first or second entry is stored to result register VR based on bit [5] (the bit just to the left of bits [4:0]) of the index).
Sazegari has not taught the storing comprises overwriting data included in the index in the destination register with the first entry or the second entry. In other words, Sazegari has not taught that register 26 is the same as register VR. However, Moyer, who has similarly taught register-based lookups (FIG.8), has also taught that the index register and the destination register for looked-up results can be the same register, and that these looked-up results can overwrite the indices in the destination register (note how FIG.8 shows that register rD holds the indices and also serves as the destination with lookup values replacing the indices). One of ordinary skill in the art would have recognized that if the indices are no longer needed at the end of this lookup operation, it is efficient to simply overwrite the indices as opposed to keeping the indices in one register and writing the lookup result to a separate register (utilizing more registers than necessary). As a result, it would have been obvious to one of ordinary skill in the art to modify Sazegari such that VR is both the index register and the destination register such that the indices therein are overwritten by lookup values at the end of the operation of FIG.6. This would constitute efficient register utilization where the indices are no longer needed after the operation of FIG.6.
Sazegari has also not taught that the first entry and the second entry are identified by the bits [6:0] of the index, nor that the overwriting is based on a value of bit seven of the index. However, this is because each register in Sazegari is only 128 bits wide, with each register storing 16 bytes. However, Brown has taught implementing registers of various sizes with varying element sizes therein. For instance, Brown has taught 512-bit registers with 64 bytes (see FIG.8 and paragraph [0069] and note the 512-bit zmm registers). The examiner notes that by increasing the size of the registers in Sazegari, larger lookup tables could be implemented with more efficiency because more values can be looked up at once. In addition, a change in size is deemed by the court(s) to constitute a routine expedient and not a patentable distinction, particularly absent some demonstration of the criticality of the claimed size (see MPEP 2144.04, including section IV(A)). As a result, to allow for larger lookup tables, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sazegari such that the registers involved with a permute instruction are 512-bit registers holding 64 bytes as opposed to 128-bit registers holding 16 bytes. With larger registers and more bytes, the bits used in the index also have to be changed. That is, the bits identifying the byte lane would be bits [6:0] (to identify one of 128 total lanes among two registers), with bit #6 selecting a first 512-bit register (V1) or a second 512-bit register (V2). Bits [5:0] of the index would select one of the 64 bytes in the register corresponding to the value of bit #6. This means that bit seven (among bits [7:0] in the index) is responsible for controlling which value overwrites the index.
With respect to overwriting without using a mask register, this is not patentable for multiple reasons:
First, even though bit 7 may appear in a mask register to control selection of a value, from FIG.12 and column 7, line 1, there are multiple mask registers in the system and the overwriting would only be based on one mask register, and not any of the other mask registers (hence, the overwriting is performed without using a mask register). Valentine and Le are not required under this interpretation.
Secondly, where the claimed overwriting is interpreted to use zero mask registers, Sazegari, as modified, has not taught such overwriting. However, for reasoning given in the rejection of claim 1 above, it would have first been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sazegari to implement a multiplexer to select the value to write to the destination (note that this could include either modifying Sazegari to include the 3-to-1 mux to allow for preservation of the original destination value, or because claim 19 makes no mention of such an original value, modifying Sazegari to include only a simple 2-to-1 multiplexer (e.g. Valentine, FIG.14, 1426) to select only from among the two lookup table entries while simultaneously implementing less hardware than required by a 3-to-1 multiplexer). Furthermore, Le, in FIG.3 and the description thereof, has taught that multiplexer controls can simply be latched (temporarily held) in a latch 322, which is a stand-alone latch coupled to multiplexers 330, 332, etc., and not a register to store normal data/masks for processing. One of ordinary skill in the art would have recognized that this would be a suitable substitute to control a multiplexer in a predictable way and to realize the same result in Sazegari. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the latch control in Le for any mask created in Sazegari. In the combination, bit 7 from register 26 will simply be sent to a latch (Le, FIG.3, 322) to control a multiplexer to select an appropriate value. This will replace Sazegari’s generation of a mask through various shifting operations to control selection (column 4, line 59, to column 5, line 67).
Referring to claim 21, Sazegari, as modified, has taught the method of claim 19, wherein overwriting the data included in the index in the destination register with the first entry or the second entry based on the value of bit seven of the index in the destination register comprises:
overwriting the data included in the index in the destination register with the first entry in response to the value of bit seven of the index in the destination register being a first value (as modified, the first entry overwrites data in register VR based on bit [7] being a particular (first) value); or
overwriting the data included in the index in the destination register with the second entry in response to the value of bit seven of the index in the destination register being a second value (this limitation, though not required due to the “or” language, is still taught by Sazegari, as modified, where the first entry overwrites data in register VR based on bit [7] being the opposite of the first value, i.e., a second value).
Referring to claim 23, Sazegari, as modified, has taught the method of claim 19, wherein retrieving the first entry identified by bits [6:0] of the index in the destination register from the first lookup table that is stored in the plurality of source registers comprises:
selecting, as the first lookup table, a first source register or a second source register of the plurality of source registers based a value of bit six of the index in the destination register (again, as modified, Sazegari’s registers are 512-bit registers with 64 bytes each. To carry out the first permute of FIG.6, bit [6] is used to select the first lookup table among V1 and V2);
selecting a first byte lane of the first lookup table based on bits [5:0] of the index in the destination register (as modified, to select one of 64 bytes from the selected one of V1 and V2, a 6-bit value is required (since 26 = 64). Thus, bits [5:0] of the index select a byte lane); and
retrieving the first entry from the first byte lane (from the selected byte lane, the byte value (the first entry) is retrieved).
Referring to claim 24, Sazegari, as modified, has taught the method of claim 23, wherein retrieving the second entry identified by the bits [6:0] of the index in the destination register from the second lookup table that is stored in the plurality of source registers comprises:
selecting, as the second lookup table, a third source register or a fourth source register of the plurality of source registers based on the value of bit six of the index in the destination register (again, as modified, Sazegari’s registers are 512-bit registers with 64 bytes each. To carry out the second permute of FIG.6, which uses the same index as the first permute, bit [6] is used to select the second lookup table among V3 and V4);
selecting a second byte lane of the second lookup table based on the bits [5:0] of the index in the destination register (as modified, to select one of 64 bytes from the selected one of V3 and V4, a 6-bit value is required (since 26 = 64). Thus, bits [5:0] of the index select a byte lane); and
retrieving the second entry from the second byte lane (from the second byte lane, the byte value (the second entry) is retrieved).
Claims 20 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Sazegari in view of Moyer, Brown, Valentine, and Le.
Referring to claim 20, Sazegari, as modified (including by Valentine and Le), has taught the method of claim 19, further comprising:
providing the first entry and the second entry as inputs to a multiplexer and providing the value of bit seven of the index in the destination register as a select line to the multiplexer (this is how Sazegari works as modified, with a multiplexer taking in first and second entries and outputting the entry, which is selected based on bit seven, to be written to the destination);
selecting the first entry (see paragraph [0133] and FIG.14 of Valentine. Note that when bit seven contains a particular value, the multiplexer will select the first entry); or
selecting the second entry for overwriting the data included in the index in the destination register based on an output of the multiplexer (see paragraph [0133] and FIG.14 of Valentine. Note that when bit seven contains a different value, the multiplexer will select the second entry. To select this entry for overwriting, the multiplexer must output the value; thus, the selecting for overwriting is based on the output).
Referring to claim 22, Sazegari, as modified (including by Valentine and Le), has taught the method of claim 19, wherein overwriting the data included in the index in the destination register with the first entry or the second entry based on the value of bit seven of the index in the destination register comprises:
inputting the first entry and the second entry to a multiplexer (again, see Valentine’s FIG.14. As modified, Sazegari’s entries would be sent to the multiplexer);
providing the value of bit seven of the index in the destination register as a select line to the multiplexer (as modified, since bit seven controls the selection, this is a bit sent to the multiplexer);
causing the multiplexer to output the first entry in response to the value of bit seven of the index being a first value (see FIG.14 and paragraph [0133] of Valentine. Note that this is how selection via a multiplexer works. Bit seven, when containing one value, will cause the multiplexer to select and output the first entry);
causing the multiplexer to output the second entry in response to the value of bit seven of the index being a second value (see FIG.14 and paragraph [0133] of Valentine. Again, note that this is how selection via a multiplexer works. Bit seven, when containing another value, will cause the multiplexer to select and output the second entry); and
overwriting the data include in the index in the destination register based on an output of the multiplexer (see FIG.14 of Valentine and the explanations above. Sazegari, as modified, would overwrite the data in the index with the entry selected and outputted by the multiplexer based on bit seven control).
Allowable Subject Matter
Claims 4, 9, and 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable over the prior art if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Note that any amendments to address 112 rejections may affect allowability of at least one of these claims.
Response to Arguments
On pages 14-15 of applicant’s response, applicant argues that the examiner’s interpretation of “mask register” is beyond broadest reasonable interpretation.
The examiner respectfully disagrees. Key sentences in paragraphs 12-13 of the specification include “Each mask register is generated based on the value of bit seven.” and “In accordance with the described techniques, the permute instructions utilize all eight bits of data stored in a destination register index as input in order to access source registers without requiring additional mask instructions or mask registers, as required by previous approaches.” In other words, applicant appears to have support for not generating an additional mask register value based on the value of bit 7. However, this does not mean that the register including bit 7 is not a mask register. Applicant’s bit 7 masks values that are not to be written to the destination. Thus, the register including a mask bit is a mask register and, therefore, a mask register is used in the decision to overwrite. In other words, applicant’s specification describes using one mask register (the one containing mask bit 7) but not using an additional mask register generated based on bit 7. As such, the new matter rejection of claim 19 is maintained. The new matter rejection for claims 1 and 10 has been withdrawn in response to applicant’s amendments.
Applicant argues that the prior art has not taught claims 1 and 10 as amended.
The examiner respectfully disagrees for reasons set forth in the updated rejections.
On page 19 of applicant’s response, applicant argues that Sazegari uses a mask register to select between two values and, thus, the “without using a mask register” limitation is not taught by the prior art.
The examiner first notes the breadth of the negative limitation. There are multiple mask registers in Sazegari and at least one is not needed to perform the method of claim 19; thus, Sazegari has taught overwriting without using a mask register. Alternatively, it would have been obvious to latch the mux control signals as opposed to storing them in a mask register per se.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Abedifard (US 6,445,625) is evidence that a chain of two 2-to-1 muxes forms a 3-to-1 mux (FIG.6A and column 13, lines 37-40). This supports the examiner calling the sequence of muxes in FIG.14 of Valentine a 3-to-1 mux.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
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