DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action responds to the Application filed on 12/30/2022. Claims 1-21 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1,3-4,8,10-11,15,17-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chakrabarty et al. (US Patent No. 8,832,608 B1).
As per claims 1,8,15, Fig. 5 illustrates the elements of the claims, comprising:
the register-transfer level (RTL) design defining operations of electrical circuits in a first and second dice of a multi-die semiconductor package in which the second die to be stacked on the first die in the multi-die semiconductor package, is synthesized or obtained at step 500 (the synthesized RTL design contain structural circuit definition which includes circuit elements and interconnection paths spanning across multi-die in a 3D stack –see col. 7, line 65 to col. 8, line 6; see also Fig. 1, wherein Die 1 is stacked on top of Die 1—col. 3, lines 48-56)
select placement of a cell for a physical layout for the multi-die semiconductor package based on the register-transfer level design, the cell including a via to electrically interconnect the first die to the second die is performed in steps 520-560 to stratify timing constraints (i.e., selective placement of GSFs (gate scan flop) and through-silicon via (TSV) to electrically interconnect the paths from one die to another as shown in Fig. 1 to satisfy die level and inter-die level timing constraints; see also col. 8, line 77 to col. 9, line 35); wherein the apparatus comprising at least a memory or one non-transitory computer-readable storage medium, processor circuitry, machine-readable instructions, are illustrated in Fig. 3 (see also col. 6. Lines 8-45).
As per claims 3,10, 17, multi-die semiconductor further includes a third die and the select placement further extends to the third through a silicon via (i.e.,TSV) (see col. 12, line 6 to col. 13, line 67).
As per claims 4,11,18, the determination of characteristics of the cell, the connected cells coupled to the cell, and selection of one or more additional cells based on the comparison of the characteristics (i.e., characteristics being timing slack or delay—see col. 7, lines 1-64, which are performed for die level as well as inter-die levels--see col. 12, line 6 to col. 13, line 67).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 9, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chakrabarty et al. (US Patent No. 8,832,608 B1).in view of. Seidemann et al. (US Patent Application Publication No. 2018/0331070 A1).
As per claims 2, 9, 16, Chakrabarty et al. disclose all of the elements of claims 1, 8 and 15, from which the respective claims depend, as discussed in the rejection of claims 1, 8, 15 above, including the multi-die semiconductor further includes a third die and the select placement further extends to the third through a via (i.e., TSV) (see col. 12, line 6 to col. 13, line 67). However, Chakrabarty et al. failed to teach that the via is a through mold via. The use of through Silicon Via (TSV) and through mold via (TMV) for interconnections between stacked dies are known in the art as further taught by Seidemann et al. (see abstract; paragraphs [0033], [0040]). It would have been obvious to one of ordinary skilled in the art at the time of the effective filing date of Applicant’s invention to further incorporate the teachings using TMV as well as TVS for inter-dies interconnections of Seidemann et al. into the method/system of Chakrabarty et al. because such incorporation would further allow inter-dies interconnection of Chakrabarty et al. as known in the art and further taught by Seidemann et al..
Claim(s) 5,12,19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chakrabarty et al. (US Patent No. 8,832,608 B1).in view of. Chang et al. (US Patent Application Publication No. US 20200020635 A1).
As per claims 5,12,19, Chakrabarty et al. disclose all of the elements of claims 1, 8 and 15, from which the respective claims depend, as discussed in the rejection of claims 1, 8, 15 above, determining timing based characteristics and selection of a second via based on the timing characteristics based on the timing greater than a threshold (i.e., does not meet the timing constraints) and placement and routing of the second via (see col. 7, lines 1-64, which are performed for die level as well as inter-die levels). However, Chakrabarty et al. failed to teach that the characteristics being resistance and that the placement and routing of the second via is in parallel to the first via. Chang et al. teaches 3D IC structure using various vias such as TSVs, TDVs (i.e., stacked dies—paragraph [0002]) for interconnecting the dies (see paragraph [0016]) in which vias are placed parallel to each other to reduce electrical resistance between the wires (see paragraphs [0020], [0039]-[0041]). It would have been obvious to one of ordinary skilled in the art at the time of effective filing of date of Applicant’s invention to further incorporate the teachings of Chang et al. into the method/system of Chakrabarty et al. to determine the characteristics being resistances and placing/routing the vias in parallel to each other as further taught by Chang et al. so that proper interconnections are made between the dies by reducing the resistances below the threshold.
Claim(s) 6-7,13-14,20-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chakrabarty et al. (US Patent No. 8,832,608 B1).in view of Uzoh (US Patent Application Publication No. 2016/0343613 A1).
As per claims 6-7, 13-14, 20-21, Chakrabarty et al. disclose all of the elements of claims 1, 8 and 15, from which the respective claims depend, as discussed in the rejection of claims 1, 8, 15 above, including placement of a via based on a second placement of another via (TSV) on the second die (see Fig. 1, placement of TSV 104 on die 0 corresponding to placement of TSV 114 on Die 1 to satisfy timing constraints; see also col. 4, lines 12-51). However, Chakrabarty et al. failed to teach that one of the via placement is a through dielectric via placement. The use of through Silicon Via (TSV) and through dielectric via (TDV) for interconnections between stacked dies are known in the art as further taught by Uzoh (see abstract; paragraphs [0021]-[0023], [0050]-[0051]). It would have been obvious to one of ordinary skilled in the art at the time of the effective filing date of Applicant’s invention to further incorporate the teachings using TDV as well as TVS for inter-dies interconnections of Uzoh into the method/system of Chakrabarty et al. because such incorporation would further allow inter-dies interconnection of Chakrabarty et al. as known in the art and further taught by Uzoh.
Conclusion
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/PHALLAKA KIK/Primary Examiner, Art Unit 2851 January 24, 2026