DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1, 5, 11 and 15 are objected to because of the following informalities:
In claim 1, lines 12, “wherein the thin-film transistor area further comprises …” should read --wherein the thin-film transistor area comprises …--.
In claim 1, lines 13-14, “on the second insulating layer” should read --on a second insulating layer--.
In claim 5, lines 1-2, “wherein the thin-film transistor area comprises …” should read -- wherein the thin-film transistor area further comprises …--.
In claim 5, line 4, “a second insulating layer” should read --the second insulating layer--.
In claim 11, line 13, “wherein the thin-film transistor area further comprises …” should read --wherein the thin-film transistor area comprises …--.
In claim 11, lines 14-15, “on the second insulating layer” should read --on a second insulating layer--.
In claim 15, lines 1-2, “wherein the thin-film transistor area comprises …” should read -- wherein the thin-film transistor area further comprises …--.
In claim 15, line 4, “a second insulating layer” should read --the second insulating layer--
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4, 5, 7, 11, 12, 14, 15 and 17 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Sakurai et al. US 2008/0067519.
Regarding claim 1, Sakurai teaches an array substrate (e.g., Fig. 5, [5]-[12]), comprising a thin-film transistor area (e.g., thin-film transistor area including the pixel TFT portion, Fig. 5) and a capacitance area (e.g., capacitance area including the capacitor portion, Fig. 5) located around the thin-film transistor area, wherein the capacitance area comprises:
a substrate (e.g., 10, Fig. 5);
a first insulating layer (e.g., 56C in the capacitance area (discussed above), Fig. 5) arranged on the substrate, wherein a plurality of first grooves (e.g., first grooves in which 58 is disposed, Fig. 5) are defined on the first insulating layer; and
a first storage capacitor (e.g., capacitor including 58 and 55 in the capacitance area (discussed above), Fig. 5), wherein the first storage capacitor comprises a first electrode plate (e.g., 55 in the capacitance area (discussed above), Fig. 5) and a second electrode plate (e.g., 58, Fig. 5) arranged opposite and insulated from the first electrode plate, the first electrode plate is arranged on the substrate (e.g., Fig. 5), and the second electrode plate is located at a side of the first insulating layer away from the substrate and is partially filled in the plurality of first grooves (e.g., Fig. 5);
wherein the thin-film transistor area further comprises a passivation layer (e.g., 19, Fig. 5) and a planarization layer (e.g., 22, Fig. 5), and a plurality of second grooves (e.g., second grooves on 56, Fig. 5) are defined on the second insulating layer (e.g., 56 in the thin-film transistor area (discussed above), Fig. 5); wherein the passivation layer is arranged on a side of the second insulating layer away from the substrate (e.g., Fig. 5), and the passivation layer is filled in the plurality of second grooves (e.g., Fig. 5); and wherein the planarization layer is arranged on a side of the passivation layer away from the second insulating layer (e.g., Fig. 5).
Regarding claim 2, Sakurai teaches the array substrate according to claim 1, wherein the capacitance area further comprises a buffer layer (e.g., 53, Fig. 5), the buffer layer is arranged on the substrate (e.g., Fig. 5), and the first electrode plate (e.g., 55 in the capacitance area (discussed above), Fig. 5) is located on a side of the buffer layer away from the substrate (e.g., Fig. 5).
Regarding claim 4, Sakurai teaches the array substrate according to claim 1, wherein the capacitance area further comprises a buffer layer (e.g., 21, Fig. 5), the buffer layer is arranged on the substrate (e.g., Fig. 5), and the first electrode plate (e.g., 55 in the capacitance area (discussed above), Fig. 5) is located between the buffer layer and the substrate (e.g., Fig. 5).
Regarding claim 5, Sakurai teaches the array substrate according to claim 1, wherein the thin-film transistor area comprises a thin-film transistor structure (e.g., pixel TFT, Fig. 5), and the thin-film transistor structure comprises an active layer (e.g., 55 in the thin-film transistor area (discussed above)), a gate electrode (e.g., 57, Fig. 5), a source electrode (e.g., 20S, Fig. 5), a drain electrode (e.g., 20D, Fig. 5), and a second insulating layer (e.g., 56 in the thin-film transistor area (discussed above), Fig. 5); wherein a first contact hole (e.g., CH2, Fig, 5) and a second contact hole (e.g., CH1, Fig. 5) are defined on the second insulating layer, the source electrode and the drain electrode are arranged on the second insulating layer (e.g., Fig, 5), and the source electrode and the drain electrode are respectively connected with the active layer through the first contact hole and the second contact hole (e.g., Fig, 5); and wherein the first insulating layer is arranged on a same layer as the second insulating layer (e.g., Fig, 5).
Regarding claim 7, Sakurai teaches the array substrate according to claim 5, wherein the active layer and the first electrode plate are made of a same material and are located in a same layer (e.g., Fig. 5).
Regarding claim 11, Sakurai teaches a display panel (e.g., [2]), wherein the display panel comprises an array substrate (e.g., Fig. 5, [5]-[12]), comprising a thin-film transistor area (e.g., thin-film transistor area including the pixel TFT portion, Fig. 5) and a capacitance area (e.g., capacitance area including the capacitor portion, Fig. 5) located around the thin-film transistor area, wherein the capacitance area comprises:
a substrate (e.g., 10, Fig. 5);
a first insulating layer (e.g., 56C in the capacitance area (discussed above), Fig. 5) arranged on the substrate, wherein a plurality of first grooves (e.g., first grooves in which 58 is disposed, Fig. 5) are defined on the first insulating layer; and
a first storage capacitor (e.g., capacitor including 55 and 58 in the capacitance area (discussed above), Fig. 5), wherein the first storage capacitor comprises a first electrode plate (e.g., 55 in the capacitance area (discussed above), Fig. 5) and a second electrode plate (e.g., 58, Fig. 5) arranged opposite and insulated from the first electrode plate, the first electrode plate is arranged on the substrate (e.g., Fig. 5), and the second electrode plate is located at a side of the first insulating layer away from the substrate and is partially filled in the plurality of first grooves (e.g., Fig. 5);
wherein the thin-film transistor area further a passivation layer (e.g., 19, Fig. 5) and a planarization layer (e.g., 22, Fig. 5), and a plurality of second grooves (e.g., second grooves on 56, Fig. 5) are defined on the second insulating layer (e.g., 56 in the thin-film transistor area (discussed above), Fig. 5); wherein the passivation layer is arranged on a side of the second insulating layer away from the substrate (e.g., Fig. 5), and the passivation layer is filled in the plurality of second grooves (e.g., Fig. 5); and wherein the planarization layer is arranged on a side of the passivation layer away from the second insulating layer (e.g., Fig. 5).
Regarding claim 12, Sakurai teaches the display panel according to claim 11, wherein the capacitance area further comprises a buffer layer (e.g., 53, Fig. 5), the buffer layer is arranged on the substrate (e.g., Fig. 5), and the first electrode plate (e.g., 55 in the capacitance area (discussed above), Fig. 5) is located on a side of the buffer layer away from the substrate (e.g., Fig. 5).
Regarding claim 14, Sakurai teaches the display panel according to claim 11, wherein the capacitance area further comprises a buffer layer (e.g., 21, Fig. 5), the buffer layer is arranged on the substrate (e.g., Fig. 5), and the first electrode plate (e.g., 55 in the capacitance area (discussed above), Fig. 5) is located between the buffer layer and the substrate (e.g., Fig. 5).
Regarding claim 15, Sakurai teaches the display panel according to claim 11, wherein the thin-film transistor area comprises a thin-film transistor structure (e.g., pixel TFT, Fig. 5), and the thin-film transistor structure comprises an active layer (e.g., 55 in the thin-film transistor area (discussed above)), a gate electrode (e.g., 57, Fig. 5), a source electrode (e.g., 20S, Fig. 5), a drain electrode (e.g., 20D, Fig. 5), and a second insulating layer (e.g., 56 in the thin-film transistor area (discussed above), Fig. 5); wherein a first contact hole (e.g., CH2, Fig, 5) and a second contact hole (e.g., CH1, Fig. 5) are defined on the second insulating layer, the source electrode and the drain electrode are arranged on the second insulating layer (e.g. , Fig, 5), and the source electrode and the drain electrode are respectively connected with the active layer through the first contact hole and the second contact hole (e.g., Fig, 5); and wherein the first insulating layer is arranged on a same layer as the second insulating layer (e.g., Fig, 5).
Regarding claim 17, Sakurai teaches the display panel according to claim 15, wherein the active layer and the first electrode plate are made of a same material and are located in a same layer (e.g., Fig. 5).
Response to Arguments
Applicant's arguments filed on April 10, 2026 have been fully considered but are moot in view of the new ground(s) of rejection.
Allowable Subject Matter
Claims 3, 6, 9 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if amended to overcome the claim objection above.
Claims 13, 16, 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if amended to overcome the claim objection above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
If applicant should desire to file an amendment, entry of a proposed amendment after final rejection cannot be made as a matter of right unless it merely cancels claims or complies with a formal requirement made earlier. Amendments touching the merits of the application which otherwise might not be proper may be admitted upon a showing a good and sufficient reasons why they are necessary and why they were not presented earlier.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bo Bin Jang whose telephone number is (571) 270-0271. The examiner can normally be reached on M-F from 9:00 AM to 6:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BO B JANG/Primary Examiner, Art Unit 2818 April 21, 2026
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