DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application CN 202211659304.X filed in China National Intellectual Property Administration (CNIPA) on December 22, 2022 and receipt of a certified copy thereof.
Claim Objections
Claims 1, 8, 11 and 18 are objected to because of the following informalities:
In claim 1, line 10, “in the first grooves” should read --in the plurality of first grooves--.
In claim 8, line 1, “the thin-film transistor” should read --the thin-film transistor area--.
In claim 8, line 5, “in the second grooves” should read --in the plurality of second grooves--.
In claim 11, line 11, “in the first grooves” should read --in the plurality of first grooves--.
In claim 18, line 1, “the thin-film transistor” should read --the thin-film transistor area--.
In claim 18, line 5, “in the second grooves” should read --in the plurality of second grooves--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 9 recites the feature “the third electrode plate” in line 6. There is insufficient antecedent basis for the feature in the claim and intervening claim(s) and base claim.
Claim 19 recites the feature “the third electrode plate” in line 6. There is insufficient antecedent basis for the feature in the claim and intervening claim(s) and base claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4-6, 11, 12 and 14-16 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Jeong et al. US 2018/0102398 (an embodiment used in rejection).
Regarding claim 1, Jeong teaches an array substrate (e.g., Embodiment of Figs. 1 and 5-7; [49]-[58], [94]-[109]), comprising a thin-film transistor area (e.g., thin-film transistor area including T1, T2 and/or T6, Fig. 5, Fig. 7) and a capacitance area (e.g., capacitance area including Cst, Fig. 5, Fig. 6, Fig. 7) located around the thin-film transistor area, wherein the capacitance area comprises:
a substrate (e.g., SUB, Fig. 7);
a first insulating layer (e.g., IL2 in the capacitance area (discussed above), Fig. 7) arranged on the substrate, wherein a plurality of first grooves (e.g., GR3, Fig. 7) are defined on the first insulating layer; and
a first storage capacitor (e.g., capacitor including Cst2 and Cst3, Fig. 7), wherein the first storage capacitor comprises a first electrode plate (e.g., Cst2, Fig. 7) and a second electrode plate (e.g., Cst3, Fig. 7) arranged opposite and insulated from the first electrode plate, the first electrode plate is arranged on the substrate (e.g., Fig. 7), and the second electrode plate is located at a side of the first insulating layer away from the substrate and is partially filled in the first grooves (e.g., Fig. 7).
Regarding claim 2, Jeong teaches the array substrate according to claim 1, wherein the capacitance area further comprises a buffer layer (e.g., GI, Fig. 7), the buffer layer is arranged on the substrate (e.g., Fig. 7), and the first electrode plate (e.g., Cst2, Fig. 4) is located on a side of the buffer layer away from the substrate (e.g., Fig. 7).
Regarding claim 4, Jeong teaches the array substrate according to claim 1, wherein the capacitance area further comprises a buffer layer (e.g., PSV, Fig. 7), the buffer layer is arranged on the substrate (e.g., Fig. 7), and the first electrode plate (e.g., Cst2, Fig. 7) is located between the buffer layer and the substrate (e.g., Fig. 7).
Regarding claim 5, Jeong teaches the array substrate according to claim 1, wherein the thin-film transistor area comprises a thin-film transistor structure (e.g., T1, T2 and/or T6, Fig. 7, Fig. 5), and the thin-film transistor structure comprises an active layer (e.g., ACT, Fig. 7), a gate electrode (e.g., GE, Fig. 7), a source electrode (e.g., DL1a connected to SE region, Fig. 7), a drain electrode (e.g., BRP connected to DE region, Fig. 7), and a second insulating layer (e.g., IL2 in the thin-film transistor area (discussed above), Fig. 7); wherein a first contact hole (e.g., CH7b in which DL1a is disposed, Fig. 7, Fig. 6) and a second contact hole (e.g., CH9 in which BRP is disposed, Fig. 7, Fig. 6) are defined on the second insulating layer, the source electrode and the drain electrode are arranged on the second insulating layer (e.g., Fig. 7), and the source electrode and the drain electrode are respectively connected with the active layer through the first contact hole and the second contact hole (e.g., Fig. 7); and wherein the first insulating layer is arranged on a same layer as the second insulating layer (e.g., Fig. 7).
Regarding claim 6, Jeong teaches the array substrate according to claim 5, wherein the source electrode, the drain electrode, and the second electrode plate (e.g., Cst3, Fig. 7) are made of a same material and are located in a same layer (e.g., Fig, 7).
Regarding claim 11, Jeong teaches a display panel (e.g., [2]), wherein the display panel comprises an array substrate (e.g., Embodiment of Figs. 1 and 5-7; [49]-[58], [94]-[109]), comprising a thin-film transistor area (e.g., thin-film transistor area including T1, T2 and/or T6, Fig. 5, Fig. 7) and a capacitance area (e.g., capacitance area including Cst, Fig. 5, Fig. 6, Fig. 7) located around the thin-film transistor area, wherein the capacitance area comprises:
a substrate (e.g., SUB, Fig. 7);
a first insulating layer (e.g., IL2 in the capacitance area (discussed above), Fig. 7) arranged on the substrate, wherein a plurality of first grooves (e.g., GR3, Fig. 7) are defined on the first insulating layer; and
a first storage capacitor (e.g., capacitor including Cst2 and Cst3, Fig. 7), wherein the first storage capacitor comprises a first electrode plate (e.g., Cst2, Fig. 7) and a second electrode plate (e.g., Cst3, Fig. 7) arranged opposite and insulated from the first electrode plate, the first electrode plate is arranged on the substrate (e.g., Fig. 7), and the second electrode plate is located at a side of the first insulating layer away from the substrate and is partially filled in the first grooves (e.g., Fig. 7).
Regarding claim 12, Jeong teaches the display panel according to claim 11, wherein the capacitance area further comprises a buffer layer (e.g., GI, Fig. 7), the buffer layer is arranged on the substrate (e.g., Fig. 7), and the first electrode plate (e.g., Cst2, Fig. 4) is located on a side of the buffer layer away from the substrate (e.g., Fig. 7).
Regarding claim 14, Jeong teaches the display panel according to claim 11, wherein the capacitance area further comprises a buffer layer (e.g., PSV, Fig. 7), the buffer layer is arranged on the substrate (e.g., Fig. 7), and the first electrode plate (e.g., Cst2, Fig. 7) is located between the buffer layer and the substrate (e.g., Fig. 7).
Regarding claim 15, Jeong teaches the display panel according to claim 11, wherein the thin-film transistor area comprises a thin-film transistor structure (e.g., T1, T2 and/or T6, Fig. 7, Fig. 5), and the thin-film transistor structure comprises an active layer (e.g., ACT, Fig. 7), a gate electrode (e.g., GE, Fig. 7), a source electrode (e.g., DL1a connected to SE region, Fig. 7), a drain electrode (e.g., BRP connected to DE region, Fig. 7), and a second insulating layer (e.g., IL2 in the thin-film transistor area (discussed above), Fig. 7); wherein a first contact hole (e.g., CH7b in which DL1a is disposed, Fig. 7, Fig. 6) and a second contact hole (e.g., CH9 in which BRP is disposed, Fig. 7, Fig. 6) are defined on the second insulating layer, the source electrode and the drain electrode are arranged on the second insulating layer (e.g., Fig. 7), and the source electrode and the drain electrode are respectively connected with the active layer through the first contact hole and the second contact hole (e.g., Fig. 7); and wherein the first insulating layer is arranged on a same layer as the second insulating layer (e.g., Fig. 7).
Regarding claim 16, Jeong teaches the display panel according to claim 15, wherein the source electrode, the drain electrode, and the second electrode plate (e.g., Cst3, Fig. 7) are made of a same material and are located in a same layer (e.g., Fig, 7).
Claims 1-6, 10-16 and 20 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Jeong et al. US 2018/0102398 (another embodiment used in rejection).
Regarding claim 1, Jeong teaches a display panel (e.g., [2]), wherein the display panel comprises an array substrate (e.g., Embodiment of Figs. 1 and 8-9; [49]-[58], [110]-[111]; Figs. 1 and 5-7, [94]-[109]: The embodiment of Figs. 1 and 8-9 includes a modified example of the capacitance area shown in the embodiment of Figs. 1 and 5-7 in which the capacitor includes three electrode plates Cst1, Cst2 and Cst3, Thus, the capacitance area of Figs. 8-9 in association with the thin-film transistor area of Figs. 5-7 is used in rejection.), comprising a thin-film transistor area (e.g., thin-film transistor area including T1, T2 and/or T6, Fig. 5, Fig. 7) and a capacitance area (e.g., capacitance area including Cst, Fig. 9, Fig. 8) located around the thin-film transistor area, wherein the capacitance area comprises:
a substrate (e.g., SUB, Fig. 9);
a first insulating layer (e.g., IL2 in the capacitance area (discussed above), Fig. 9) arranged on the substrate, wherein a plurality of first grooves (e.g., GR3, Fig. 9) are defined on the first insulating layer; and
a first storage capacitor (e.g., capacitor including Cst2 and Cst3, Fig. 9), wherein the first storage capacitor comprises a first electrode plate (e.g., Cst2, Fig. 9) and a second electrode plate (e.g., Cst3, Fig. 9) arranged opposite and insulated from the first electrode plate, the first electrode plate is arranged on the substrate (e.g., Fig. 9), and the second electrode plate is located at a side of the first insulating layer away from the substrate and is partially filled in the first grooves (e.g., Fig. 9).
Regarding claim 2, Jeong teaches the array substrate according to claim 1, wherein the capacitance area further comprises a buffer layer (e.g., IL1, Fig. 9), the buffer layer is arranged on the substrate (e.g., Fig. 9), and the first electrode plate (e.g., Cst2, Fig. 9) is located on a side of the buffer layer away from the substrate (e.g., Fig. 9).
Regarding claim 3, Jeong teaches the array substrate according to claim 2, wherein the capacitance area further comprises a third electrode plate (e.g., Cst1, Fig. 9), the third electrode plate is located between the buffer layer and the substrate (e.g., Fig. 9), and the third electrode plate and the first electrode plate (e.g., Cst2, Fig. 9) are configured as a second storage capacitor (e.g., Fig. 9).
Regarding claim 4, Jeong teaches the array substrate according to claim 1, wherein the capacitance area further comprises a buffer layer (e.g., PSV, Fig. 9), the buffer layer is arranged on the substrate (e.g., Fig. 9), and the first electrode plate (e.g., Cst2, Fig. 9) is located between the buffer layer and the substrate (e.g., Fig. 9).
Regarding claim 5, Jeong teaches the array substrate according to claim 1, wherein the thin-film transistor area comprises a thin-film transistor structure (e.g., T1, T2 and/or T6, Fig. 7, Fig. 5), and the thin-film transistor structure comprises an active layer (e.g., ACT, Fig. 7), a gate electrode (e.g., GE, Fig. 7), a source electrode (e.g., DL1a connected to SE region, Fig. 7), a drain electrode (e.g., BRP connected to DE region, Fig. 7), and a second insulating layer (e.g., IL2 in the thin-film transistor area (discussed above), Fig. 7); wherein a first contact hole (e.g., CH7b in which DL1a is disposed, Fig. 7, Fig. 6) and a second contact hole (e.g., CH9 in which BRP is disposed, Fig. 7, Fig. 6) are defined on the second insulating layer, the source electrode and the drain electrode are arranged on the second insulating layer (e.g., Fig. 7), and the source electrode and the drain electrode are respectively connected with the active layer through the first contact hole and the second contact hole (e.g., Fig. 7); and wherein the first insulating layer is arranged on a same layer as the second insulating layer (e.g., Fig. 7).
Regarding claim 6, Jeong teaches the array substrate according to claim 5, wherein the source electrode, the drain electrode, and the second electrode plate (e.g., Cst3, Fig. 9, Fig. 7) are made of a same material and are located in a same layer (e.g., Fig, 9, Fig. 7).
Regarding claim 10, Jeong teaches the array substrate according to claim 3, wherein the thin-film transistor area comprises a light shielding layer (e.g., EL, Fig. 7), and the light shielding layer and the third electrode plate (e.g., Cst1, Fig. 9) are located in a same layer and are made of a same material (e.g., Fig. 9, Fig. 7).
Regarding claim 11, Jeong teaches a display panel (e.g., [2]), wherein the display panel comprises an array substrate (e.g., Embodiment of Figs. 1 and 8-9; [49]-[58], [110]-[111]; Figs. 1 and 5-7, [94]-[109]: The embodiment of Figs. 1 and 8-9 includes a modified example of the capacitance area shown in the embodiment of Figs. 1 and 5-7 in which the capacitor includes three electrode plates Cst1, Cst2 and Cst3, Thus, the capacitance area of Figs. 8-9 in association with the thin-film transistor area of Figs. 5-7 is used in rejection.), comprising a thin-film transistor area (e.g., thin-film transistor area including T1, T2 and/or T6, Fig. 5, Fig. 7) and a capacitance area (e.g., capacitance area including Cst, Fig. 9, Fig. 8) located around the thin-film transistor area, wherein the capacitance area comprises:
a substrate (e.g., SUB, Fig. 9);
a first insulating layer (e.g., IL2 in the capacitance area (discussed above), Fig. 9) arranged on the substrate, wherein a plurality of first grooves (e.g., GR3, Fig. 9) are defined on the first insulating layer; and
a first storage capacitor (e.g., capacitor including Cst2 and Cst3, Fig. 9), wherein the first storage capacitor comprises a first electrode plate (e.g., Cst2, Fig. 9) and a second electrode plate (e.g., Cst3, Fig. 9) arranged opposite and insulated from the first electrode plate, the first electrode plate is arranged on the substrate (e.g., Fig. 9), and the second electrode plate is located at a side of the first insulating layer away from the substrate and is partially filled in the first grooves (e.g., Fig. 9).
Regarding claim 12, Jeong teaches the display panel according to claim 11, wherein the capacitance area further comprises a buffer layer (e.g., IL1, Fig. 9), the buffer layer is arranged on the substrate (e.g., Fig. 9), and the first electrode plate (e.g., Cst2, Fig. 9) is located on a side of the buffer layer away from the substrate (e.g., Fig. 9).
Regarding claim 13, Jeong teaches the display panel according to claim 12, wherein the capacitance area further comprises a third electrode plate (e.g., Cst1, Fig. 9), the third electrode plate is located between the buffer layer and the substrate (e.g., Fig. 9), and the third electrode plate and the first electrode plate (e.g., Cst2, Fig. 9) are configured as a second storage capacitor (e.g., Fig. 9).
Regarding claim 14, Jeong teaches the display panel according to claim 11, wherein the capacitance area further comprises a buffer layer (e.g., PSV, Fig. 9), the buffer layer is arranged on the substrate (e.g., Fig. 9), and the first electrode plate (e.g., Cst2, Fig. 9) is located between the buffer layer and the substrate (e.g., Fig. 9).
Regarding claim 15, Jeong teaches the display panel according to claim 11, wherein the thin-film transistor area comprises a thin-film transistor structure (e.g., T1, T2 and/or T6, Fig. 7, Fig. 5), and the thin-film transistor structure comprises an active layer (e.g., ACT, Fig. 7), a gate electrode (e.g., GE, Fig. 7), a source electrode (e.g., DL1a connected to SE region, Fig. 7), a drain electrode (e.g., BRP connected to DE region, Fig. 7), and a second insulating layer (e.g., IL2 in the thin-film transistor area (discussed above), Fig. 7); wherein a first contact hole (e.g., CH7b in which DL1a is disposed, Fig. 7, Fig. 6) and a second contact hole (e.g., CH9 in which BRP is disposed, Fig. 7, Fig. 6) are defined on the second insulating layer, the source electrode and the drain electrode are arranged on the second insulating layer (e.g., Fig. 7), and the source electrode and the drain electrode are respectively connected with the active layer through the first contact hole and the second contact hole (e.g., Fig. 7); and wherein the first insulating layer is arranged on a same layer as the second insulating layer (e.g., Fig. 7).
Regarding claim 16, Jeong teaches the display panel according to claim 15, wherein the source electrode, the drain electrode, and the second electrode plate (e.g., Cst3, Fig. 9, Fig. 7) are made of a same material and are located in a same layer (e.g., Fig, 9, Fig. 7).
Regarding claim 20, Jeong teaches the display panel according to claim 13, wherein the thin-film transistor area comprises a light shielding layer (e.g., EL, Fig. 7), and the light shielding layer and the third electrode plate (e.g., Cst1, Fig. 9) are located in a same layer and are made of a same material (e.g., Fig. 9, Fig. 7).
Claims 1, 2, 4-6, 11, 12 and 14-16 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Peng TW 201327757 (the original document and a machine-generated English translation thereof are used in rejection).
Regarding claim 1, Peng teaches an array substrate (e.g., Fig. 2G, translation [22]-[32]) comprising a thin-film transistor area (e.g., thin-film transistor area including 240, Fig. 2G) and a capacitance area (e.g., capacitance area including C1, Fig. 2G) around the thin-film transistor area, wherein the capacitance area comprises:
a substrate (e.g., 210, Fig. 2G);
a first insulating layer (e.g., 230 in the capacitance area (discussed above), Fig. 2G) arranged on the substrate, wherein a plurality of first grooves (e.g., first grooves in which 244 is disposed, Fig. 2G) are defined on the first insulating layer; and
a first storage capacitor (e.g., capacitor including C1, Fig. 2G; translation [35]), wherein the first storage capacitor comprises a first electrode plate (e.g., 224, Fig. 2G) and a second electrode plate (e.g., 244, Fig. 2G) arranged opposite and insulated from the first electrode plate, the first electrode plate is arranged on the substrate (e.g., Fig. 2G), and the second electrode plate is located at a side of the first insulating layer away from the substrate and is partially filled in the first grooves (e.g., Fig. 2G).
Regarding claim 2, Peng teaches the array substrate according to claim 1, wherein the capacitance area further comprises a buffer layer (e.g., 212, Fig. 2G), the buffer layer is arranged on the substrate (e.g., Fig. 2G), and the first electrode plate (e.g., 224, Fig. 2G) is located on a side of the buffer layer away from the substrate (e.g., Fig. 2G).
Regarding claim 4, Peng teaches the array substrate according to claim 1, wherein the capacitance area further comprises a buffer layer (e.g., 250, Fig. 2G), the buffer layer is arranged on the substrate (e.g., Fig. 2G), and the first electrode plate (e.g., 224, Fig. 2G) is located between the buffer layer and the substrate (e.g., Fig. 2G).
Regarding claim 5, Peng teaches the array substrate according to claim 1, wherein the thin-film transistor area comprises a thin-film transistor structure (e.g., 240, Fig. 2G), and the thin-film transistor structure comprises an active layer (e.g., 216, Fig. 2G), a gate electrode (e.g., 222, Fig. 2G), a source electrode (e.g., 242b, Fig. 2G), a drain electrode (e.g., 242c, Fig. 2G), and a second insulating layer (e.g., 230 in the thin-film transistor area (discussed above), Fig. 2G); wherein a first contact hole (e.g., W1 in which 242b is disposed, Fig. 2G) and a second contact hole (e.g., W1 in which 242c is disposed, Fig. 2G) are defined on the second insulating layer, the source electrode and the drain electrode are arranged on the second insulating layer (e.g., Fig. 2G), and the source electrode and the drain electrode are respectively connected with the active layer through the first contact hole and the second contact hole (e.g., Fig. 2G); and wherein the first insulating layer is arranged on a same layer as the second insulating layer (e.g., Fig. 2G).
Regarding claim 6, Peng teaches the array substrate according to claim 5, wherein the source electrode, the drain electrode, and the second electrode plate (e.g., 244, Fig. 2G) are made of a same material and are located in a same layer (e.g., Fig. 2G).
Regarding claim 11, Peng teaches a display panel (e.g., translation [20]), wherein the display panel comprises an array substrate (e.g., Fig. 2G, translation [22]-[32]) comprising a thin-film transistor area (e.g., thin-film transistor area including 240, Fig. 2G) and a capacitance area (e.g., capacitance area including C1, Fig. 2G) around the thin-film transistor area, wherein the capacitance area comprises:
a substrate (e.g., 210, Fig. 2G);
a first insulating layer (e.g., 230 in the capacitance area (discussed above), Fig. 2G) arranged on the substrate, wherein a plurality of first grooves (e.g., first grooves in which 244 is disposed, Fig. 2G) are defined on the first insulating layer; and
a first storage capacitor (e.g., capacitor including C1, Fig. 2G; translation [35]), wherein the first storage capacitor comprises a first electrode plate (e.g., 224, Fig. 2G) and a second electrode plate (e.g., 244, Fig. 2G) arranged opposite and insulated from the first electrode plate, the first electrode plate is arranged on the substrate (e.g., Fig. 2G), and the second electrode plate is located at a side of the first insulating layer away from the substrate and is partially filled in the first grooves (e.g., Fig. 2G).
Regarding claim 12, Peng teaches the display panel according to claim 11, wherein the capacitance area further comprises a buffer layer (e.g., 212, Fig. 2G), the buffer layer is arranged on the substrate (e.g., Fig. 2G), and the first electrode plate (e.g., 224, Fig. 2G) is located on a side of the buffer layer away from the substrate (e.g., Fig. 2G).
Regarding claim 14, Peng teaches the display panel according to claim 11, wherein the capacitance area further comprises a buffer layer (e.g., 250, Fig. 2G), the buffer layer is arranged on the substrate (e.g., Fig. 2G), and the first electrode plate (e.g., 224, Fig. 2G) is located between the buffer layer and the substrate (e.g., Fig. 2G).
Regarding claim 15, Peng teaches the display panel according to claim 11, wherein the thin-film transistor area comprises a thin-film transistor structure (e.g., 240, Fig. 2G), and the thin-film transistor structure comprises an active layer (e.g., 216, Fig. 2G), a gate electrode (e.g., 222, Fig. 2G), a source electrode (e.g., 242b, Fig. 2G), a drain electrode (e.g., 242c, Fig. 2G), and a second insulating layer (e.g., 230 in the thin-film transistor area (discussed above), Fig. 2G); wherein a first contact hole (e.g., W1 in which 242b is disposed, Fig. 2G) and a second contact hole (e.g., W1 in which 242c is disposed, Fig. 2G) are defined on the second insulating layer, the source electrode and the drain electrode are arranged on the second insulating layer (e.g., Fig. 2G), and the source electrode and the drain electrode are respectively connected with the active layer through the first contact hole and the second contact hole (e.g., Fig. 2G); and wherein the first insulating layer is arranged on a same layer as the second insulating layer (e.g., Fig. 2G).
Regarding claim 16, Peng teaches the display panel according to claim 15, wherein the source electrode, the drain electrode, and the second electrode plate (e.g., 244, Fig. 2G) are made of a same material and are located in a same layer (e.g., Fig. 2G).
Claims 1, 2, 4, 5, 7, 11, 12, 14, 15 and 17 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Sakurai et al. US 2008/0067519.
Regarding claim 1, Sakurai teaches an array substrate (e.g., Fig. 5, [5]-[12]), comprising a thin-film transistor area (e.g., thin-film transistor area including the pixel TFT portion, Fig. 5) and a capacitance area (e.g., capacitance area including the capacitor portion, Fig. 5) located around the thin-film transistor area, wherein the capacitance area comprises:
a substrate (e.g., 10, Fig. 5);
a first insulating layer (e.g., 56C in the capacitance area (discussed above), Fig. 5) arranged on the substrate, wherein a plurality of first grooves (e.g., first grooves in which 58 is disposed, Fig. 5) are defined on the first insulating layer; and
a first storage capacitor (e.g., capacitor including 58 and 55 in the capacitance area (discussed above), Fig. 5), wherein the first storage capacitor comprises a first electrode plate (e.g., 55 in the capacitance area (discussed above), Fig. 5) and a second electrode plate (e.g., 58, Fig. 5) arranged opposite and insulated from the first electrode plate, the first electrode plate is arranged on the substrate (e.g., Fig. 5), and the second electrode plate is located at a side of the first insulating layer away from the substrate and is partially filled in the first grooves (e.g., Fig. 5).
Regarding claim 2, Sakurai teaches the array substrate according to claim 1, wherein the capacitance area further comprises a buffer layer (e.g., 53, Fig. 5), the buffer layer is arranged on the substrate (e.g., Fig. 5), and the first electrode plate (e.g., 55 in the capacitance area (discussed above), Fig. 5) is located on a side of the buffer layer away from the substrate (e.g., Fig. 5).
Regarding claim 4, Sakurai teaches the array substrate according to claim 1, wherein the capacitance area further comprises a buffer layer (e.g., 19, Fig. 5), the buffer layer is arranged on the substrate (e.g., Fig. 5), and the first electrode plate (e.g., 55 in the capacitance area (discussed above), Fig. 5) is located between the buffer layer and the substrate (e.g., Fig. 5).
Regarding claim 5, Sakurai teaches the array substrate according to claim 1, wherein the thin-film transistor area comprises a thin-film transistor structure (e.g., pixel TFT, Fig. 5), and the thin-film transistor structure comprises an active layer (e.g., 55 in the thin-film transistor area (discussed above)), a gate electrode (e.g., 57, Fig. 5), a source electrode (e.g., 20S, Fig. 5), a drain electrode (e.g., 20D, Fig. 5), and a second insulating layer (e.g., 56 in the thin-film transistor area (discussed above), Fig. 5); wherein a first contact hole (e.g., CH2, Fig, 5) and a second contact hole (e.g., CH1, Fig. 5) are defined on the second insulating layer, the source electrode and the drain electrode are arranged on the second insulating layer (e.g. , Fig, 5), and the source electrode and the drain electrode are respectively connected with the active layer through the first contact hole and the second contact hole (e.g., Fig, 5); and wherein the first insulating layer is arranged on a same layer as the second insulating layer (e.g., Fig, 5).
Regarding claim 7, Sakurai teaches the array substrate according to claim 5, wherein the active layer and the first electrode plate are made of a same material and are located in a same layer (e.g., Fig. 5).
Regarding claim 11, Sakurai teaches a display panel (e.g., [2]), wherein the display panel comprises an array substrate (e.g., Fig. 5, [5]-[12]), comprising a thin-film transistor area (e.g., thin-film transistor area including the pixel TFT portion, Fig. 5) and a capacitance area (e.g., capacitance area including the capacitor portion, Fig. 5) located around the thin-film transistor area, wherein the capacitance area comprises:
a substrate (e.g., 10, Fig. 5);
a first insulating layer (e.g., 56C in the capacitance area (discussed above), Fig. 5) arranged on the substrate, wherein a plurality of first grooves (e.g., first grooves in which 58 is disposed, Fig. 5) are defined on the first insulating layer; and
a first storage capacitor (e.g., capacitor including 55 and 58 in the capacitance area (discussed above), Fig. 5), wherein the first storage capacitor comprises a first electrode plate (e.g., 55 in the capacitance area (discussed above), Fig. 5) and a second electrode plate (e.g., 58, Fig. 5) arranged opposite and insulated from the first electrode plate, the first electrode plate is arranged on the substrate (e.g., Fig. 5), and the second electrode plate is located at a side of the first insulating layer away from the substrate and is partially filled in the first grooves (e.g., Fig. 5).
Regarding claim 12, Sakurai teaches the display panel according to claim 11, wherein the capacitance area further comprises a buffer layer (e.g., 53, Fig. 5), the buffer layer is arranged on the substrate (e.g., Fig. 5), and the first electrode plate (e.g., 55 in the capacitance area (discussed above), Fig. 5) is located on a side of the buffer layer away from the substrate (e.g., Fig. 5).
Regarding claim 14, Sakurai teaches the display panel according to claim 11, wherein the capacitance area further comprises a buffer layer (e.g., 19, Fig. 5), the buffer layer is arranged on the substrate (e.g., Fig. 5), and the first electrode plate (e.g., 55 in the capacitance area (discussed above), Fig. 5) is located between the buffer layer and the substrate (e.g., Fig. 5).
Regarding claim 15, Sakurai teaches the display panel according to claim 11, wherein the thin-film transistor area comprises a thin-film transistor structure (e.g., pixel TFT, Fig. 5), and the thin-film transistor structure comprises an active layer (e.g., 55 in the thin-film transistor area (discussed above)), a gate electrode (e.g., 57, Fig. 5), a source electrode (e.g., 20S, Fig. 5), a drain electrode (e.g., 20D, Fig. 5), and a second insulating layer (e.g., 56 in the thin-film transistor area (discussed above), Fig. 5); wherein a first contact hole (e.g., CH2, Fig, 5) and a second contact hole (e.g., CH1, Fig. 5) are defined on the second insulating layer, the source electrode and the drain electrode are arranged on the second insulating layer (e.g. , Fig, 5), and the source electrode and the drain electrode are respectively connected with the active layer through the first contact hole and the second contact hole (e.g., Fig, 5); and wherein the first insulating layer is arranged on a same layer as the second insulating layer (e.g., Fig, 5).
Regarding claim 17, Sakurai teaches the display panel according to claim 15, wherein the active layer and the first electrode plate are made of a same material and are located in a same layer (e.g., Fig. 5).
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if amended to overcome the claim objection above.
Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if amended to overcome the claim objection above.
Conclusion
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/BO B JANG/Primary Examiner, Art Unit 2818 November 21, 2025