Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claims are rejected under 35 U.S.C. 103 as being unpatentable over Subbareddy et al (US 2014/0189302, herein Subbareddy) in view of Prabhakar et al (US 2020/0404888, herein Prabhakar).
Regarding claim 1, Subbareddy teaches an apparatus comprising:
a first plurality of physical processor cores of a first type to implement a plurality of logical processor cores of the first type ([0002], [0020-0022], multiple big cores to implement multiple logical cores, [0025], distinction between big and small logical cores);
a second plurality of physical processor cores of a second type, wherein each core of the second type is to implement a plurality of logical processor cores of the second type ([0002], [0020-0022], multiple small cores to implement logical cores, [0025], distinction between big and small logical cores); and
circuitry to: determine if a set of threads is to use more than a threshold number ([0032], current total number of available logical cores, determined dynamically) of logical processor cores and less than or equal to a total number of the first plurality of physical processor cores of the first type and the second plurality of physical processor cores of the second type ([0025], determine what subset of logical cores may be used to execute an application, [0032-0033], core selection circuitry, selecting a number of logical cores to execute threads up to a total available amount), and
disable a second logical core of a physical processor core of the second type ([0024], [0027], deactivating cores that are not executing threads), and not disable a first logical core of the physical processor core of the second type, in response to a determination that the set of threads is to use more than the threshold number of logical processor cores and less than or equal to the total number of the first plurality of physical processor cores of the first type and the second plurality of physical processor cores of the second type ([0025], [0032-0033], changing numbers and types of cores executing threads according to execution needs, including disabling one or more cores of only a specific type).
Subbareddy fails to teach wherein the threads are of a foreground application.
Prabhakar teaches an apparatus comprising a plurality of processor cores wherein circuitry is to determine if a set of threads of a foreground application is to use a number of the plurality of processor cores ([0023], system comprising multiple processor cores of different types, [0002], foreground and background processing, [0080], [0090], [0092], dynamically modifying number of cores available to execute programs, [0095], [0100], applications executing as threads).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Subbareddy and Prabhakar to utilize the logical core management method of Subbareddy for handling explicit foreground and background type applications, as taught by Prabhakar. While Subbareddy does not explicitly disclose that the multithreaded execution environment may handle applications which are split between a foreground and background processing environment, both Subbareddy and Prabhakar disclose methods for managing processor core allocation in multithreaded execution environments where the processor cores are split into different types. As Subbareddy does disclose the threads being executed potentially being split between multiple different applications (Subbareddy [0032]), the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 2, the combination of Subbareddy and Prabhakar teaches the apparatus of claim 1, wherein the circuitry is further to determine if a set of threads of a background application (Prabhakar [0002], background applications) also to execute on the first plurality of physical processor cores of the first type or the second plurality of physical processor cores of the second type is to contend for any logical core that is to execute the set of threads of the foreground application when the second logical core is disabled, wherein the circuitry is to not disable the second logical core in response to a determination that the set of threads of the background application that is to execute on the first plurality of physical processor cores of the first type or the second plurality of physical processor cores of the second type is to contend for any logical core that is to execute the set of threads of the foreground application when the second logical core is disabled (Subbareddy [0032-0033], thread selection circuitry to handle when active threads are from the same or different applications, dynamically assign threads according to current execution environment including which cores are currently active, [0027-0028], activate or deactivate cores as needed to handle processing).
Regarding claim 3, the combination of Subbareddy and Prabhakar teaches the apparatus of claim 1, wherein each core of the first type is to implement a single logical processor core of the first type (Subbareddy [0022], small cores implement only one logical core).
Regarding claim 4, the combination of Subbareddy and Prabhakar teaches the apparatus of claim 1, wherein the circuitry is to, in response to the determination that the set of threads of the foreground application (Prabhakar [0002], foreground applications) is to use more than the threshold number of logical processor cores and less than or equal to the total number of the first plurality of physical processor cores of the first type and the second plurality of physical processor cores of the second type: disable each second logical core of each physical processor core of the second type that is to execute a thread of the set of threads of the foreground application; not disable each first logical core of each physical processor core of the second type that is to execute a thread of the set of threads of the foreground application; and not disable each second logical core of each physical processor core of the second type that is not to execute a thread of the set of threads of the foreground application (Subbareddy [0025-0028], [0032-0033], dynamically assign threads to appropriate execution environment including activating & deactivating cores necessary for active threads; limit of total cores available; applications may execute on multiple types of cores or all on one type according to execution environment demands).
Regarding claim 5, the combination of Subbareddy and Prabhakar teaches the apparatus of claim 1, wherein the circuitry is to, in response to the determination that the set of threads of the foreground application is to use more than the threshold number of logical processor cores and less than or equal to the total number of the first plurality of physical processor cores of the first type and the second plurality of physical processor cores of the second type, disable each second logical core of each physical processor core of the second type (Subbareddy [0030], activate only small cores to execute program, [0027], deactivate cores that are not selected to run programs).
Regarding claim 6, the combination of Subbareddy and Prabhakar teaches the apparatus of claim 1, wherein the threshold number of logical processor cores is a single logical processor core ([0022], small core implements one logical core, [0032], current number of available logical cores depends on runtime constraints and execution environment).
Regarding claim 7, the combination of Subbareddy and Prabhakar teaches the apparatus of claim 1, further comprising a thread runtime telemetry circuit to generate an energy efficiency capability value or a performance capability value for each logical processor core of the apparatus, wherein the circuitry is to disable the second logical core of the physical processor core of the second type, and not disable the first logical core of the physical processor core of the second type, by lowering the energy efficiency capability value or the performance capability value of the second logical core (Subbareddy [0002-0003], dynamic allocation to increase energy efficiency, [0030-0031], tracking performance via performance counters per-core, [0033], performance counters and power budget used to dynamically allocate and select active cores & Prabhakar [0050], energy performance preference control).
Regarding claim 8, the combination of Subbareddy and Prabhakar teaches the apparatus of claim 1, wherein the circuitry is to disable the second logical core of the physical processor core of the second type, and not disable the first logical core of the physical processor core of the second type, by causing modification of a control value, of an operating system, that sets a maximum percentage of logical processors that are to be in an un-parked state ([0022], cores visible to operating system, [0025-0027], dynamically determining core availability by core selection module, [0032], modifying total number of available cores according to execution environment and processing constraints & Prabhakar [0040-0041], applications designated as using higher or lower percentage of available CPU processing power).
Claims 9-16 refer to a method embodiment of the apparatus embodiment of claims 1-8. Therefore, the above rejections for claims 1-8 are applicable to claims 9-16, respectively.
Claims 17-24 refer to a medium embodiment of the apparatus embodiment of claims 1-8. Therefore, the above rejections for claims 1-8 are applicable to claims 17-24, respectively.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Desikachari (US 2022/0027199) discloses a processor for managing a number of threads assigned to a background process.
Adsure (US 2021/0325956) discloses a processor that maps cores to multiple types of logical processors).
Chanterac (US 10,817,307) discloses a processor for mapping foreground and background processes to multiple threads to be scheduled for execution.
Kim (US 2020/0301745) discloses a processor for changing a threshold value for a processing amount according to whether an application is in the foreground or background.
Reid (US 2019/0163902) discloses a processor that distinguishes application execution contexts by logical core number.
Dumitrescu (US 2018/0107766) discloses a processor that maps logical cores to physical cores according to application demands.
Kannan (US 2016/0170470) discloses a processor that schedules threads according to core type and a threshold value.
Shows (US 2015/0007187) discloses a processor that schedules threads according to an available number of logical processors.
Lyashevsky (US 2013/03228891) discloses a processor for scheduling threads to different core types accounting for a threshold number of processing requests.
Murakami (US 2013/0103956) discloses a processor for increasing a number of operating cores for a foreground application.
Herdrich (US 2010/0250998) discloses a processor for implementing logical processors to execute foreground and background applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 8:30-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183