DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 6, 8-17 and 20 have been considered but are moot on grounds of new rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6, 8-17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (Yu) (US 2021/0366854 A1) in view of Hsu (US 2022/0045025 A1 now US 11,798,909 B2) in view of Rubin et al. (Rubin) (US 2021/0134724 A1).
In regards to claim 6, Yu (Figs. 9-20 and associated text and items) discloses a chip packaging structure (Figs. 17-20, items 110, 112, 124, 138), comprising: an encapsulated grain (item 66), comprising a plurality first hybrid bonding structure (items 39 plus 40); a plurality of third hybrid bonding structures (items 60 or 54 plus 60) arranged inside the encapsulated grain (item 66), and at least one chip (item 68 on the left or right); and a packaging substrate (items 106, 114, 128, 140), comprising a front side and a back side opposite to each other; a plurality of second hybrid bonding structures (top surfaces of items 106, 114, 128, 140) are formed on the front side of the packaging substrate (items 106, 114, 128, 140) and a plurality of connection pins (solder balls/bumps shown but not labeled in Figs. 17-20) is formed on the back side of the packing substrate (items 106, 114, 128, 140); the plurality of second hybrid bonding structure (top surfaces of items 106, 114, 128, 140) are electrically connected to the connection pins (solder balls/bumps shown but not labeled in Figs. 17-20) through a plurality of metal post (redistribution lines and via/posts shown but not labeled, item 130) penetrating the packaging substrate (items 106, 114, 128, 140); wherein each of the plurality of first hybrid bonding structures (items 39 plus 40) of the encapsulated grain (item 66) is bonded to a respective one of the plurality of second hybrid bonding structures (top surfaces of items 106, 114, 128, 140 or item 49) of the packaging substrate (items 106, 114, 128, 140) by medium-to-medium and metal-to-metal aligned bonding (paragraph 46), such that the encapsulated grain (item 66) is bonded to the packaging substrate (items 106, 114, 128, 140); the plurality of third hybrid bonding structures (items 60 or 54 plus 60) are bonded to the at least one chip (item 68 on the left or right).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine features of the various embodiments of Yu for the purpose of an electrical connection and design choice.
Yu does not specifically disclose a pitch an any adjacent two of the plurality of first hybrid bonding structures (items 39 plus 40) is than a pitch of any adjacent two of the plurality of third hybrid structures (items 60 or 54 plus 60).
Hsu (Fig. 2A and associated text) discloses a pitch of any adjacent two of the plurality of the first hybrid structures (items 34) is greater than a pitch of any adjacent two of the plurality of third hybrid structures (items 31).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Hsu or the purpose of an electrical connection and design choice.
Yu as modified by Hsu does not specifically disclose a package substrate, being a ceramic substrate.
Rubin (Figs. 1-5 and associated text) discloses a package substrate (item 110), being a ceramic substrate (paragraph 38).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Rubin for the purpose of having a package substrate that is suitable for the given application (paragraph 38), since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
In regards to claim 8, Yu (Figs. 9-20 and associated text and items) discloses wherein each of the plurality of connection pins (solder balls/bumps shown but not labeled in Figs. 17-20) comprises a metal bump and/or a metal solder ball (solder balls/bumps shown but not labeled in Figs. 17-20).
In regards to claim 9, Yu (Figs. 9-20 and associated text and items) discloses wherein the encapsulated grain (item 66) further comprises a wafer (item 20); the at least one chip (items 68 and/or 84) is bonded to the wafer (item 20), and a side of the wafer (item 20) away from the at least one chip (items 68 and/or 84) is formed with the plurality of first hybrid bonding structures (items 39 plus 40); the third hybrid bonding structures (items 60 or 54 plus 60) is formed on a side of the wafer (item 20) bonded to the at least one chip (items 68 and/or 84).
In regards to claim 10, Yu (Figs. 9-20 and associated text and items) discloses wherein for each of the at least one chip (items 68 and/or 84), to two of the plurality of first hybrid bonding structures (items 39 plus 40) and two of the plurality of third hybrid bonding structure (items 49) comprises two third hybrid bonding structures (items 49, 54 plus 60 or 70 plus 72), and an orthographic projection of each of the two first hybrid bonding structures (items 39 plus 40) and the two third hybrid bonding structures (items 49, 54 plus 60 or 70 plus 72) on the packaging substrate (items 106, 114, 128, 140) is within an orthographic projection of the chip on the packaging substrate (items 106, 114, 128, 140).
In regards to claim 11, Yu (Figs. 9-20 and associated text and items) discloses wherein the wafer (item 20) comprises a first semiconductor substrate (item 26), and a first dielectric layer (items 44, 46 or 44 plus 46) a second dielectric layer (items 34, 36, 39 or 36 plus 39) laminated on opposite sides of the first semiconductor substrate (item 26); a side surface of the second dielectric layer (items 34, 36, 39 or 36 plus 39) away from the first semiconductor substrate (item 26) is taken as a pin surface (where items 42 can be placed).
In regards to claim 12, Yu (Figs. 9-20 and associated text and items) discloses wherein at least one electronic device (item 28, paragraphs 14, 17) and at least one connecting metal column (item 30) are formed in the first semiconductor substrate (item 36), and each of the at least one connecting metal column (item 30) extends to a side surface of the first semiconductor substrate (item 26) away from the first dielectric layer (items 44, 46 or 44 plus 46); the first hybrid bonding structure (item 39 plus 40) is formed in the second dielectric layer items 34, 36, 39 or 36 plus 39), electrically connected to the connecting metal column (item 30), and exposed from the pin surface (where items 42 can be placed).
In regards to claim 13, Yu (Figs. 9-20 and associated text and items) discloses wherein at least one first interconnection structure (items 50, 60 or 50 plus 60) is formed in the first dielectric layer (items 44, 46, 54, 44 plus 46 or 44 plus 46 plus 54), and each first interconnection structure (items 50, 60 or 50 plus 60) is electrically connected to each connecting metal column (item 30) in one-to-one correspondence; the third hybrid bonding structure (items 70 plus 72) comprises at least one third hybrid bonding structure (items 70 plus 72), and each of the at least one third hybrid bonding structure (items 70 plus 72) is formed on a side surface of the first dielectric layer (items 44, 46, 54, 44 plus 46 or 44 plus 46 plus 54) away from the first semiconductor substrate (item 26) and is electrically connected to each first interconnection structure (items 50, 60 or 50 plus 60) in one-to-one correspondence.
In regards to claim 14, Yu (Figs. 9-20 and associated text and items) discloses wherein each chip (item 68) comprises a second semiconductor substrate (item 76) and a third dielectric layer (items 70, 74 or 70 plus 74); at least one electronic device (paragraph 33) is formed in the second semiconductor substrate (item 76), the third dielectric layer (items 70, 74 or 70 plus 74) is laminated on the second semiconductor substrate (item 76) and is attached to the first dielectric layer (items 44, 46, 54, 44 plus 46 or 44 plus 46 plus 54), and the third dielectric layer (items 70, 74 or 70 plus 74) is formed with a second interconnection structure (item 74) and a plurality of fourth hybrid bonding structures (item 70 plus 72) electrically connected to the second interconnection structure (item 74); the plurality of fourth hybrid bonding structures is formed on a side surface of the third dielectric layer (items 70, 74 or 70 plus 74) away from the second semiconductor substrate (item 76); the plurality of fourth hybrid bonding structures (item 70 plus 72) are bonded to the plurality of third hybrid bonding structures (item 49 or 54 plus 60) for aligning and bonding the first dielectric layer (items 44, 46, 54, 44 plus 46 or 44 plus 46 plus 54) with the third dielectric layer (items 70, 74 or 70 plus 74), and aligning and bonding the third hybrid bonding structure (item 49 or 54 plus 60) with the plurality of fourth hybrid bonding structure (item 70 plus 72), to enable the chip to be bonded to the wafer (item 20).
In regards to claim 15, Yu (Figs. 9-20 and associated text and items) discloses wherein the encapsulated grain (item 66) further comprises an encapsulated layer (item 80), covering the at least one chip (item 68) and a gap (shown but not labeled) between adjacent two of the at least one chip (item 68).
In regards to claim 16, Yu (Figs. 9-20 and associated text and items) discloses wherein the packaging substrate (items 106, 114, 128, 140) further comprises a third substrate and a fourth dielectric layer (items 106, 114, 128, 140) that are laminated; the third substrate (items 106, 114, 128, 140) comprises a first side and a second side opposite to each other; the second hybrid bonding structure (top surface/layer of items 106, 114, 128, 140) is disposed on the first side of the third substrate (items 106, 114, 128, 140), the connection pin (balls/bumps shown but not labeled) is formed on the second side of the third substrate (items 106, 114, 128, 140), and the metal post (item 130) runs through the first side and second side of the third substrate (items 106, 114, 128, 140).
In regards to claim 17, Yu (Figs. 9-20 and associated text and items) discloses wherein the fourth dielectric layer is laminated to the first side of the third substrate (items 106, 114, 128, 140) and a side of the fourth dielectric layer away from the third substrate is taken as a substrate surface; the first hybrid bonding structure (items 39 plus 40) is arranged in the fourth dielectric layer, and the plurality of first hybrid bonding structure (item 39 plus 40) is connected to the plurality of second hybrid bonding structure (top surface/layer of items 106, 114, 128, 140) and exposed from the substrate surface of the fourth dielectric layer.
In regards to claim 20, Yu (Figs. 9-20 and associated text and items) discloses a printed circuit board (items 134 or 142, paragraph 47); wherein the connecting pin (balls/bumps shown but not labeled) of the package substrate (items 106, 114, 128, 140) is bonded to a metal bump and/or a metal solder ball (balls/bumps shown but not labeled) of the printed circuit board (items 134 or 142).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 January 21, 2026