Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/10/2025 has been entered.
Claim Rejections – 35 U.S.C. 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 36 recites “the first dielectric layer primarily including silicon nitride” and “the first dielectric layer primarily including silicon oxynitride”. Claim 36 depends from Claim 35, wherein the first dielectric layer primarily including silicon nitride; the second dielectric layer primarily including silicon oxynitride. For purpose of examination, the Examiner interprets the limitation as the first dielectric layer primarily including silicon nitride; the second dielectric layer primarily including silicon oxynitride.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6, 9, 10, 21, 23, 25, 27 and 29 rejected under 35 U.S.C. 103 as being unpatentable over Massolini (U.S. Patent Pub. No. 2017/0178787) of record, in view of Bonifield (U.S. Patent Pub. No. 2019/0206981), in view of Matsushita (JP 2019087428) of record, in view of Smith (U.S. Patent No. 6,255,233) of record.
Regarding Claim 1
FIG. 8 of Massolini discloses a microelectronic device, comprising: a substrate (810); a lower isolation element (822) above the substrate, the lower isolation element being electrically conductive; a lower field reduction layer (830-842) over the lower isolation element: an isolation dielectric layer stack (850) over the lower field reduction layer; and an upper isolation element (852) over the isolation dielectric layer stack, the upper isolation element being electrically conductive and magnetically coupled to the lower isolation element, wherein: the lower field reduction layer includes a first dielectric layer (830) adjacent to the lower isolation element and physically contacts a top surface of the lower isolation element that faces the upper isolation element; the lower field reduction layer includes a second dielectric layer (840) disposed over the top surface of the lower isolation element between the first dielectric layer and the isolation dielectric layer stack; and physically contacts the first dielectric layer.
Massolini is silent with respect to “the first dielectric layer has a first dielectric constant greater than a dielectric constant of the isolation dielectric layer stack adjacent to the lower field reduction layer, the first dielectric layer includes primarily silicon nitride” and “the second dielectric layer has a second dielectric constant greater than the dielectric constant of the isolation dielectric layer stack adjacent to the lower field reduction layer and less than the first dielectric constant, the second dielectric layer includes primarily silicon oxynitride”.
FIG. 1 of Bonifield discloses a similar microelectronic device, wherein the lower field reduction layer includes a first dielectric layer (silicon nitride 124) adjacent to the lower isolation element (130); the first dielectric layer has a first dielectric constant (7-9) greater than a dielectric constant of the isolation dielectric layer stack adjacent to the lower field reduction layer, the first dielectric layer includes primarily silicon nitride [0020] and physically contacts a top surface of the lower isolation element (130) that faces the upper isolation element; the lower field reduction layer includes a second dielectric layer (126) disposed over the top surface of the lower isolation element; the lower field reduction layer includes a second dielectric layer (silicon oxynitride) between the first dielectric layer and the isolation dielectric layer stack; and the second dielectric layer has a second dielectric constant (4-7) greater than the dielectric constant (3.9) of the isolation dielectric layer stack (silicon dioxide) adjacent to the lower field reduction layer and less than the first dielectric constant, the second dielectric layer includes primarily silicon oxynitride and physically contacts the first dielectric layer. One of ordinary skill in the art would use the order as claimed because Massolini discloses the field reduction layer blocks electric field but allows magnetic coupling between the primary and secondary sides of the transformer [0045]; and Matsushita discloses by providing the insulating spacer with the gradient of the dielectric constant, the maximum electric field value on the surface of the insulating spacer is suppressed, and the insulating performance of the insulating spacer is enhanced. In addition, Smith discloses a gradual change in composition of nitrogen and oxygen within the film, in particular, forming the film stack of silicon nitride, silicon oxynitride and silicon oxide in sequence would improve interfacial properties.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Massolini, as taught by Bonifield, Matsushita and Smith. The ordinary artisan would have been motivated to modify Massolini in the above manner for purpose of enhancing the insulating performance (text of Matsushita) and relieving electric stress against external electric field (JP H06251651 provides documentary evidence).
Regarding Claim 2
FIG. 1 of Smith discloses the isolation dielectric layer stack adjacent to the lower isolation element includes primarily silicon dioxide (30, dielectric constant 3.9).
Regarding Claim 3
FIG. 2 of Smith discloses the silicon oxynitride has a ratio of oxygen to nitrogen of 0.5 to 2.0. The limitation “the silicon nitride has a refractive index of 2.00 to 2.20” is related to material property, and is a function of the wavelength. When the silicon oxynitride is closer to silicon nitride, the refractive index is closer to 2.0-2.3. Where the claimed and prior art products are identi-cal or substantially identical in structure or composi-tion, or are produced by identical or substantially identical processes, a prima facie case of either antici-pation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). MPEP2112.01
Regarding Claim 4
The limitation “the silicon nitride has a refractive index of 2.03 to 2.07; and has an effective band gap energy of 4.5 electron-volts (eV) to 5.3 eV” is related to material property. Where the claimed and prior art products are identi-cal or substantially identical in structure or composi-tion, or are produced by identical or substantially identical processes, a prima facie case of either antici-pation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). MPEP2112.01
Regarding Claim 5
FIG. 8 of Massolini discloses the lower isolation element is a lower winding of an isolation transformer.
Regarding Claim 6
The limitation “the silicon nitride has a refractive index of 2.15 to 2.20; and has an effective band gap energy of 3.0 eV to 3.7 eV” is related to material property. Where the claimed and prior art products are identi-cal or substantially identical in structure or composi-tion, or are produced by identical or substantially identical processes, a prima facie case of either antici-pation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). MPEP2112.01
Regarding Claim 9
One of ordinary skill in the art would recognize that modifying Massolini such that a thickness of the second dielectric layer over a corner of the lower isolation element is thinner than the thickness of the second dielectric layer over a middle of the lower isolation element would reduce parasitic capacitance between the primary coil and the secondary coil, while minimize the interference to the magnetic field (minimize the interference to the electric field lines within the coil).
Regarding Claim 10
Smith discloses the first dielectric layer (silicon nitride) has an effective band gap energy (4.55 eV – 5.3 eV) less than an effective band gap energy (4.5 eV – 8 eV) of the second dielectric layer (silicon oxynitride); and the effective band gap energy of the second dielectric layer is less than an effective band gap energy (8.9 eV – 9.4 eV) of the isolation dielectric layer (silicon oxide) stack adjacent to the lower field reduction layer.
Regarding Claim 21
One of ordinary skill in the art would recognize that modifying Massolini to include an upper field reduction layer over the isolation dielectric layer stack between the upper isolation element and the isolation dielectric layer stack, wherein the upper field reduction layer including a third dielectric layer and a fourth dielectric layer; and the third dielectric layer has a third dielectric constant greater than the dielectric constant of the isolation dielectric layer stack; and the fourth dielectric layer has a fourth dielectric constant greater than the dielectric constant of the isolation dielectric layer stack and less than the third dielectric constant would further enhance the insulating performance.
Regarding Claim 23
Modified Massolini discloses the third dielectric layer primarily includes silicon nitride and physically contacts the upper isolation element, the fourth dielectric layer primarily includes silicon oxynitride and physically contacts the isolation dielectric layer stack; and the third dielectric layer physically contacts the fourth dielectric layer, because mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See MPEP 2144.04.
Regarding Claim 25
FIG. 8 of Massolini discloses a microelectronic device, comprising: a lower isolation element (822) disposed over a substrate (810), the lower isolation element being electrically conductive and having opposing sidewall surfaces and a top surface extending between the opposing sidewall surfaces; a lower field reduction layer (830-842) disposed over the lower isolation element: an isolation dielectric layer stack (850) disposed over the lower field reduction layer; and an upper isolation element (852) disposed over the isolation dielectric layer stack, the upper isolation element being electrically conductive and magnetically coupled to the lower isolation element, wherein the lower field reduction layer includes a first dielectric layer physically contacting the opposing sidewall surfaces and the top surface of the lower isolation element.
Massolini is silent with respect to “the first dielectric layer includes primarily silicon nitride and physically contacts the opposing sidewall surfaces and the top surface of the lower isolation element; the first dielectric layer has a first dielectric constant greater than a dielectric constant of the isolation dielectric layer stack; the lower field reduction layer includes a second dielectric layer disposed over the lower isolation element between the first dielectric layer and the isolation dielectric layer stack, the second dielectric layer extending along the opposing sidewall surfaces and the top surface of the lower isolation element; and the second dielectric layer has a second dielectric constant greater than the dielectric constant of the isolation dielectric layer stack and less than the first dielectric constant, the second dielectric layer includes primarily silicon oxynitride and physically contacts the first dielectric layer”.
FIG. 1 of Bonifield discloses a similar microelectronic device, wherein the first dielectric layer (124) includes primarily silicon nitride [0020] and physically contacts the opposing sidewall surfaces and the top surface of the lower isolation element (130); the first dielectric layer has a first dielectric constant (7-9) greater than a dielectric constant (3.9) of the isolation dielectric layer stack (silicon dioxide 128); the lower field reduction layer includes a second dielectric layer (silicon oxynitride 126) disposed over the lower isolation element between the first dielectric layer and the isolation dielectric layer stack, the second dielectric layer extending along the opposing sidewall surfaces and the top surface of the lower isolation element; and the second dielectric layer has a second dielectric constant (4-7) greater than the dielectric constant of the isolation dielectric layer stack and less than the first dielectric constant, the second dielectric layer includes primarily silicon oxynitride and physically contacts the first dielectric layer. One of ordinary skill in the art would use the specific order because Massolini discloses the field reduction layer blocks electric field but allows magnetic coupling between the primary and secondary sides of the transformer [0045]; and Matsushita discloses by providing the insulating spacer with the gradient of the dielectric constant, the maximum electric field value on the surface of the insulating spacer is suppressed, and the insulating performance of the insulating spacer is enhanced. In addition, Smith discloses a gradual change in composition of nitrogen and oxygen within the film, in particular, forming the film stack of silicon nitride, silicon oxynitride and silicon oxide in sequence would improve interfacial properties.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Massolini, as taught by Bonifield, Matsushita and Smith. The ordinary artisan would have been motivated to modify Massolini in the above manner for purpose of enhancing the insulating performance (text of Matsushita) and relieving electric stress against external electric field (JP H06251651 provides documentary evidence).
Regarding Claim 27
Modified Massolini discloses the second dielectric layer is prevented from physically contacting the lower isolation element by the first dielectric layer.
Regarding Claim 29
FIG. 8 of Massolini discloses the upper isolation element has a top surface, a bottom surface, and opposing sidewall surfaces extending from the top surface to the bottom surface of the upper isolation element. One of ordinary skill in the art would recognize that modifying Massolini to include an upper field reduction layer over the isolation dielectric layer stack between the upper isolation element and the isolation dielectric layer stack, wherein the upper field reduction layer including a third dielectric layer and a fourth dielectric layer; and the third dielectric layer has a third dielectric constant greater than the dielectric constant of the isolation dielectric layer stack; and the fourth dielectric layer has a fourth dielectric constant greater than the dielectric constant of the isolation dielectric layer stack and less than the third dielectric constant would further enhance the insulating performance.
Claims 1, 35 and 36 rejected under 35 U.S.C. 103 as being unpatentable over Lowther (U.S. Patent Pub. No. 2003/0127686), in view of Stewart (U.S. Patent Pub. No. 2020/0035617), in view of Smith (U.S. Patent No. 6,255,233) of record.
Regarding Claim 1
FIG. 2D of Lowther discloses a microelectronic device, comprising: a substrate (119); a lower isolation element (lower 102) above the substrate, the lower isolation element being electrically conductive [0050]; a lower field reduction layer (123 below the top of 124) over the lower isolation element; an isolation dielectric layer stack (123 above the top of 124) over the lower field reduction layer; and an upper isolation element (upper 102) over the isolation dielectric layer stack, the upper isolation element being electrically conductive and magnetically coupled to the lower isolation element.
Lowther is silent with respect to “the lower field reduction layer includes a first dielectric layer adjacent to the lower isolation element; the first dielectric layer has a first dielectric constant greater than a dielectric constant of the isolation dielectric layer stack adjacent to the lower field reduction layer, the first dielectric layer includes primarily silicon nitride and physically contacts a top surface of the lower isolation element that faces the upper isolation element; the lower field reduction layer includes a second dielectric layer disposed over the top surface of the lower isolation element; the lower field reduction layer includes a second dielectric layer between the first dielectric layer and the isolation dielectric layer stack; and the second dielectric layer has a second dielectric constant greater than the dielectric constant of the isolation dielectric layer stack adjacent to the lower field reduction layer and less than the first dielectric constant, the second dielectric layer includes primarily silicon oxynitride and physically contacts the first dielectric layer”.
FIG. 2G of Stewart discloses a similar microelectronic device, wherein the lower field reduction layer includes a first dielectric layer (155b) adjacent to the lower isolation element (133); the first dielectric layer has a first dielectric constant (7-9), the first dielectric layer includes primarily silicon nitride [0027] and physically contacts a top surface of the lower isolation element that faces the upper isolation element; the lower field reduction layer includes a second dielectric layer (160) disposed over the top surface of the lower isolation element; the lower field reduction layer includes a second dielectric layer; and the second dielectric layer has a second dielectric constant (4-7) less than the first dielectric constant, the second dielectric layer includes primarily silicon oxynitride [0022] and physically contacts the first dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lowther, as taught by Stewart. The ordinary artisan would have been motivated to modify Lowther in the above manner for purpose of suppressing dielectric crack ([0017] of Stewart).
Lowther as modified by Stewart is silent with respect to “the first dielectric layer has a first dielectric constant greater than a dielectric constant of the isolation dielectric layer stack adjacent to the lower field reduction layer” and “the second dielectric layer has a second dielectric constant greater than the dielectric constant of the isolation dielectric layer stack adjacent to the lower field reduction layer”
FIG. 1 of Smith discloses a similar microelectronic device, comprising an isolation dielectric layer stack (30) over the lower field reduction layer, wherein the first dielectric layer (20) has a first dielectric constant greater than a dielectric constant of the isolation dielectric layer stack adjacent to the lower field reduction layer; and the second dielectric layer (40) has a second dielectric constant greater than the dielectric constant of the isolation dielectric layer stack adjacent to the lower field reduction layer and less than the first dielectric constant.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lowther, as taught by Smith. The ordinary artisan would have been motivated to modify Lowther in the above manner, because a gradual change in composition of nitrogen and oxygen within the film, in particular, forming the film stack of silicon nitride, silicon oxynitride and silicon oxide in sequence would improve interfacial properties (Abstract of Smith).
Regarding Claim 35
FIG. 2G of Stewart discloses the lower isolation element (133) includes a first conductive portion and a second conductive portion, the first and second conductive portions defining the top surface of the lower isolation element; the first dielectric layer (155b) primarily including silicon nitride extending between the first conductive portion and the second conductive portion to a first depth within the microelectronic device, the first depth within the microelectronic device is below the top surface of the lower isolation element such that a bottom surface of the first dielectric layer is positioned closer to the substrate than the top surface of the lower isolation element; the second dielectric layer (160) primarily including silicon oxynitride extending between the first conductive portion and the second conductive portion to a second depth within the microelectronic device, the second depth within the microelectronic device is below the top surface of the lower isolation element such that a bottom surface of the second dielectric layer is positioned closer to the substrate than the top surface of the lower isolation element; and the isolation dielectric layer stack adjacent to the lower isolation element primarily includes silicon dioxide extending between the first conductive portion and the second conductive portion to a third depth within the microelectronic device, the third depth within the microelectronic device is below the top surface of the lower isolation element such that a bottom surface of the isolation dielectric layer stack is positioned closer to the substrate than the top surface of the lower isolation element.
Regarding Claim 36
FIG. 2G of Stewart discloses the first dielectric layer (155b) primarily including silicon nitride has a first thickness extending between the first conductive portion and the second conductive portion; the second dielectric layer (160) primarily including silicon oxynitride has a second thickness extending between the first conductive portion and the second conductive portion, the second thickness being greater than the first thickness. FIG. 1 of Smith discloses the isolation dielectric layer stack (30) adjacent to the lower isolation element primarily including silicon dioxide has a third thickness. Modified Lowther discloses a third thickness extending between the first conductive portion and the second conductive portion, the third thickness being greater than the first thickness.
Claim 24 rejected under 35 U.S.C. 103 as being unpatentable over Massolini, in view of Poddar (U.S. Patent Pub. No. 2013/0043970) of record.
Regarding Claim 24
Modified Massolini discloses Claim 1, wherein the lower isolation element has opposing sidewall surfaces and the first dielectric layer physically contacts the opposing sidewall surfaces of the lower isolation element; and the upper isolation element has opposing sidewall surfaces and a bottom surface facing the substrate.
Modified Massolini is silent with respect to “the third dielectric layer physically contacts the bottom surface without physically contacting the opposing sidewall surfaces of the upper isolation element”.
FIG. 2 of Poddar discloses a similar microelectronic device, wherein the lower isolation element (34) has opposing sidewall surfaces and the first dielectric layer (35) physically contacts the opposing sidewall surfaces of the lower isolation element; and the upper isolation element (32) has opposing sidewall surfaces and a bottom surface facing the substrate, the third dielectric layer (33) physically contacts the bottom surface without physically contacting the opposing sidewall surfaces of the upper isolation element.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Massolini, as taught by Poddar. The ordinary artisan would have been motivated to modify Massolini in the above manner, because the claimed configuration was a matter of choice (as evidenced by various embodiments of Poddar). In re Dailey 149 USPQ 47, 50 (CCPA 1966). See also Glue Co. v. Upton 97 US 3,24 (USSC 1878). MPEP 2144.04.
Claim 28 rejected under 35 U.S.C. 103 as being unpatentable over Massolini, in view of O’Sullivan (U.S. Patent Pub. No. 2014/0252533) of record.
Regarding Claim 28
Modified Massolini discloses Claim 25.
Modified Massolini is silent with respect to “the first dielectric layer has a first thickness over the top surface of the lower isolation element and the second dielectric layer has a second thickness over the top surface of the lower isolation element, the second thickness being greater than the first thickness”.
FIG. 2 of O’Sullivan discloses a similar microelectronic device, wherein the first dielectric layer (82) has a first thickness over the top surface of the lower isolation element (52) and the second dielectric layer (90) has a second thickness over the top surface of the lower isolation element, the second thickness being greater than the first thickness.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Massolini, as taught by O’Sullivan. The ordinary artisan would have been motivated to modify Massolini in the above manner for purpose of improving the breakdown voltage of an insulating structure ([0045] of O’Sullivan).
Claim 32 rejected under 35 U.S.C. 103 as being unpatentable over Massolini, in view of Chen (U.S. Patent Pub. No. 2020/0343037) of record.
Regarding Claim 32
Modified Massolini discloses Claim 25.
Modified Massolini is silent with respect to “an interconnect structure disposed under the lower isolation element, the interconnect structure including a via physically contacting a bottom surface of the lower isolation element, the bottom surface of the lower isolation element facing the substrate”.
FIG. 1 of Chen discloses a similar microelectronic device, comprising an interconnect structure (140) disposed under the lower isolation element (160), the interconnect structure including a via (170) physically contacting a bottom surface of the lower isolation element, the bottom surface of the lower isolation element facing the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Massolini, as taught by Chen. The ordinary artisan would have been motivated to modify Massolini in the above manner for purpose of forming micro-scale planar-coil transformers including one or more shields ([0003] of Chen).
Claims 33 and 34 rejected under 35 U.S.C. 103 as being unpatentable over Massolini, in view of Iwaya (U.S. Patent Pub. No. 2009/0280646) of record.
Regarding Claim 33
Modified Massolini discloses Claim 25, wherein the first dielectric layer including primarily silicon nitride.
Modified Massolini is silent with respect to a bond pad disposed over the substrate, the first dielectric layer extending continuously from the lower isolation element to the bond pad.
FIG. 1 of Iwaya discloses a similar microelectronic device, comprising a bond pad (9) disposed over the substrate (1), the first dielectric layer (10) extending continuously from the lower isolation element to the bond pad.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Massolini, as taught by Iwaya. The ordinary artisan would have been motivated to modify Massolini in the above manner for purpose of preventing the insulating film between the coils from being cracked ([0010] of Iwaya).
Regarding Claim 34
Modified Massolini discloses the bond pad has a top surface facing away from the substrate; the first dielectric layer including primarily silicon nitride covers a portion of the top surface of the bond pad; and the second dielectric layer including primarily silicon oxynitride extending continuously from over the lower isolation element to over the portion of the top surface of the bond pad such that the second dielectric layer covers the portion of the top surface of the bond pad
Claim 35 rejected under 35 U.S.C. 103 as being unpatentable over Massolini and Matsushita, in view of Stewart (U.S. Patent Pub. No. 2020/0035617).
Regarding Claim 35
Massolini as modified by Matsushita discloses Claim 1.
Massolini as modified by Matsushita is silent with respect to “the lower isolation element includes a first conductive portion and a second conductive portion, the first and second conductive portions defining the top surface of the lower isolation element; the first dielectric layer primarily including silicon nitride extending between the first conductive portion and the second conductive portion to a first depth within the microelectronic device, the first depth within the microelectronic device is below the top surface of the lower isolation element such that a bottom surface of the first dielectric layer is positioned closer to the substrate than the top surface of the lower isolation element; the second dielectric layer primarily including silicon oxynitride extending between the first conductive portion and the second conductive portion to a second depth within the microelectronic device, the second depth within the microelectronic device is below the top surface of the lower isolation element such that a bottom surface of the second dielectric layer is positioned closer to the substrate than the top surface of the lower isolation element; and the isolation dielectric layer stack adjacent to the lower isolation element primarily includes silicon dioxide extending between the first conductive portion and the second conductive portion to a third depth within the microelectronic device, the third depth within the microelectronic device is below the top surface of the lower isolation element such that a bottom surface of the isolation dielectric layer stack is positioned closer to the substrate than the top surface of the lower isolation element”.
FIG. 2G of Stewart discloses a similar microelectronic device, wherein the lower isolation element (133) includes a first conductive portion and a second conductive portion, the first and second conductive portions defining the top surface of the lower isolation element; the first dielectric layer (155b) primarily including silicon nitride extending between the first conductive portion and the second conductive portion to a first depth within the microelectronic device, the first depth within the microelectronic device is below the top surface of the lower isolation element such that a bottom surface of the first dielectric layer is positioned closer to the substrate than the top surface of the lower isolation element; the second dielectric layer (160) primarily including silicon oxynitride extending between the first conductive portion and the second conductive portion to a second depth within the microelectronic device, the second depth within the microelectronic device is below the top surface of the lower isolation element such that a bottom surface of the second dielectric layer is positioned closer to the substrate than the top surface of the lower isolation element; and the isolation dielectric layer stack adjacent to the lower isolation element primarily includes silicon dioxide extending between the first conductive portion and the second conductive portion to a third depth within the microelectronic device, the third depth within the microelectronic device is below the top surface of the lower isolation element such that a bottom surface of the isolation dielectric layer stack is positioned closer to the substrate than the top surface of the lower isolation element.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Massolini, as taught by Stewart and Matsuzaki. The ordinary artisan would have been motivated to modify Massolini in the above manner for purpose of suppressing dielectric crack ([0017] of Stewart).
Pertinent Art
Pertinent art includes Seong (U.S. Patent Pub. No. 2022/0052300), Yamada (U.S. Patent Pub. No. 2020/0294786), 20060263727, 20180337084, Onuma (JP 2009021568), JP 2013182091 and JP 2006313941.
Response to Arguments
Applicant’s arguments with respect to Claim 1 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897