DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Claim Rejections - 35 USC § 103 3
A. Claims 1, 5-8, 10, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0303289 (“Lee”) in view of US 2017/0336347 (“Ram”). 3
B. Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Ram, as applied to claim 1 above, and further in view of US 2019/0187092 (“Cheng”). 10
C. Claims 9 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Ram, as applied to claim 8 above, and further in view of US 2020/0182826 (“Liu”). 11
D. Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Ram and Liu, as applied to claim 15 above, and further in view of Cheng. 14
III. Response to Arguments 16
Conclusion 16
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1, 5-8, 10, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0303289 (“Lee”) in view of US 2017/0336347 (“Ram”).
Claims 1 and 8 read,
1. (Currently Amended) A device for analyte sensing, the device comprising:
[1] a first semiconductor layer including a source region, a drain region and a stack of semiconductor nanosheets extending between the source region and the drain region;
[2] a first dielectric layer including a dielectric material on the first semiconductor layer; and
[3] a cavity extending through an opening of the first dielectric layer and the first semiconductor layer,
[4a] wherein the semiconductor nanosheets are disposed within the cavity
[4b] such that a region above the semiconductor nanosheets is open and free of the dielectric material, and
[4c] a portion of the cavity resides in between the semiconductor nanosheets, and
[5] wherein the cavity includes a front gate terminal disposed therein above the semiconductor nanosheets and within the opening of the first dielectric layer.
8. (Original) The device of claim 1, further comprising
[1] a second dielectric layer beneath the first semiconductor layer and
[2] a second semiconductor layer beneath the second dielectric layer,
[3] the second dielectric layer and the second semiconductor layer defining a back gate structure.
With regard to claims 1 and 8, Lee discloses, generally in Figs. 2 and 11,
1. (Currently Amended) A device 200 [¶ 31; Fig. 2] for analyte sensing, the device 200 comprising:
[1] a first semiconductor layer 13(21)/12(20) including a source region [i.e. region below source electrode S, 30], a drain region [i.e. region below drain electrode D, 30] and a stack of semiconductor nanosheets [i.e. nanowires 20] extending between the source region and the drain region [¶¶ 8, 32-33, 41, 45, 52];
[2] a first dielectric layer 16 [¶ 54] including a dielectric material on the first semiconductor layer 13(21)/12(20); and
[3] a cavity [not given a reference character] extending through an opening of the first dielectric layer 16 and the first semiconductor layer 13(21)/12(20) [see explanation below],
[4a] wherein the semiconductor nanosheets 20 are disposed within the cavity
[4b] such that a region above the semiconductor nanosheets 20 is open and free of the dielectric material 16 [as shown in each of Figs. 2 and 11], and
[4c] a portion of the cavity resides [again, see explanation below] in between the semiconductor nanosheets 20 [as shown in each of Figs. 2 and 11], and
[5] wherein the cavity includes a front gate terminal 31 disposed therein [¶ 52] front gate terminal disposed therein … within the opening of the first dielectric layer 16.
8. (Original) The device of claim 1, further comprising
[1] a second dielectric layer 11 [¶ 39] beneath the first semiconductor layer 13(21)/12(20) and
[2] a second … layer 10 [i.e. “substrate 10” beneath the second dielectric layer 11],
[3] … [not taught] …
With regard to feature [1] of claim 1, each nanowire 20 within a given semiconductor sheet 12 may be taken as a claimed “nanosheet”, or the collection of nanowires within a single semiconductor layer 12 may be taken as a claimed “nanosheet”.
With regard to features [3] and [4c] of claim 1, the cavity is not given a reference character but is shown in each of Figs. 2 and 11 of Lee as the opening in the insulating layer 16 exposing the nanowires 20 (¶¶ 53, 54). The portion of the claimed “cavity” that is “through … the first semiconductor layer” (feature [3]) and “between the semiconductor nanosheets”, shown in each of Figs. 2 and 11, is the portion generated by removing the supporting the “support layer 21” portion of sacrificial SiGe nanosheet 13, as shown in Figs. 5-6 of Lee (¶¶ 42-43).
With regard to feature [5] of claim 1, Lee states that the purpose of the “submerged gate electrode 31” is to “fix a potential of a solution” (Lee: ¶ 8) or “to apply potential directly to the solution” (Lee: ¶ 52). Therefore, all that is required is that the electrode be in the analyte solution.
While Lee shows that the front gate terminal 31 is within the opening in the first dielectric 16, Lee does not show that the front gate terminal 31 is positioned above the nanosheets, as required by feature [5].
With regard to feature [2] of claim 8, Lee does not indicate what the material of the substrate 10 is.
With regard to feature [3] of claim 8,
[3] the second dielectric layer and the second semiconductor layer defining a back gate structure.
Lee does not disclose a back gate and does not therefore teach the limitations of feature [3].
Ram, like Lee, teaches a silicon nanostructure-channel FET used as a chemical sensor formed from a substrate including an active Si nanowire channel 101 supported on a buried oxide 111, in turn, on a bulk substrate 112 (Ram: ¶ 71; Figs. 1-2). Ram further teaches that the bulk substrate 112 is silicon (id.).
Also like Lee, Ram teaches a gate dielectric 113 formed on the Si nanowire channel (Ram: ¶ 72). Still further like Lee’s front gate electrode 31, Ram teaches a front gate electrode or “reference electrode 104” to which a “front gate voltage (VGS)” is applied (Ram: ¶¶ 81-82). Ram further shows that the “reference electrode 104” is positioned above the silicon nanowire, as required by feature [5] of claim 1.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to position the front gate electrode 31 of Lee above the nanosheet stack, as taught by Ram because it is merely a change in position.
Moreover, this amounts to mere rearrangement of parts, which has been found to be unpatentable when the operation of the device is not modified. See In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice).
Further with regard to features [2] and [3] of claim 8, Ram further teaches that the chemFET includes a back gate formed by the buried oxide 111 and bulk silicon substrate 112 (Ram: ¶¶ 73, 82) to which a back gate contact 108 is made, the back gate used to tune the threshold voltage of the transistor (Ram: ¶ 71). Ram teaches that the combination of the front gate 104 and back gate 111/112 are used to improve the sensitivity of the sensor (Ram: ¶¶ 80-82), the front gate used to “to keep the electrochemical potential drop over the electrode-electrolyte interface stable (as a result, to keep the electrochemical potential of the solution stable) and the readout signal reliable” (Ram: ¶ 81).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the substrate 10 of Lee from bulk silicon because Lee merely fails to indicate any specific material such that one having ordinary skill in the art would use materials known to be suitable for the same purpose of forming a nanosheet chemFET, such as the bulk silicon substrate material taught in Ram.
In addition, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the insulating layer 11 of Lee and the bulk silicon substrate 10 of Lee/Ram a back-gate electrode, in order to tune the threshold voltage, in order to keep the electrochemical potential of the analyte solution stable, thereby jointly improving the sensitivity of the FET sensor, as taught in Ram. As such, RAM may be seen as an improvement to Lee in this aspect. (See MPEP 2143.)
This is all of the limitations of claims 1 and 8.
With regard to claims 5-7 and 10, Lee further discloses,
5. (Original) The device of claim 1, wherein the cavity is configured to hold an analyte [e.g. target material 41 (¶ 37)].
6. (Original) The device of claim 5, wherein the device 200 comprises and ion sensitive field effect transistor (ISFET) [because the target material has a “charge (¶ 58) and is therefore, by definition, an ion].
7. (Original) The device of claim 1, wherein the source region S, 30 and drain region D, 30 each include a metallic contact [S and D in Fig. 2 and 30 in Fig. 11 (¶¶ 53-54)].
10. (Original) The device of claim 1, further comprising a plurality of separated semiconductor nanosheet stacks within the cavity and extending between the source region and the drain region.
With regard to claim 10, with each nanowire as a claimed “nanosheet”, each column of nanowires 20 shown in Fig. 2 may be taken as a single stack; therefore, Fig. 2 of Lee shows four adjacent stacks of nanosheets.
Claim 21 reads,
21. (Currently Amended) A device for analyte sensing, the device comprising:
[1] a first semiconductor layer including a source region, a drain region and a stack of semiconductor nanosheets extending between and contacting the source region and the drain region;
[2] a first dielectric layer including a dielectric material on the first semiconductor layer; and
[3] a cavity extending through the first dielectric layer and the first semiconductor layer,
[4a] wherein the semiconductor nanosheets are disposed within the cavity
[4b] such that a region above the semiconductor nanosheets is free of the dielectric material, and
[4c] a portion of the cavity resides in between the semiconductor nanosheets;
[5] a back gate located adjacent to the stack of nanosheets; and
[6] a front gate located above the stack of nanosheets.
With regard to claim 21, Lee discloses, generally in Figs. 2 and 11,
21. (Currently Amended) A device 200 for analyte sensing, the device comprising:
[1] a first semiconductor layer 13(21)/12(20) including a source region [i.e. region below source electrode S, 30], a drain region [i.e. region below drain electrode D, 30] and a stack of semiconductor nanosheets [i.e. nanowires 20] extending between and contacting the source region and the drain region [¶¶ 8, 32-33, 41, 45, 52];
[2] a first dielectric layer 16 [¶ 54] including a dielectric material on the first semiconductor layer 13(21)/12(20); and
[3] a cavity [not given a reference character] extending through the first dielectric layer 16 and the first semiconductor layer 13(21)/12(20) [see explanation under features [3] and [4c] of claim 1, above],
[4a] wherein the semiconductor nanosheets 20 are disposed within the cavity
[4b] such that a region above the semiconductor nanosheets 20 is free of the dielectric material 16 [as shown in each of Figs. 2 and 11], and
[4c] a portion of the cavity resides in between the semiconductor nanosheets 20 [see explanation under features [3] and [4c] of claim 1, above].
[5] … [not taught] …
[6] a front gate 31 located …[adjacent to]… the stack of nanosheets 20.
With regard to features [5] and [6] of claim 21, as explained above, Lee does not disclose the backage of feature [5] or the positioning of the front gate 31 above the nanosheet stack 20. However, these limitations are obvious for the same reasons as explained under claims 1 and 8, above, which are incorporated here.
This is all of the limitations of claim 21.
B. Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Ram, as applied to claim 1 above, and further in view of US 2019/0187092 (“Cheng”).
Claims 2-4 read,
2. (Original) The device of claim 1, wherein the semiconductor nanosheets includes a high dielectric constant (high-k) material.
3. (Original) The device of claim 2, wherein the high-k material is applied to a plurality of surfaces of the semiconductor nanosheets.
4. (Original) The device of claim 2, wherein the high-k material includes one of hafnium dioxide (HfO2), aluminum oxide (Al2O3), or hafnium aluminum oxide (HfAlO).
The prior art of Lee, as explained above, discloses each of the features of claim 1.
While Lee discloses a gate insulating layer 15 formed on the nanowires (Lee: ¶ 47; Fig. 8), Lee does not indicate what the gate insulating material and does not therefore teach a high-k material as required by claims 2-4.
Cheng, like Lee, teaches a stacked nanosheet chemFET 10 having a gate insulating layer one the exposed surfaces of the nanosheets within the cavity (Cheng: Figs. 14-16; abstract; ¶¶ 1, 4-6, 29, 30, 77-82; “A stacked nanofluidics sensor is formed in the second region 30” [¶ 78]). Cheng further teaches that the gate insulating material 116 is a high-k dielectric including the materials recited in claim 4 (Cheng: ¶ 65).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the gate insulating layer 15 of Lee from the high-k materials in Cheng because Lee merely fails to indicate any specific dielectric such that one having ordinary skill in the art would use materials known to be suitable for the same purpose of forming a nanosheet chemFET, such as the materials recited in Cheng. As such using a high-k material, and any of the specific high-k materials, amounts to obvious material choice. (See MPEP 2144.07.)
This is all of the limitations of claims 2-4.
C. Claims 9 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Ram, as applied to claim 8 above, and further in view of US 2020/0182826 (“Liu”).
Claim 9 reads,
9. The device of claim 8, wherein the back gate structure includes a metallic contact.
The prior art of Lee in view of Ram, as explained above, teaches each of the features of claim 8.
While Ram shows the back gate contact 108, Ram does not teach that the material of the contact is metal, as required by claim 9.
Liu, like each of Lee and Ram, teaches a FET used as a chemical sensor including a back side oxide 232 (BOX) on a supporting bulk silicon substrate 228 (Liu: title, abstract ¶ 54; Fig. 3). Like Ram, Liu teaches a back gate 234/242 formed using the back side BOX(232)/bulk Si substrate(228) to apply a back side gate potential Vg3 (Liu: Fig. 3; ¶ 58). Liu further teaches that the contact 260 to the back side gate is made from metal, i.e. “gate terminals 258, 260, 262 may be in the form of metal contacts” (Liu: ¶ 58; emphasis added).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the contact to the back gate of Lee/Ram from metal because Liu teaches that metal is suitable for forming a contact to a back side gate electrode used as a sensing FET. As such, the selection of metal for the back gate contact amount to obvious material choice. (See MPEP 2144.07.)
This is all of the features of claim 9.
Claim 15 reads,
15. (Currently Amended) An analyte sensor device, comprising:
[1] a first semiconductor layer including a source region, a drain region and a stack of semiconductor nanosheets extending between the source region and the drain region;
[2] a first dielectric layer including a dielectric material on the first semiconductor layer;
[3] a cavity extending through the first dielectric layer and the first semiconductor layer,
[4a] wherein the semiconductor nanosheets are disposed within the cavity
[4b] such that a region above the semiconductor nanosheets is open and free of the dielectric material, and
[4c] a portion of the cavity resides in between the semiconductor nanosheets, and
[5] wherein the cavity includes a front gate terminal above the semiconductor nanosheets; and
[6] a back gate structure defined by a second dielectric layer and a second semiconductor layer disposed beneath the first semiconductor layer,
[7] wherein the back gate structure, the source region and the drain region each include a metallic contact.
With regard to claim 15, Lee discloses, generally in Figs. 2 and 11,
15. (Currently Amended) An analyte sensor device 200 [¶ 31; Fig. 2] comprising:
[1] a first semiconductor layer 13(21)/12(20) including a source region [i.e. region below source electrode S, 30], a drain region [i.e. region below drain electrode D, 30] and a stack of semiconductor nanosheets [i.e. nanowires 20] extending between the source region and the drain region [¶¶ 8, 32-33, 41, 45, 52];
[2] a first dielectric layer 16 [¶ 54] including a dielectric material on the first semiconductor layer 13(21)/12(20); and
[3] a cavity [not given a reference character] extending through the first dielectric layer 16 and the first semiconductor layer 13(21)/12(20) [see explanation under claim 1, above],
[4a] wherein the semiconductor nanosheets 20 are disposed within the cavity
[4b] such that a region above the semiconductor nanosheets 20 is open and free of the dielectric material 16 [as shown in each of Figs. 2 and 11], and
[4c] a portion of the cavity resides [as explained under claim 1, above] in between the semiconductor nanosheets 20 [as shown in each of Figs. 2 and 11], and
[5] wherein the cavity includes a front gate terminal 31 disposed therein [¶ 52] …;
[6] … [not taught] …
[7] wherein … the source region S, 30 and drain region D, 30 each include a metallic contact [S and D in Fig. 2 and 30 in Fig. 11 (¶¶ 53-54)].
With regard to feature [5] of claim 15, as explained above under claim 1, while Lee shows that the front gate terminal 31 is within the opening in the first dielectric 16, Lee does not show that the front gate terminal 31 is positioned above the nanosheets. However, this is obvious in view of Ram for the reasons explained above under claim 1 (supra), which is applied here.
With regard to features [6] of claim 15, as explained above under claim 1, Lee does not disclose a back gate structure formed by the insulating layer 11 of Lee and the underlying bulk silicon substrate 10 of Lee/Ram. However, this is obvious in view of Ram for the reasons explained above under claim 1 (supra), which is applied here.
With regard to feature [7] of claim 15, Ram does not indicate that the contact to the back gate, used in Lee, is metal. However, this is obvious for the reasons explained under claim 9, above, which is applied here.
This is all of the limitations of claim 15.
D. Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Ram and Liu, as applied to claim 15 above, and further in view of Cheng.
Claims 16 and 17 read,
16. (Original) The device of claim 15, wherein the semiconductor nanosheets includes a high dielectric constant (high-k) material.
17. The device of claim 16, wherein the high-k material includes one of hafnium dioxide (HfO2), aluminum oxide (Al2O3), or hafnium aluminum oxide (HfAlO).
The prior art of Lee in view of Ram and Liu, as explained above, teaches each of the features of claim 15.
As explained above under the rejection of claims 2-4 over Lee in view of Cheng, while Lee discloses a gate insulating layer 15 formed on the nanowires (Lee: ¶ 47; Fig. 8), Lee does not indicate what the gate insulating material and does not therefore teach a high-k material as required by claims 2-4.
As explained above, Cheng, like Lee, teaches a stacked nanosheet chemFET having a gate insulating layer one the exposed surfaces of the nanosheets within the cavity. Cheng further teaches that the gate insulating material is a high-k dielectric including the materials recited in claim 17 (Cheng: ¶ 65).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the gate insulating layer 15 of Lee form the materials in Cheng because Lee merely fails to indicate any specific dielectric such that one having ordinary skill in the art would use materials known to be suitable for the same purpose of forming a nanosheet chemFET, such as the materials recited in Cheng. As such using a high-k material and any of the specific high-k materials amounts to obvious material choice. (See MPEP 2144.07.)
This is all of the limitations of claims 16-17.
With regard to claim 18, Lee further discloses,
18. (Original) The device of claim 17, wherein the cavity is configured to hold an analyte [i.e. “target material 41” as shown in Fig. 2 of Lee].
Claim 19 and 20 read,
19. (Original) The device of claim 18, wherein sensing a property of the analyte is implemented by:
[1] setting a source voltage Vs to ground;
[2] biasing a drain/source voltage VDS to approximately 0.1 V; and
[3] sweeping a back gate voltage VBG and recording a threshold voltage Vth at the back gate structure.
20. (Original) The device of claim 19, wherein the back gate voltage VBG is swept positively for an NFET and negatively for a PFET.
The limitations recited in claims 19 and 20 are statements of intended use and fail to have patentable weight for failing to require any additional structural element. It is well settled that (1) “apparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original) and (2) a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). (See MPEP 2114(II).)
III. Response to Arguments
Applicant’s arguments filed 05/27/2026 have been considered but they are not fully persuasive.
Applicant argues that the applied prior art of Lee does not teach the newly added feature requiring “a front gate terminal disposed therein above the semiconductor nanosheets and within the opening of the first dielectric layer” (Remarks filed 05/27/2026, p. 7). While this overcomes the rejection of claims 1 and 21 over Lee alone, Ram is applied for teaching the positioning of a front gate electrode above the stack of nanosheets. As such, Applicant’s arguments are not fully persuasive.
Conclusion
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
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