DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Continued Examination Under 37 CFR 1.114 3
III. Claim Rejections - 35 USC § 102 3
A. Claim 21 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2019/0187092 (“Cheng”). 4
B. Claims 1, 5-7, 10, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2015/0303289 (“Lee”). 5
IV. Claim Rejections - 35 USC § 103 7
A. Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Cheng. 7
B. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of US 2017/0336347 (“Ram”). 8
C. Claims 9 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Ram, as applied to claim 8 above, and further in view of US 2020/0182826 (“Liu”). 11
D. Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Ram and Liu, as applied to claim 14 above, and further in view of Cheng. 13
E. Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Lee. 15
F. Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Lee, Ram, and US 2012/0214172 (“Chen”). 16
G. Claims 9 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Ram and Chen, as applied to claim 8 above, and further in view of US 2020/0182826 (“Liu”). 21
H. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Lee, Ram, and Chen, as applied to claim 1 above, and further in view of CN 109427908 A (“Gao”). 25
V. Response to Arguments 26
Conclusion 27
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 02/10/2026 has been entered.
III. Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
A. Claim 21 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2019/0187092 (“Cheng”).
With regard to claims 21, Cheng discloses, generally in Figs. 14-16,
21. (Currently Amended) A device 10 for analyte sensing [abstract; ¶¶ 1, 4-6, 29, 30, 77-82; “A stacked nanofluidics sensor is formed in the second region 30” (¶ 78)], the device comprising:
[1] a first semiconductor layer 114, 314 including a source region 314, a drain region 314 and a stack of semiconductor nanosheets 114 extending between and contacting the source region 314 and the drain region 314 [¶¶ 51-54, ; Figs. 5, 14, 16];
[2] a first dielectric layer 110 including a dielectric material [¶¶ 55-56] on the [first] semiconductor layer 114, 314 [Figs. 6, 16]; and
[3] a cavity 318, 330 extending through the first dielectric layer 110 and the first semiconductor layer 114, 314 [¶ 79; Figs. 7, 14, 16],
[4a] wherein the semiconductor nanosheets 114 are disposed within the cavity 318, 330
[4b] such that a region above the semiconductor nanosheets 114 is open and free of the dielectric material 110 [as shown in Fig. 10; see explanation below], and
[4c] a portion 318 of the cavity 318, 330 resides in between the semiconductor nanosheets 114 [as shown in Figs. 7, 14, 16].
With regard to feature [4b] of claim 21, Fig. 10 of Cheng shows that the first dielectric layer 110 formed over the top surface of the nanosheets 114. A second dielectric layer that may be, but is not required to be, the same material as that used for the first dielectric layer 110 shown in Fig. 10 is subsequently deposited in Fig. 11:
[0071] Referring now to FIG. 11, a step including forming additional dielectric on the ILD 110 of the semiconductor device 10 is depicted according to an embodiment of the present invention.
(Cheng: ¶ 71; emphasis added)
Therefore the claimed “dielectric material” of the claimed “first dielectric layer” 110 of Cheng is not over the nanosheets 114, because the dielectric material is the “additional dielectric on the ILD 110” (id.) and therefore not the dielectric material of the first dielectric layer 110 shown in Fig. 10.
B. Claims 1, 5-7, 10, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2015/0303289 (“Lee”).
With regard to claim 1, Lee discloses, generally in Figs. 2 and 11,
1. (Currently Amended) A device 200 [¶ 31; Fig. 2] for analyte sensing, the device 200 comprising:
[1] a first semiconductor layer 13(21)/12(20) including a source region [i.e. region below source electrode S, 30], a drain region [i.e. region below drain electrode D, 30] and a stack of semiconductor nanosheets [i.e. nanowires 20] extending between the source region and the drain region [¶¶ 8, 32-33, 41, 45, 52];
[2] a first dielectric layer 16 [¶ 54] including a dielectric material on the first semiconductor layer 13(21)/12(20); and
[3] a cavity [not given a reference character] extending through the first dielectric layer 16 and the first semiconductor layer 13(21)/12(20) [see explanation below],
[4a] wherein the semiconductor nanosheets 20 are disposed within the cavity
[4b] such that a region above the semiconductor nanosheets 20 is open and free of the dielectric material 16 [as shown in each of Figs. 2 and 11], and
[4c] a portion of the cavity resides [again, see explanation below] in between the semiconductor nanosheets 20 [as shown in each of Figs. 2 and 11], and
[5] wherein the cavity includes a front gate terminal 31 disposed therein [¶ 52].
With regard to feature [1] of claim 1, each nanowire 20 within a given semiconductor sheet 12 may be taken as a claimed “nanosheet”, or the collection of nanowires within a single semiconductor layer 12 may be taken as a claimed “nanosheet”.
With regard to features [3] and [4c] of claim 1, the cavity is not given a reference character but is shown in each of Figs. 2 and 11 of Lee as the absence of the insulating layer 16 exposing the nanowires 20 (¶¶ 53, 54). The portion of the claimed “cavity” that is “through … the first semiconductor layer” (feature [3]) and “between the semiconductor nanosheets”, shown in each of Figs. 2 and 11, is the portion generated by removing the supporting the “support layer 21” portion of sacrificial SiGe nanosheet 13, as shown in Figs. 5-6 of Lee (¶¶ 42-43).
This is all of the limitations of claim 1.
With regard to claims 5-7 and 10, Lee further discloses,
5. (Original) The device of claim 1, wherein the cavity is configured to hold an analyte [e.g. target material 41 (¶ 37)].
6. (Original) The device of claim 5, wherein the device 200 comprises and ion sensitive field effect transistor (ISFET) [because the target material has a “charge (¶ 58) and is therefore, by definition, an ion].
7. (Original) The device of claim 1, wherein the source region S, 30 and drain region D, 30 each include a metallic contact [S and D in Fig. 2 and 30 in Fig. 11 (¶¶ 53-54)].
10. (Original) The device of claim 1, further comprising a plurality of separated semiconductor nanosheet stacks within the cavity and extending between the source region and the drain region.
With regard to claim 10, with each nanowire as a claimed “nanosheet”, each column of nanowires 20 shown in Fig. 2 may be taken as a single stack; therefore, Fig. 2 of Lee shows four adjacent stacks of nanosheets.
With regard to claim 21, Lee discloses, generally in Figs. 2 and 11,
21. (Currently Amended) A device 200 for analyte sensing, the device comprising:
[1] a first semiconductor layer 13(21)/12(20) including a source region [i.e. region below source electrode S, 30], a drain region [i.e. region below drain electrode D, 30] and a stack of semiconductor nanosheets [i.e. nanowires 20] extending between and contacting the source region and the drain region [¶¶ 8, 32-33, 41, 45, 52];
[2] a first dielectric layer 16 [¶ 54] including a dielectric material on the first semiconductor layer 13(21)/12(20); and
[3] a cavity [not given a reference character] extending through the first dielectric layer 16 and the first semiconductor layer 13(21)/12(20) [see explanation under features [3] and [4c] of claim 1, above],
[4a] wherein the semiconductor nanosheets 20 are disposed within the cavity
[4b] such that a region above the semiconductor nanosheets 20 is free of the dielectric material 16 [as shown in each of Figs. 2 and 11], and
[4c] a portion of the cavity resides in between the semiconductor nanosheets 20 [see explanation under features [3] and [4c] of claim 1, above].
IV. Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Cheng.
Claims 2-4 read,
2. (Original) The device of claim 1, wherein the semiconductor nanosheets includes a high dielectric constant (high-k) material.
3. (Original) The device of claim 2, wherein the high-k material is applied to a plurality of surfaces of the semiconductor nanosheets.
4. (Original) The device of claim 2, wherein the high-k material includes one of hafnium dioxide (HfO2), aluminum oxide (Al2O3), or hafnium aluminum oxide (HfAlO).
The prior art of Lee, as explained above, discloses each of the features of claim 1.
While Lee discloses a gate insulating layer 15 formed on the nanowires (Lee: ¶ 47; Fig. 8), Lee does not indicate what the gate insulating material and does not therefore teach a high-k material as required by claims 2-4.
As explained above, Cheng, like Lee, teaches a stacked nanosheet chemFET having a gate insulating layer one the exposed surfaces of the nanosheets within the cavity. Cheng further teaches that the gate insulating material is a high-k dielectric including the materials recited in claim 4 (Cheng: ¶ 65).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the gate insulating layer 15 of Lee form the materials in Cheng because Lee merely fails to indicate any specific dielectric such that one having ordinary skill in the art would use materials known to be suitable for the same purpose of forming a nanosheet chemFET, such as the materials recited in Cheng. As such using a high-k material and any of the specific high-k materials amounts to obvious material choice. (See MPEP 2144.07.)
This is all of the limitations of claims 2-4.
B. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of US 2017/0336347 (“Ram”).
Claim 8 reads,
8. (Original) The device of claim 1, further comprising
[1] a second dielectric layer beneath the first semiconductor layer and
[2] a second semiconductor layer beneath the second dielectric layer,
[3] the second dielectric layer and the second semiconductor layer defining a back gate structure.
The prior art of Lee, as explained above, discloses each of the features of claim 1.
With regard to claim 8, Lee further discloses,
8. (Original) The device of claim 1, further comprising
[1] a second dielectric layer 11 [¶ 39] beneath the first semiconductor layer 13(21)/12(20) and
[2] a second … layer 10 [i.e. “substrate 10” beneath the second dielectric layer 11],
[3] … [not taught] …
With regard to feature [2] of claim 8, Lee does not indicate what the material of the substrate 10 is.
With regard to feature [3] of claim 8,
[3] the second dielectric layer and the second semiconductor layer defining a back gate structure.
Lee does not disclose a back gate and does not therefore teach the limitations of feature [3].
Ram, like Lee, teaches a silicon nanostructure-channel FET used as a chemical sensor formed from a substrate including an active Si nanowire channel 101 supported on a buried oxide 111, in turn, on a bulk substrate 112 (Ram: ¶ 71; Figs. 1-2). Ram further teaches that the bulk substrate 112 is silicon (id.).
Also like Lee, Ram teaches a gate dielectric 113 formed on the Si nanowire channel (Ram: ¶ 72). Still further like Lee’s front gate electrode 31, Ram teaches a front gate electrode or “reference electrode 104” to which a “front gate voltage (VGS)” is applied (Ram: ¶¶ 81-82).
Ram further teaches that the chemFET includes a back gate formed by the buried oxide 111 and bulk silicon substrate 112 (Ram: ¶¶ 73, 82) to which a back gate contact 108 is made, the back gate used to tune the threshold voltage of the transistor (Ram: ¶ 71). Ram teaches that the combination of the front gate 104 and back gate 111/112 are used to improve the sensitivity of the sensor (Ram: ¶¶ 80-82), the front gate used to “to keep the electrochemical potential drop over the electrode-electrolyte interface stable (as a result, to keep the electrochemical potential of the solution stable) and the readout signal reliable” (Ram: ¶ 81).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the substrate 10 of Lee from bulk silicon because Lee merely fails to indicate any specific material such that one having ordinary skill in the art would use materials known to be suitable for the same purpose of forming a nanosheet chemFET, such as the bulk silicon substrate material taught in Ram.
In addition, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the insulating layer 11 of Lee and the bulk silicon substrate 10 of Lee/Ram a back-gate electrode, in order to tune the threshold voltage, in order to keep the electrochemical potential of the analyte solution stable, thereby jointly improving the sensitivity of the FET sensor, as taught in Ram. As such, RAM may be seen as an improvement to Lee in this aspect. (See MPEP 2143.)
This is all of the limitations of claim 8.
C. Claims 9 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Ram, as applied to claim 8 above, and further in view of US 2020/0182826 (“Liu”).
Claim 9 reads,
9. The device of claim 8, wherein the back gate structure includes a metallic contact.
The prior art of Lee in view of Ram, as explained above, teaches each of the features of claim 8.
While Ram shows that the back gate contact 108, Ram does not teach that the material of the contact is metal, as required by claim 9.
Liu, like each of Lee and Ram, teaches a FET used as a chemical sensor including a back side oxide 232 (BOX) on a supporting bulk silicon substrate 228 (Liu: title, abstract ¶ 54; Fig. 3). Like Ram, Liu teaches a back gate 234/242 formed using the back side BOX(232)/bulk Si substrate(228) to apply a back side gate potential Vg3 (Liu: Fig. 3; ¶ 58). Liu further teaches that the contact 260 to the back side gate is made from metal, i.e. “gate terminals 258, 260, 262 may be in the form of metal contacts” (Liu: ¶ 58; emphasis added).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the contact to the back gate of Lee/Ram from metal because Liu teaches that metal is suitable for forming a contact to a back side gate electrode used as a sensing FET. As such, the selection of metal for the back gate contact amount to obvious material choice. (See MPEP 2144.07.)
This is all of the features of claim 9.
Claim 15 reads,
15. (Currently Amended) An analyte sensor device, comprising:
[1] a first semiconductor layer including a source region, a drain region and a stack of semiconductor nanosheets extending between the source region and the drain region;
[2] a first dielectric layer including a dielectric material on the first semiconductor layer;
[3] a cavity extending through the first dielectric layer and the first semiconductor layer,
[4a] wherein the semiconductor nanosheets are disposed within the cavity
[4b] such that a region above the semiconductor nanosheets is open and free of the dielectric material, and
[4c] a portion of the cavity resides in between the semiconductor nanosheets, and
[5] wherein the cavity includes a front gate terminal; and
[6] a back gate structure defined by a second dielectric layer and a second semiconductor layer disposed beneath the first semiconductor layer,
[7] wherein the back gate structure, the source region and the drain region each include a metallic contact.
With regard to claim 15, Lee discloses, generally in Figs. 2 and 11,
15. (Currently Amended) An analyte sensor device 200 [¶ 31; Fig. 2] comprising:
[1] a first semiconductor layer 13(21)/12(20) including a source region [i.e. region below source electrode S, 30], a drain region [i.e. region below drain electrode D, 30] and a stack of semiconductor nanosheets [i.e. nanowires 20] extending between the source region and the drain region [¶¶ 8, 32-33, 41, 45, 52];
[2] a first dielectric layer 16 [¶ 54] including a dielectric material on the first semiconductor layer 13(21)/12(20); and
[3] a cavity [not given a reference character] extending through the first dielectric layer 16 and the first semiconductor layer 13(21)/12(20) [see explanation under claim 1, above],
[4a] wherein the semiconductor nanosheets 20 are disposed within the cavity
[4b] such that a region above the semiconductor nanosheets 20 is open and free of the dielectric material 16 [as shown in each of Figs. 2 and 11], and
[4c] a portion of the cavity resides [as explained under claim 1, above] in between the semiconductor nanosheets 20 [as shown in each of Figs. 2 and 11], and
[5] wherein the cavity includes a front gate terminal 31 disposed therein [¶ 52];
[6] … [not taught] …
[7] wherein … the source region S, 30 and drain region D, 30 each include a metallic contact [S and D in Fig. 2 and 30 in Fig. 11 (¶¶ 53-54)].
With regard to features [6] of claim 15, as explained above under claim 1, Lee does not disclose a back gate structure formed by the insulating layer 11 of Lee and the underlying bulk silicon substrate 10 of Lee/Ram is obvious in view of Ram for the reasons explained above under claim 8 (supra), which is applied here.
With regard to feature [7] of claim 15, Ram does not indicate that the contact to the back gate, used in Lee, is metal. However, this is obvious for the reasons explained under claim 9, above, which is applied here.
This is all of the limitations of claim 15.
D. Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Ram and Liu, as applied to claim 14 above, and further in view of Cheng.
Claims 16 and 17 read,
16. (Original) The device of claim 15, wherein the semiconductor nanosheets includes a high dielectric constant (high-k) material.
17. The device of claim 16, wherein the high-k material includes one of hafnium dioxide (HfO2), aluminum oxide (Al2O3), or hafnium aluminum oxide (HfAlO).
The prior art of Lee in view of Ram and Liu, as explained above, teaches each of the features of claim 15.
As explained above under the rejection of claims 2-4 over Lee in view of Cheng, while Lee discloses a gate insulating layer 15 formed on the nanowires (Lee: ¶ 47; Fig. 8), Lee does not indicate what the gate insulating material and does not therefore teach a high-k material as required by claims 2-4.
As explained above, Cheng, like Lee, teaches a stacked nanosheet chemFET having a gate insulating layer one the exposed surfaces of the nanosheets within the cavity. Cheng further teaches that the gate insulating material is a high-k dielectric including the materials recited in claim 17 (Cheng: ¶ 65).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the gate insulating layer 15 of Lee form the materials in Cheng because Lee merely fails to indicate any specific dielectric such that one having ordinary skill in the art would use materials known to be suitable for the same purpose of forming a nanosheet chemFET, such as the materials recited in Cheng. As such using a high-k material and any of the specific high-k materials amounts to obvious material choice. (See MPEP 2144.07.)
This is all of the limitations of claims 16-17.
With regard to claim 18, Lee further discloses,
18. (Original) The device of claim 17, wherein the cavity is configured to hold an analyte [i.e. “target material 41” as shown in Fig. 2 of Lee].
Claim 19 and 20 read,
19. (Original) The device of claim 18, wherein sensing a property of the analyte is implemented by:
[1] setting a source voltage Vs to ground;
[2] biasing a drain/source voltage VDS to approximately 0.1 V; and
[3] sweeping a back gate voltage VBG and recording a threshold voltage Vth at the back gate structure.
20. (Original) The device of claim 19, wherein the back gate voltage VBG is swept positively for an NFET and negatively for a PFET.
The limitations recited in claims 19 and 20 are statements of intended use and fail to have patentable weight for failing to require any additional structural element. It is well settled that (1) “apparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original) and (2) a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). (See MPEP 2114(II).)
E. Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Lee.
Claim 21 reads,
21. (Currently Amended) A device for analyte sensing, the device comprising:
[1] a first semiconductor layer including a source region, a drain region and a stack of semiconductor nanosheets extending between and contacting the source region and the drain region;
[2] a first dielectric layer including a dielectric material on the first semiconductor layer; and
[3] a cavity extending through the first dielectric layer and the first semiconductor layer,
[4a] wherein the semiconductor nanosheets are disposed within the cavity
[4b] such that a region above the semiconductor nanosheets is free of the dielectric material, and
[4c] a portion of the cavity resides in between the semiconductor nanosheets.
The prior art of Chang, as explained above, discloses each of the features of claim 21.
To the extent that Applicant may amend claim 21 to require that none of the dielectric material used to form the cavity extends over the nanosheets, then this would be a difference between Cheng and claim 21.
Lee teaches an embodiment having the additional dielectric 17 over the nanosheets 20 (Lee: Fig. 12: ¶¶ 55-56), in addition to the embodiment in which there is no additional dielectric layer 17 over the cavity and therefore over the nanosheets 20, as shown in Figs. 2 and 11 of Lee (Lee: ¶ 54). As such, Lee provides evidence that it is a matter of design choice to have additional dielectric material 17 over the dielectric material 16 forming the cavity around the nanosheets 20 or not have said additional dielectric material.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to omit the additional dielectric layer discussed in Cheng that is deposited in Fig. 11 of Cheng over the dielectric layer 110 of Cheng in Fig. 10, as taught in Lee, in order to make a chemFET having an open top, such as that shown in Figs. 2 and 11 of Lee, which is a matter of design choice, as evidenced by Lee. (See MPEP 2143.)
F. Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Lee, Ram, and US 2012/0214172 (“Chen”).
Claim 1 reads,
1. (Currently Amended) A device for analyte sensing, the device comprising:
[1] a first semiconductor layer including a source region, a drain region and a stack of semiconductor nanosheets extending between the source region and the drain region;
[2] a first dielectric layer including a dielectric material on the first semiconductor layer; and
[3] a cavity extending through the first dielectric layer and the first semiconductor layer,
[4a] wherein the semiconductor nanosheets are disposed within the cavity
[4b] such that a region above the semiconductor nanosheets is open and free of the dielectric material, and
[4c] a portion of the cavity resides in between the semiconductor nanosheets, and
[5] wherein the cavity includes a front gate terminal disposed therein.
With regard to claims 1-6, Cheng as modified according to Lee as explained under the rejection of claim 21, above teaches, generally in Figs. 14-16 of Cheng, as follows:
1. (Currently Amended) A device 10 for analyte sensing [abstract; ¶¶ 1, 4-6, 29, 30, 77-82; “A stacked nanofluidics sensor is formed in the second region 30” (¶ 78)], the device comprising:
[1] a first semiconductor layer 114, 314 including a source region 314, a drain region 314 and a stack of semiconductor nanosheets 114 extending between the source region 314 and the drain region 314 [¶¶ 51-54, ; Figs. 5, 14, 16];
[2] a first dielectric layer 110 [¶¶ 55-56] on the first semiconductor layer 114, 314 [Figs. 6, 16]; and
[3] a cavity 318, 330 extending through the first dielectric layer 110 and the first semiconductor layer 114, 314 [¶ 79; Figs. 7, 14, 16],
[4a] wherein the semiconductor nanosheets 114 are disposed within the cavity 318, 330
[4b] such that a region above the semiconductor nanosheets 114 is free of the dielectric material [as taught by Lee (supra)], and
[4c] a portion 318 of the cavity 318, 330 resides in between the semiconductor nanosheets 114 [as shown in Figs. 7, 14, 16], and
[5] … [not taught] … .
With regard to feature [5] of claim 1 and claim 8,
[5] wherein the cavity includes a front gate terminal disposed therein.
8. (Original) The device of claim 1, further comprising
[1] a second dielectric layer beneath the first semiconductor layer and
[2] a second semiconductor layer beneath the second dielectric layer,
[3] the second dielectric layer and the second semiconductor layer defining a back gate structure.
With regard to feature [5] of claim 1, Cheng does not disclose a front gate terminal in the cavity 330/318. Cheng does, however, state that the analyte, i.e. “sample”, in the cavity 330/318, can have an “electrical signal”, i.e. electric potential, applied to it (¶ 81), which at least implies a means for applying said electric potential.
With regard to claim 8, Cheng further teaches that the substrate 100 can be a “a bulk substrate including an insulating layer or buried oxide (BOX) layer formed thereon” (Cheng: ¶ 37), which therefore includes a second dielectric layer, i.e. the BOX, under the first semiconductor layer 110, and a second semiconductor layer, i.e. the bulk substrate of e.g. Si, beneath the BOX (id.), as required by features [1] and [2] of claim 8. Cheng does not disclose that the bulk substrate and BOX form a back gate as required by feature [3] of claim 8.
Ram, like Cheng, teaches a silicon nanostructure-channel FET used as a chemical sensor formed from a SOI substrate including an active Si nanowire channel 101 supported on a buried oxide 111, in turn, on a bulk silicon substrate 112 (Ram: ¶ 71; Figs. 1-2). Also like Chen, Ram teaches a high-k gate dielectric 113 formed on the Si nanowire channel (Ram: ¶ 72). Ram further teaches that the FET sensor includes both (1) a front gate electrode or “reference electrode 104” to which a “front gate voltage (VGS)” is applied (Ram: ¶¶ 81-82) and (2) and a back gate formed by the buried oxide 111 and bulk substrate 112 (Ram: ¶¶ 73, 82) to which a back gate contact 108 is made, the back gate used to tune the threshold voltage of the transistor (Ram: ¶ 71). Ram teaches that the combination of the front gate 104 and back gate are used to improve the sensitivity of the sensor (Ram: ¶¶ 80-82), the front gate used to “to keep the electrochemical potential drop over the electrode-electrolyte interface stable (as a result, to keep the electrochemical potential of the solution stable) and the readout signal reliable” (Ram: ¶ 81).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the BOX and underlying bulk Si substrate of Cheng a back-gate electrode, in order to tune the threshold voltage, and to include the reference or front gate electrode, in order to keep the electrochemical potential of the analyte solution stable, thereby jointly improving the sensitivity of the FET sensor, as taught in Ram. As such, RAM may be seen as an improvement to Cheng in this aspect. (See MPEP 2143.)
Chen is included for showing that there is a reasonable likelihood of success in including a back gate electrode in the FET sensor of Cheng—despite the nanochannels 114 of Cheng being suspended, which is a difference between Cheng and Ram. In this regard, Chen, like Cheng, teaches a FET chemical sensor 10 including a suspended nanosheet channel 35 extending between a source 25 and drain 30, the semiconductor nanosheet channel 35 disposed over an underlying dielectric layer 20 (SiO2) which is, in turn on an underlying silicon substrate 15 (Chen: ¶ 42; Figs. 1(a)-1(b)). Chen further teaches that the stack 15/20 is a back gate structure used to apply a gate potential, Vg, to the graphene channel 35 for characterization (Chen: ¶¶ 66, 71; Fig. 12(a)) and during sensing (Chen: ¶¶ 79-81; Fig. 9(a)). Fig. 9(a) of Chen shows that the drain current Id can be adjusted by changing the back gate voltage Vg (Chen: ¶ 81). Therefore, despite the semiconductor channel 35 being suspended over underlying dielectric layer 20, the carriers in said semiconductor channel 35 can still be controlled by the back gate. Therefore, there is a reasonable expectation that the suspended nanochannels 114 of Cheng can also have the carriers therein controlled by the back gate of Cheng/Ram formed as explained above.
This is all of the limitations of claims 1 and 8.
With regard to claims 2-6, Cheng further discloses,
2. (Original) The device of claim 1, wherein the semiconductor nanosheets 114 includes a high dielectric constant (high-k) material 116 [¶¶ 63-65; Figs. 7-8, 14, 16].
3. (Original) The device of claim 2, wherein the high-k material 116 is applied to a plurality of surfaces of the semiconductor nanosheets 114 [¶¶ 63-65].
4. (Original) The device of claim 2, wherein the high-k material 116 includes one of hafnium dioxide (HfO2), aluminum oxide (Al2O3), or hafnium aluminum oxide (HfAlO) [¶ 65].
5. (Original) The device of claim 1, wherein the cavity 318, 330 is configured to hold an analyte [¶ 79; “in operation, a fluid sample for analysis is accepted into one or both reservoirs 330 and flows through the channels 318”].
6. (Original) The device of claim 5, wherein the device comprises and ion sensitive field effect transistor (ISFET).
With regard to claim 6, Cheng does not state that the stacked nanosheet transistor sensor is sensitive to ions. However, the use of the sensor to sense ions is a statement of intended use and fails to have patentable weight beyond the implied structural features necessary to make the device capable of sensing ions. As to the structural features, the stacked nanosheet transistor of Cheng includes all of the features of at least claims 1-5, particularly the high-k gate dielectric material 116, that is ion sensitive as admitted in the Instant Application (at ¶ 14: “a deposited film of hafnium dioxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), etc., that acts as a sensing membrane, capable of interacting with H+ ions of the analyte to sense properties such as acidity (pH) levels”). As such, it is held, absent evidence to the contrary, that the stacked nanosheet transistor of Cheng is capable of sensing ions, which is all that is required. As such, the burden of proof is shifted to Applicant to prove the contrary. (See MPEP 2112(I)-(V).)
With regard to claim 7, Cheng further discloses,
7. (Original) The device of claim 1, wherein the source region 314 and drain region 314 each include a metallic contact 316 [¶ 76, noting that the gate contact 230 and source/drain contacts 216, 316 are simultaneously formed; and ¶ 89].
G. Claims 9 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Ram and Chen, as applied to claim 8 above, and further in view of US 2020/0182826 (“Liu”).
Claim 9 reads,
9. The device of claim 8, wherein the back gate structure includes a metallic contact.
The prior art of Cheng in view of Ram and Chen, as explained above, teaches each of the features of claim 8.
While Ram shows that the back gate contact 108, Ram does not teach that the material of the contact is metal, as required by claim 9.
Liu, like each of Cheng, Ram, and Chen, teaches a FET used as a chemical sensor including a back side oxide 232 (BOX) on a supporting bulk silicon substrate 228 (Liu: title, abstract ¶ 54; Fig. 3). Like Cheng, the substrate in Liu is SOI (Liu: ¶ 54). Like each of Ram and Chen, Liu teaches a back gate 234/242 formed using the back side BOX(232)/bulk Si substrate(228) to apply a back side gate potential Vg3 (Liu: Fig. 3; ¶ 58). Liu further teaches that the contact 260 to the back side gate is made from metal, i.e. “gate terminals 258, 260, 262 may be in the form of metal contacts” (Liu: ¶ 58; emphasis added).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the contact to the back gate of Cheng/Ram from metal because Liu teaches that metal is suitable for forming a contact to a back side gate electrode used as a sensing FET. As such, the selection of metal for the back gate contact amount to obvious material choice. (See MPEP 2144.07.)
This is all of the features of claim 9.
Claim 15 reads,
15. (Currently Amended) An analyte sensor device, comprising:
[1] a first semiconductor layer including a source region, a drain region and a stack of semiconductor nanosheets extending between the source region and the drain region;
[2] a first dielectric layer on the first semiconductor layer;
[3] a cavity extending through the first dielectric layer and the first semiconductor layer,
[4a] wherein the semiconductor nanosheets are disposed within the cavity
[4b] such that a region above the semiconductor nanosheets is open and free of the dielectric material, and
[4c] a portion of the cavity resides in between the semiconductor nanosheets, and
[5] wherein the cavity includes a front gate terminal; and
[6] a back gate structure defined by a second dielectric layer and a second semiconductor layer disposed beneath the first semiconductor layer,
[7] wherein the back gate structure, the source region and the drain region each include a metallic contact.
With regard to claim 15, Cheng as modified according to Lee as explained under the rejection of claim 21, above teaches, generally in Figs. 14-16 of Cheng, as follows:
15. (Currently Amended) An analyte sensor device 10 [abstract; ¶¶ 1, 4-6, 29, 30, 77-82; “A stacked nanofluidics sensor is formed in the second region 30” (¶ 78)], comprising:
[1] a first semiconductor layer 114, 314 including a source region 314, a drain region 314 and a stack of semiconductor nanosheets 114 extending between the source region 314 and the drain region 314 [¶¶ 51-54, ; Figs. 5, 14, 16];
[2] a first dielectric layer 110 [¶¶ 55-56] on the first semiconductor layer 114, 314 [Figs. 6, 16];
[3] a cavity 318, 330 extending through the first dielectric layer 110 and the first semiconductor layer 114, 314 [¶ 79; Figs. 7, 14, 16],
[4a] wherein the semiconductor nanosheets 114 are disposed within the cavity 318, 330
[4b] such that a region above the semiconductor nanosheets 114 is free of the dielectric material [as taught by Lee (supra)], and
[4c] a portion 318 of the cavity 318, 330 resides in between the semiconductor nanosheets 114 [as shown in Figs. 7, 14, 16], and
[5] … [not taught] …
[6] … a second dielectric layer [i.e. the BOX portion of substrate 100] and a second semiconductor layer [i.e. the bulk Si substrate portion of substrate 100] disposed beneath the first semiconductor layer [Cheng: ¶ 37, supra],
[7] wherein … the source region 314 and the drain region 314 each include a metal contact 316 [¶¶ 74, 76].
With regard to features [5]-[6] of claim 15, as explained above under claim 1, Cheng does not disclose a front gate terminal in the cavity 330/318 or a back gate structure. However, the inclusion of the front gate terminal and the back gate are obvious in view of Ram and Chen for the reasons explained above under claims 1 and 8 (supra).
With regard to feature [7] of claim 15, the conducting contacts 316 to each of the source and drain 314 being metal, Cheng states that the contacts are made from “conducting material or combination of conducting materials” (Cheng: ¶ 74). Cheng also states that the source and drain contacts 216, 316 can be made “concurrently” with the gate contact 230, which may be made from metal (Cheng: ¶ 76).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the contacts 316 to each of the source and drain 314 from metal because it is a “conducting material” and because Cheng suggests that the contacts 316 may be the same material as the gate contact 230 and therefore metal.
Further with regard to feature [8] of claim 15, as explained above under claim 9, Ram does not teach that the contact to the back gate structure that is used in Cheng is made from metal. However, using metal for the contact to the back gate structure is obvious in view of Liu for the same reasons as explained under claim 9, above, which are applied equally here.
With regard to features 16-18, Cheng further discloses,
16. The device of claim 15, wherein the semiconductor nanosheets 114 includes a high dielectric constant (high-k) material 116 [¶¶ 63-65].
17. The device of claim 16, wherein the high-k material includes one of hafnium dioxide (HfO2), aluminum oxide (Al2O3), or hafnium aluminum oxide (HfAlO) [¶ 65].
18. The device of claim 17, wherein the cavity 318/330 is configured to hold an analyte [¶¶ 78-79].
Claim 19 and 20 read,
19. The device of claim 18, wherein sensing a property of the analyte is implemented by:
[1] setting a source voltage VS to ground;
[2] biasing a drain/source voltage VDS to approximately 0.1 V; and
[3] sweeping a back gate voltage VBG and recording a threshold voltage Vth at the back gate structure.
20. The device of claim 19, wherein the back gate voltage VBG is swept positively for an NFET and negatively for a PFET.
The limitations recited in claims 19 and 20 are statements of intended use and fail to have patentable weight for failing to require any additional structural element. It is well settled that (1) “apparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original) and (2) a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). (See MPEP 2114(II).)
H. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Lee, Ram, and Chen, as applied to claim 1 above, and further in view of CN 109427908 A (“Gao”).
All citations to Gao are from the machine language translation attached with this Office action.
Claim 10 reads,
10. The device of claim 1, further comprising a plurality of separated semiconductor nanosheet stacks within the cavity and extending between the source region and the drain region.
The prior art of Cheng in view of Lee, Ram, and Chen, as explained above, teaches each of the features of claim 1.
Cheng does not teach including additional stacks of semiconductor nanosheets within the same cavity, i.e. “reservoir 330”.
Gao, like Cheng, teaches a FET used for a sensor including a stack of nanochannels 5111 suspended between source and drain regions over and SOI substrate 11 (Gao: Figs. 12-14; p. 9, lines 26-44). Although the nanochannels are Si nanowires, versus nanosheets, Gao further teaches that there are a plurality of separate stacks of Si nanowires as shown in the overhead view in Figs. 4, 6, 8, 10, and 12.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include plural, separate stacks of nanosheets 114 in the same cavity 330 in Cheng, e.g. in order to increase the sensitivity of the sensor by increasing the total sensitive surface area with the additional stacks of nanosheets.
The courts have held that mere duplication of parts has no patentable significance unless a new or unexpected result is produced. See In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
V. Response to Arguments
Applicant’s argument submitted 02/10/2026 with regard to the rejection of claim 21 over Cheng have been considered but are not fully persuasive. Applicant argues that Cheng does not teach the newly added feature requiring the dielectric material of the first dielectric layer over the source and drain regions to not be over the nanosheets 114 (Remarks filed 02/10/2026: pp. 6-7). Examiner respectfully disagrees for the reasons explained in the rejection. Again, Fig. 10 of Cheng shows that the first dielectric layer 110 formed over the top surface of the nanosheets 114. A second dielectric layer that may be, but is not required to be, the same material as that used for the first dielectric layer 110 shown in Fig. 10 is subsequently deposited in Fig. 11:
[0071] Referring now to FIG. 11, a step including forming additional dielectric on the ILD 110 of the semiconductor device 10 is depicted according to an embodiment of the present invention.
(Cheng: ¶ 71; emphasis added)
Therefore the claimed “dielectric material” of the claimed “first dielectric layer” 110 of Cheng is not over the nanosheets 114, because the dielectric material is the “additional dielectric on the ILD 110” (id.) and therefore not the dielectric material of the first dielectric layer 110 shown in Fig. 10.
The remaining of Applicant’s arguments are moot because the new grounds of rejection do not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814