Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 18, and 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 18, and 19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The present application under examination discloses “in FIG. 6, i.e., in the range from the depth B to the depth A along the dotted line 70 in FIG. 8, the potential distribution is such that the avalanche multiplication does not take place.” However, the present application under examination does not discloses or suggest the limitation of “the avalanche multiplication region is not formed in a region where the third semiconductor region does not overlap the first semiconductor region in the planar view” as now specified in claims 1, 18, and 19.
Claims 3-12, 15-17, and 21-22 are rejected as if it depend on rejected claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-6, 8-12, 18-19, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Shimada et al. (U.S. 2024/0213281 A1, hereinafter refer to Shimada) in view of Iwata (U.S. 2021/0057463 A1, hereinafter refer to Iwata) and Kobayashi et al. (WO 2019/026719 A1, hereinafter refer to Kobayashi).
Regarding Claim 1: Shimada discloses a photoelectric conversion apparatus (see Shimada, Figs.1 and 9-10 as shown below and ¶ [0001]) comprising
PNG
media_image1.png
437
866
media_image1.png
Greyscale
PNG
media_image2.png
454
592
media_image2.png
Greyscale
an avalanche diode (21) disposed in a semiconductor layer having a first surface and a second surface facing the first surface (see Shimada, Figs.1 and 10 as shown above and ¶ [0069]- ¶ [0045]),
wherein the avalanche diode (21) includes:
a first semiconductor region (43) of a first conductivity type disposed at a first depth (see Shimada, Fig.10 as shown above);
a second semiconductor region (44) of a second conductivity type disposed at a second depth deeper from the second surface than the first depth (see Shimada, Fig.10 as shown above);
a third semiconductor region (42) disposed at an edge of the first semiconductor region (43) in a planar view (see Shimada, Figs.9-10 as shown above);
wherein the photoelectric conversion apparatus (see Shimada, Figs.9-10 as shown above) comprises:
a first wiring (51) connected to the first semiconductor region (43) (see Shimada, Fig.10 as shown above);
a second wiring (52) connected to the second semiconductor region (44) (see Shimada, Fig.10 as shown above); and
wherein an avalanche multiplication region (47) is formed across the first semiconductor region (43) and the second semiconductor region (44) (see Shimada, Fig.10 as shown above, ¶ [0092], ¶ [0096], and ¶ [0099]).
Shimada is silent upon explicitly disclosing wherein the avalanche multiplication region is formed in a region where the third semiconductor region overlaps the first semiconductor region in the planar view, and is not formed in a region where the third semiconductor region does not overlap the first semiconductor region in the planar view.
For support see Iwata, which teaches wherein the avalanche multiplication region (310) is formed in a region where the third semiconductor region (331) overlaps the first semiconductor region (301) in the planar view, and is not formed in a region where the third semiconductor region (331) does not overlap the first semiconductor region (301) in the planar view (note: Figs.9 and 10 demonstrates an potential distribution (potentials relative to electrons serving as signal charges) in a section taken along a broken line K-K′ (center line) which the third semiconductor region (331) overlaps the first semiconductor region (301); hence, the electric charges that pass through the along a broken line K-K′ (center line) is subjected to the avalanche multiplication) (see Iwata, Figs.3, 9, and 10 as shown below and ¶ [0120]).
PNG
media_image3.png
465
420
media_image3.png
Greyscale
PNG
media_image4.png
284
566
media_image4.png
Greyscale
PNG
media_image5.png
300
465
media_image5.png
Greyscale
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Shimada and Iwata to recognize and utilize the electric charges the electric charges that pass through the along third semiconductor region of Shimada overlaps the first semiconductor region as avalanche multiplication region as taught by Iwata in order to reduce crosstalk between adjacent avalanche diodes and reduce the size of each pixel while suppressing an increase in dark current in a photoelectric conversion apparatus using avalanche diodes.
Note: the discovery of a previously unappreciated property of the Shimada prior art composition, or of a scientific explanation for the Shimada prior art’s, does not render the old composition patentably new to the discoverer.
The combination of Shimada and Iwata is silent upon explicitly disclosing wherein a third wiring disposed at a wiring layer and not connected to the avalanche diode, at least a part of the third wiring overlapping with the third semiconductor region in a planar view,
wherein the third wiring does not overlap with the first semiconductor region in a planar view,
wherein a third voltage to be supplied to the third wiring is a value between a first voltage to be supplied to the first wiring and a second voltage to be supplied to the second wiring.
For support see Kobayashi, which teaches wherein a third wiring (63M1) disposed at a wiring layer and not connected to the avalanche diode, at least a part of the third wiring (63M1) overlapping with the third semiconductor region (32) in a planar view (see Kobayashi, Figs.30-31 as shown below and ¶ [0001]),
wherein the third wiring (63M1) does not overlap with the first semiconductor region (32a) in a planar view (cross-sectional view) (note: Kobayashi teaches wiring 63M1 not overlapping with region 32a in cross-sectional view; hence, ordinary skill in the art before effective filing date of the claimed invention necessarily recognize that the Kobayashi wiring 63M1 not to overlap with region 32a in planar/top view) (see Kobayashi, Figs.30-31 as shown below and ¶ [0001]),
wherein a third voltage to be supplied to the third wiring (63M1) is a value between a first voltage to be supplied to the first wiring (52M1) and a second voltage to be supplied to the second wiring (51M1) (NOTE: claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim) (see Kobayashi, Figs.30-31 as shown below and ¶ [0001]).
PNG
media_image6.png
336
540
media_image6.png
Greyscale
PNG
media_image7.png
432
520
media_image7.png
Greyscale
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Shimada, Iwata, and Kobayashi to enable third wiring not to connect to the semiconductor layer, at least a part of the third wiring overlapping with the third semiconductor region in a planar view as taught by Kobayashi in order to obtain a SPAD pixel chip that suppress occurrence of noise.
Regarding Claim 3: Shimada as modified teaches a photoelectric conversion apparatus as set forth in claim 1 as above. The combination of Shimada and Kobayashi further teaches wherein the wiring layer includes a plurality of wiring layers (V1/M1/VE/35/37) (see Kobayashi, Figs.30-31 as shown above),
wherein the first (52M1) and third wirings (Fig.30, 63M1/Fig.46, 81/83M1) are formed in the plurality of wiring layers stacked in layers on a side of the second surface (see Kobayashi, Figs.30-31 as shown above and Fig.46), and
wherein the third wiring (Fig.30, 63M1/Fig.46, 81/83M1) is formed in a position that is further from the second surface than a contact connecting the first semiconductor region (32a) and the first wiring (52M1), and is closer to the second surface than the first wiring (52M1) (see Kobayashi, Figs.30-31 as shown above and Fig.46).
NOTE: claims to a wiring layers which read on the prior art except with regard to the position of the wiring layers were held unpatentable because shifting the position of the wiring layers would not have modified the operation of the device.
Regarding Claim 4: Shimada as modified teaches a photoelectric conversion apparatus as set forth in claim 3 as above. The combination of Shimada and Kobayashi further teaches wherein at least a part of the first wiring (52M1/35) overlaps with at least a part of the third wiring (63M1) in a planar view (see Kobayashi, Figs.30-31 as shown above and Figs.46-48).
Regarding Claim 5: Shimada as modified teaches a photoelectric conversion apparatus as set forth in claim 1 as above. The combination of Shimada and Kobayashi further teaches wherein the wiring layer includes a plurality of wiring layers (V1/M1/VE/35/37) (see Kobayashi, Figs.30-31 as shown above),
wherein the second (51M1/37) and third wirings (Fig.30, 63M1/Fig.46, 81/83M1) are formed in the plurality of wiring layers stacked in layers on a side of the second surface (see Kobayashi, Figs.30-31 as shown above and Figs.46-48), and
wherein the third wiring (Fig.30, 63M1/Fig.46, 81/83M1) is formed in a position that is further from the second surface a contact connecting the second semiconductor region (33) and the second wiring (51M1/37), and is closer to the second surface than the second wiring (51M1) (see Kobayashi, Figs.30-31 as shown above and Figs.46-48).
NOTE: Claims to a wiring layers which read on the prior art except with regard to the position of the wiring layers were held unpatentable because shifting the position of the wiring layers would not have modified the operation of the device.
Regarding Claim 6: Shimada as modified teaches a photoelectric conversion apparatus as set forth in claim 5 as above. The combination of Shimada and Kobayashi further teaches wherein at least a part of the second wiring (51M1/37) overlaps with at least a part of the third wiring (Fig.30, 63M1/Fig.46, 81/83M1) in a planar view (see Kobayashi, Figs.30-31 as shown above and Figs.46-48).
Regarding Claim 8: Shimada as modified teaches a photoelectric conversion apparatus as set forth in claim 1 as above. The combination of Shimada and Kobayashi further teaches wherein the wiring layer includes a plurality of wiring layers (V1/M1/VE/35/37) (see Kobayashi, Figs.30-31 as shown above),
wherein the third wiring (Fig.30, 63M1/Fig.46, 81/83M1) is formed in the plurality of wiring layers stacked in layers on a side of the second surface (see Kobayashi, Figs.30-31 as shown above and Figs.46-48), and
wherein the third wiring (Fig.30, 63M1/Fig.46, 81/83M1) is formed in a position that is further from the second surface than a contact connecting the first semiconductor region (32a) and the first wiring (52M1), and is closest to the second surface out of the plurality of wiring layers (see Kobayashi, Figs.30-31 as shown above and Figs.46-48).
Regarding Claim 9: Shimada as modified teaches a photoelectric conversion apparatus as set forth in claim 1 as above. The combination of Shimada and Kobayashi further teaches wherein the first (52M1) and second (51M1) wirings are formed in the same wiring layer stacked on a side of the second surface (see Kobayashi, Figs.30-31 as shown above and Figs.46-48).
Regarding Claim 10: Shimada as modified teaches a photoelectric conversion apparatus as set forth in claim 1 as above. The combination of Shimada and Kobayashi further teaches wherein the third voltage is within a range {(Van - Vca)/2} * 0.8 ≤ Vmid ≤ {(Van - Vca)/2} * 1.2 where Vca denotes the first voltage, Van denotes the second voltage, and Vmid denotes the third voltage (NOTE: claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim) (see Kobayashi, Figs.30-31 as shown above and Figs.46-48).
Regarding Claim 11: Shimada as modified teaches a photoelectric conversion apparatus as set forth in claim 1 as above. The combination of Shimada and Kobayashi further teaches wherein the third voltage is a ground voltage (NOTE: claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim) (see Kobayashi, Figs.30-31 as shown above and Figs.46-48).
Regarding Claim 12: Shimada as modified teaches a photoelectric conversion apparatus as set forth in claim 1 as above. The combination of Shimada and Kobayashi further teaches wherein a fourth semiconductor region (45, back side portion) of the second conductivity type disposed at a third depth deeper from the second surface than the second depth (see Shimada, Fig.10 as shown above).
Regarding Claim 18: Shimada discloses a photoelectric conversion system (see Shimada, Figs.1 and 9-10 as shown above and ¶ [0001]) comprising:
a photoelectric conversion apparatus comprising an avalanche diode (21) disposed in a semiconductor layer having a first surface and a second surface facing the first surface (see Shimada, Figs.1 and 10 as shown above and ¶ [0069]- ¶ [0045]),
wherein the avalanche diode (21) includes:
a first semiconductor region (43) of a first conductivity type disposed at a first depth (see Shimada, Fig.10 as shown above);
a second semiconductor region (44) of a second conductivity type disposed at a second depth deeper from the second surface than the first depth (see Shimada, Fig.10 as shown above);
a third semiconductor region (42) disposed at an edge of the first semiconductor region (43) in a planar view (see Shimada, Figs.9-10 as shown above);
wherein the photoelectric conversion apparatus (see Shimada, Figs.9-10 as shown above) comprises:
a first wiring (51) connected to the first semiconductor region (43) (see Shimada, Fig.10 as shown above);
a second wiring (52) connected to the second semiconductor region (44) (see Shimada, Fig.10 as shown above); and
wherein an avalanche multiplication region (47) is formed across the first semiconductor region (43) and the second semiconductor region (44) (see Shimada, Fig.10 as shown above, ¶ [0092], ¶ [0096], and ¶ [0099]),
a signal processing unit configured to generate an image by using a signal output by the photoelectric conversion apparatus (see Shimada, Figs.1 and 10 as shown above and Fig.30).
Shimada is silent upon explicitly disclosing wherein an avalanche multiplication region is formed in a region where the third semiconductor region overlaps the first semiconductor region in the planar view, and is not formed in a region where the third semiconductor region does not overlap with the first semiconductor region in the planar view.
For support see Iwata, which teaches wherein an avalanche multiplication region (310) is formed in a region where the third semiconductor region (331) overlaps the first semiconductor region (301) in the planar view, and is not formed in a region where the third semiconductor region (331) does not overlap with the first semiconductor region (301) in the planar view (note: Figs.9 and 10 demonstrates an potential distribution (potentials relative to electrons serving as signal charges) in a section taken along a broken line K-K′ (center line) which the third semiconductor region (331) overlaps the first semiconductor region (301); hence, the electric charges that pass through the along a broken line K-K′ (center line) is subjected to the avalanche multiplication) (see Iwata, Figs.3, 9, and 10 as shown above and ¶ [0120]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Shimada and Iwata to recognize and utilize the electric charges the electric charges that pass through the along third semiconductor region of Shimada overlaps the first semiconductor region as avalanche multiplication region as taught by Iwata in order to reduce crosstalk between adjacent avalanche diodes and reduce the size of each pixel while suppressing an increase in dark current in a photoelectric conversion apparatus using avalanche diodes.
Note: the discovery of a previously unappreciated property of the Shimada prior art composition, or of a scientific explanation for the Shimada prior art’s, does not render the old composition patentably new to the discoverer.
The combination of Shimada and Iwata is silent upon explicitly disclosing wherein a third wiring disposed at a wiring layer and not connected to the avalanche diode, at least a part of the third wiring overlapping with the third semiconductor region in a planar view,
wherein the third wiring does not overlap with the first semiconductor region in a planar view,
wherein a third voltage to be supplied to the third wiring is a value between a first voltage to be supplied to the first wiring and a second voltage to be supplied to the second wiring.
For support see Kobayashi, which teaches wherein a third wiring (63M1) disposed at a wiring layer and not connected to the avalanche diode, at least a part of the third wiring (63M1) overlapping with the third semiconductor region (32) in a planar view (see Kobayashi, Figs.30-31 as shown above and ¶ [0001]),
wherein the third wiring (63M1) does not overlap with the first semiconductor region (32a) in a planar view (cross-sectional view) (note: Kobayashi teaches wiring 63M1 not overlapping with region 32a in cross-sectional view; hence, ordinary skill in the art before effective filing date of the claimed invention necessarily recognize that the Kobayashi wiring 63M1 not to overlap with region 32a in planar/top view) (see Kobayashi, Figs.30-31 as shown above and ¶ [0001]),
wherein a third voltage to be supplied to the third wiring (63M1) is a value between a first voltage to be supplied to the first wiring (52M1) and a second voltage to be supplied to the second wiring (51M1) (NOTE: claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim) (see Kobayashi, Figs.30-31 as shown above and ¶ [0001]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Shimada, Iwata, and Kobayashi to enable third wiring not to connect to the semiconductor layer, at least a part of the third wiring overlapping with the third semiconductor region in a planar view as taught by Kobayashi in order to obtain a SPAD pixel chip that suppress occurrence of noise.
Regarding Claim 19: Shimada discloses a moving body including a photoelectric conversion apparatus (see Shimada, Figs.1 and 9-10 as shown above, Figs.30-32 and 34-35 and ¶ [0001]) comprising
an avalanche diode (21) disposed in a semiconductor layer having a first surface and a second surface facing the first surface (see Shimada, Figs.1 and 10 as shown above and ¶ [0069]- ¶ [0045]),
wherein the avalanche diode (21) includes:
a first semiconductor region (43) of a first conductivity type disposed at a first depth (see Shimada, Fig.10 as shown above);
a second semiconductor region (44) of a second conductivity type disposed at a second depth deeper from the second surface than the first depth (see Shimada, Fig.10 as shown above);
a third semiconductor region (42) disposed at an edge of the first semiconductor region (43) in a planar view (see Shimada, Figs.9-10 as shown above);
wherein the photoelectric conversion apparatus (see Shimada, Figs.9-10 as shown above) comprises:
a first wiring (51) connected to the first semiconductor region (43) (see Shimada, Fig.10 as shown above);
a second wiring (52) connected to the second semiconductor region (44) (see Shimada, Fig.10 as shown above); and
wherein an avalanche multiplication region (47) is formed across the first semiconductor region (43) and the second semiconductor region (44) (see Shimada, Fig.10 as shown above, ¶ [0092], ¶ [0096], and ¶ [0099]), and
the moving body comprising a control unit (642/631/12020) configured to control movement of the moving body by using a signal output by the photoelectric conversion apparatus ((see Shimada, Figs.1 and 9-10 as shown above, Figs.30-32 and 34-35 and ¶ [0001]).
Shimada is silent upon explicitly disclosing wherein an avalanche multiplication region is formed in a region where the third semiconductor region overlaps the first semiconductor region in the planar view, and is not formed in a region where the third semiconductor region does not overlap the first semiconductor region in the planar view.
For support see Iwata, which teaches wherein an avalanche multiplication region (310) is formed in a region where the third semiconductor region (331) overlaps the first semiconductor region (301) in the planar view, and is not formed in a region where the third semiconductor region (331) does not overlap the first semiconductor region (301) in the planar view (note: Figs.9 and 10 demonstrates an potential distribution (potentials relative to electrons serving as signal charges) in a section taken along a broken line K-K′ (center line) which the third semiconductor region (331) overlaps the first semiconductor region (301); hence, the electric charges that pass through the along a broken line K-K′ (center line) is subjected to the avalanche multiplication) (see Iwata, Figs.3, 9, and 10 as shown above and ¶ [0120]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Shimada and Iwata to recognize and utilize the electric charges the electric charges that pass through the along third semiconductor region of Shimada overlaps the first semiconductor region as avalanche multiplication region as taught by Iwata in order to reduce crosstalk between adjacent avalanche diodes and reduce the size of each pixel while suppressing an increase in dark current in a photoelectric conversion apparatus using avalanche diodes.
Note: the discovery of a previously unappreciated property of the Shimada prior art composition, or of a scientific explanation for the Shimada prior art’s, does not render the old composition patentably new to the discoverer.
The combination of Shimada and Iwata is silent upon explicitly disclosing wherein a third wiring disposed at a wiring layer and not connected to the avalanche diode, at least a part of the third wiring overlapping with the third semiconductor region in a planar view,
wherein the third wiring does not overlap with the first semiconductor region in a planar view,
wherein a third voltage to be supplied to the third wiring is a value between a first voltage to be supplied to the first wiring and a second voltage to be supplied to the second wiring.
Before effective filing date of the claimed invention the disclosed third wiring were known not to connect to the semiconductor layer, at least a part of the third wiring overlapping with the third semiconductor region in a planar view in order to obtain a SPAD pixel chip that suppress occurrence of noise.
For support see Kobayashi, which teaches wherein a third wiring (63M1) disposed at a wiring layer and not connected to the avalanche diode, at least a part of the third wiring (63M1) overlapping with the third semiconductor region (32) in a planar view (see Kobayashi, Figs.30-31 as shown above and ¶ [0001]),
wherein the third wiring (63M1) does not overlap with the first semiconductor region (32a) in a planar view (cross-sectional view) (note: Kobayashi teaches wiring 63M1 not overlapping with region 32a in cross-sectional view; hence, ordinary skill in the art before effective filing date of the claimed invention necessarily recognize that the Kobayashi wiring 63M1 not to overlap with region 32a in planar/top view) (see Kobayashi, Figs.30-31 as shown above and ¶ [0001]),
wherein a third voltage to be supplied to the third wiring (63M1) is a value between a first voltage to be supplied to the first wiring (52M1) and a second voltage to be supplied to the second wiring (51M1) (NOTE: claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim) (see Kobayashi, Figs.30-31 as shown above and ¶ [0001]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Shimada, Iwata, and Kobayashi to enable third wiring not to connect to the semiconductor layer, at least a part of the third wiring overlapping with the third semiconductor region in a planar view as taught by Kobayashi in order to obtain a SPAD pixel chip that suppress occurrence of noise.
Regarding Claim 21: Shimada as modified teaches a photoelectric conversion apparatus as set forth in claim 1 as above. The combination of Shimada and Kobayashi further teaches wherein a potential difference between the third semiconductor region and the second semiconductor region is smaller than a potential difference between the first semiconductor region and the second semiconductor region (see Shimada, Fig.10 as shown above).
Note: claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Regarding Claim 22: Shimada as modified teaches a photoelectric conversion apparatus as set forth in claim 1 as above. The combination of Shimada and Kobayashi further teaches wherein a pixel separation portion (48) having a trench structure disposed between adjacent pixels (see Shimada, Fig.10 as shown above and Fig.8A); and
a seventh semiconductor region (a portion of semiconductor region 45 which directly contacts separation portion 48) of the second conductivity type is formed around the pixel separation portion (48) (see Shimada, Fig.10 as shown above and Fig.8A),
wherein the second semiconductor region (44) and the seventh semiconductor region (a portion of semiconductor region 45 which directly contacts separation portion 48) are electrically connected (see Shimada, Fig.10 as shown above and Fig.8A).
Claim(s) 7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Shimada et al. (U.S. 2024/0213281 A1, hereinafter refer to Shimada), Iwata (U.S. 2021/0057463 A1, hereinafter refer to Iwata), and Kobayashi et al. (WO 2019/026719 A1, hereinafter refer to Kobayashi) as applied to claim 1 above, and further in view of Matsumoto (U.S. 2022/0163674 A1, hereinafter refer to Matsumoto).
Regarding Claim 7: Shimada as modified teaches a photoelectric conversion apparatus as applied to claim 1 above. The combination of Shimada, Iwata, and Kobayashi is silent upon explicitly disclosing wherein at least a part of the third wiring is made of polysilicon.
For support see Matsumoto, which teaches wherein at least a part of the third wiring (20) is made of polysilicon (see Matsumoto, Fig.9 and ¶ [0051]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Shimada, Iwata, Kobayashi, and Matsumoto to enable the third wiring to be made of polysilicon as taught by Matsumoto in order to obtain a MOS (Metal-Oxide-Semiconductor) transistor in the semiconductor substrate in a region where the pixel is not provided.
Regarding Claim 15: Shimada as modified teaches a photoelectric conversion apparatus as applied to claim 1 above. The combination of Shimada, Iwata, and Kobayashi is silent upon explicitly disclosing wherein the second surface is provided with an oxide film and a nitride film stacked in layers.
For support see Matsumoto, which teaches wherein the second surface is provided with an oxide film (23) and a nitride film (22) stacked in layers (see Matsumoto, Figs.4 and 9 and ¶ [0053]).
Thus, it would have been obvious to one of ordinary skill in the art before effective between e filing date of the claimed invention to combine the teachings of Shimada, Iwata, Kobayashi, and Matsumoto to enable the second surface to be provided with an oxide film and a nitride film stacked in layers as taught by Matsumoto in order to improve adhesion the semiconductor layer and interconnect structure and reduce current leakages.
Claim(s) 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Shimada et al. (U.S. 2024/0213281 A1, hereinafter refer to Shimada), Iwata (U.S. 2021/0057463 A1, hereinafter refer to Iwata), and Kobayashi et al. (WO 2019/026719 A1, hereinafter refer to Kobayashi) as applied to claim 1 above, and further in view of Yagi et al. (U.S. 2022/0140156 A1, hereinafter refer to Yagi).
Regarding Claim 16: Shimada as modified teaches a photoelectric conversion apparatus as applied to claim 1 above. The combination of Shimada, Iwata, and Kobayashi is silent upon explicitly disclosing wherein the semiconductor layer includes a plurality of concavo-convex structures disposed on the first surface.
For support see Yagi, which teaches wherein the semiconductor layer includes a plurality of concavo-convex structures (181) disposed on the first surface (see Yagi, Fig.8 as shown below and ¶ [0140]- ¶ [0143]).
PNG
media_image8.png
594
632
media_image8.png
Greyscale
Thus, it would have been obvious to one of ordinary skill in the art before effective between e filing date of the claimed invention to combine the teachings of Shimada, Iwata, Kobayashi, and Yagi to enable the semiconductor layer to includes a plurality of concavo-convex structures disposed on the first surface as taught by Yagi in order to increase the quantum efficiency of the photoelectric conversion portion.
Regarding Claim 17: Shimada as modified teaches a photoelectric conversion apparatus as set forth in claim 16 as above. The combination of Shimada, Iwata, Kobayashi, and Yagi is silent upon explicitly disclosing wherein at least a part of the third wiring is contained in a region where the plurality of concavo-convex structures is formed in a planar view.
However, practicing the combination of Shimada, Iwata, Kobayashi, and Yagi to enable the third wiring 63M1 to be connected to ground as taught by Kobayashi, ¶ [0103], necessarily results the claimed limitation of “at least a part of the third wiring is contained in a region where the plurality of concavo-convex structures is formed in a planar view” as now specified in claim 17.
Claim(s) 23 is rejected under 35 U.S.C. 103 as being unpatentable over Shimada et al. (U.S. 2024/0213281 A1, hereinafter refer to Shimada) in view of Kobayashi et al. (WO 2019/026719 A1, hereinafter refer to Kobayashi).
Regarding Claim 23: Shimada discloses a photoelectric conversion apparatus (see Shimada, Figs.1 and 9-10 as shown below and ¶ [0001]) comprising
an avalanche diode (21) disposed in a semiconductor layer having a first surface and a second surface facing the first surface (see Shimada, Figs.1 and 10 as shown above and ¶ [0069]- ¶ [0045]),
wherein the avalanche diode (21) includes:
a first semiconductor region (43) of a first conductivity type disposed at a first depth (see Shimada, Fig.10 as shown above);
a second semiconductor region (44) of a second conductivity type disposed at a second depth deeper from the second surface than the first depth (see Shimada, Fig.10 as shown above); and
a third semiconductor region (42) disposed at an edge of the first semiconductor region (43) in a planar view (see Shimada, Figs.9-10 as shown above);
wherein the photoelectric conversion apparatus (see Shimada, Figs.9-10 as shown above) comprises:
a first wiring (51) connected to the first semiconductor region (44) (see Shimada, Fig.10 as shown above);
a second wiring (52) connected to the second semiconductor region (44) (see Shimada, Fig.10 as shown above); and
wherein an avalanche multiplication region (47) is formed across the first semiconductor region (43) and the second semiconductor region (44) (see Shimada, Fig.10 as shown above, ¶ [0092], ¶ [0096], and ¶ [0099]).
wherein an impurity density in the third semiconductor region (42) is lower than an impurity density in the first semiconductor region (43) (note: concentration or impurity density of n is known to be lower than concentration or impurity density of n+) (see Shimada, Fig.10 as shown above and ¶ [0092]),
wherein the impurity density in the second semiconductor region (44) is lower than the impurity density in the first semiconductor region (43) (note: concentration or impurity density of n is known to be lower than concentration or impurity density of n+, in addition, Shimada teaches the impurity density in the third semiconductor region (42) equal to an impurity density in the second semiconductor region (44)) (see Shimada, Fig.10 as shown above and ¶ [0096]).
Shimada is silent upon explicitly disclosing wherein the impurity density in the third semiconductor region is lower than an impurity density in the second semiconductor region; however, Shimada teaches wherein the impurity density in the third semiconductor region (42) is equal to an impurity density in the second semiconductor region (44) (see Shimada, Fig.10 as shown above and ¶ [0096]).
Hence, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the impurity density in the third semiconductor region and second semiconductor region through routine experimentation and optimization to obtain optimal or desired avalanche multiplication region because the impurity density in the third semiconductor region and second semiconductor region is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Shimada is silent upon explicitly disclosing wherein a third wiring disposed at a wiring layer and not connected to the avalanche diode, at least a part of the third wiring overlapping with the third semiconductor region in a planar view,
wherein the third wiring does not overlap with the first semiconductor region in a planar view,
wherein a third voltage to be supplied to the third wiring is a value between a first voltage to be supplied to the first wiring and a second voltage to be supplied to the second wiring.
For support see Kobayashi, which teaches wherein a third wiring (63M1) disposed at a wiring layer and not connected to the avalanche diode, at least a part of the third wiring (63M1) overlapping with the third semiconductor region (32) in a planar view (see Kobayashi, Figs.30-31 as shown above and ¶ [0001]),
wherein the third wiring (63M1) does not overlap with the first semiconductor region (32a) in a planar view (cross-sectional view) (note: Kobayashi teaches wiring 63M1 not overlapping with region 32a in cross-sectional view; hence, ordinary skill in the art before effective filing date of the claimed invention necessarily recognize that the Kobayashi wiring 63M1 not to overlap with region 32a in planar/top view) (see Kobayashi, Figs.30-31 as shown above and ¶ [0001]),
wherein a third voltage to be supplied to the third wiring (63M1) is a value between a first voltage to be supplied to the first wiring (52M1) and a second voltage to be supplied to the second wiring (51M1) (NOTE: claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim) (see Kobayashi, Figs.30-31 as shown above and ¶ [0001]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Shimada and Kobayashi to enable third wiring not to connect to the semiconductor layer, at least a part of the third wiring overlapping with the third semiconductor region in a planar view as taught by Kobayashi in order to obtain a SPAD pixel chip that suppress occurrence of noise.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BITEW A DINKE/Primary Examiner, Art Unit 2812