DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/4/2023 and 12/2/2025 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Status
Present action: Claims 1, 2, 3, 4, and 5 through 10 and 12 through 20 are rejected, claim 11 is objected.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12 through 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites the limitation "the front surface of the cell structure" in line 9. There is insufficient antecedent basis for this limitation in the claim. The examiner believes the applicant intended “the front surface of the cell substrate” as was anteceded in line 7.
Claim 13 through 19 depend from and incorporate claim 12.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, and 4 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Mizutani (US 2021/0035965).
Regarding claim 1.
Mizutani teaches a nonvolatile memory device (fig 27a, paragraph 260) comprising: a cell substrate including portions respectively included in a cell array region, an extension region, and a pad region of the nonvolatile memory device (annotated figure 27 A), the cell substrate including a front surface and a rear surface opposite to each other and including a common source plate (18, paragraph 259) and an insulating pattern (330, paragraph 268); a mold structure (65, paragraph 268) on the front surface of the cell substrate and including a plurality of gate electrodes (46, paragraph 269) and a plurality of mold insulating films (32, paragraph 260), wherein the plurality of gate electrodes (46, paragraph 269) and the plurality of mold insulating films (32, paragraph 260) include respective first portions, and the first portions of the plurality of gate electrodes (46, paragraph 269) and the first portions of the plurality of mold insulating films (32, paragraph 260) are alternately stacked in the cell array region, and wherein the plurality of gate electrodes (46, paragraph 269) and the plurality of mold insulating films (32, paragraph 260) further include respective second portions, and the second portions of the plurality of gate electrodes (46, paragraph 269) and the second portions of the plurality of mold insulating films (32, paragraph 260) are alternately stacked in a stair shape in the extension region; a channel structure (58, paragraph 269) that extends through the mold structure (65, paragraph 268) in the cell array region and is connected to the common source plate (18, paragraph 259); a cell contact (86, paragraph 112) that extends through the mold structure (65, paragraph 268) in the extension region and is connected to at least one of the plurality of gate electrodes (46, paragraph 269); a first interlayer insulating film (160, paragraph 260) that is on the front surface of the cell substrate and extends on the mold structure (65, paragraph 268); a second interlayer insulating film (230, paragraph 262) on the rear surface of the cell substrate; an input/output pad (16, paragraph 266) on the second interlayer insulating film (230, paragraph 262) in the pad region; an input/output contact (annotated fig 27a) extending through the first interlayer insulating film (160, paragraph 260) in the pad region; and an input/output via (16V, paragraph 266) that includes portions respectively in the second interlayer insulating film (230, paragraph 262) and the cell substrate in the pad region and connects the input/output contact and the input/output pad (16, paragraph 266) to each other, wherein the common source plate (19, paragraph 259) does not overlap the cell contact and the input/output contact in a first direction that is perpendicular to the front surface of the cell substrate (fig 27a).
PNG
media_image1.png
702
930
media_image1.png
Greyscale
Regarding claim 3.
Mizutani teaches the nonvolatile memory device of claim 1, wherein an upper surface of the cell contact (86, paragraph 112) is between the front surface of the cell substrate and the rear surface of the cell substrate (annotated fig 27a).
Regarding claim 4.
Mizutani teaches the nonvolatile memory device of claim 1, wherein an upper surface of the input/output contact (annotated fig 27a) is between the front surface of the cell substrate and the rear surface of the cell substrate (annotated fig 27a).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 5, 6, 7, 9, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mizutani (US 2021/0035965) in view of Lu (US 2017/0352678)
Regarding claim 1.
Mizutani teaches a nonvolatile memory device (fig 27a) comprising:
a cell substrate including portions respectively included in a cell array region, an extension region, and a pad region of the nonvolatile memory device, the cell substrate (18,218,240,440,640,230) including a front surface (HP) and a rear surface opposite to each other and including a common source plate (18,218,240,440,640) (paragraph 259) and an insulating pattern (230) (paragraph 262); a mold structure on the front surface (HP) of the cell substrate and including a plurality of gate electrodes (46) (paragraph 260) and a plurality of mold insulating films (32) (paragraph 260), wherein the plurality of gate electrodes (46) and the plurality of mold insulating films (32) include respective first portions (fig 27a), and the first portions of the plurality of gate electrodes (46) and the first portions of the plurality of mold insulating films (32) are alternately stacked in the cell array region (paragraph 260), and wherein the plurality of gate electrodes (46) and the plurality of mold insulating films (32) further include respective second portions, and the second portions of the plurality of gate electrodes (46) and the second portions of the plurality of mold insulating films (32) are alternately stacked in a stair shape in the extension region (fig 27a); a channel structure (58) that extends through the mold structure in the cell array region and is connected to the common source plate (18,218,240,440,640) (paragraph 260) (fig 19c); a cell contact (86) that extends in the extension region and is connected to at least one of the plurality of gate electrodes (46) (paragraph 111) (fig 27a); a first interlayer insulating film (65) that is on the front surface (HP) of the cell substrate and extends on the mold structure (paragraph 260);
PNG
media_image2.png
604
1092
media_image2.png
Greyscale
an input/output pad (16) in the pad region (fig 27a) (paragraph 265); an input/output contact (8p) extending through the first interlayer insulating film (65) in the pad region (fig 27a) (paragraph 260); and an input/output via (16v) that includes portions in the cell substrate (18,218,240,440,640,230) in the pad region and connects the input/output contact (8p) and the input/output pad (16) to each other, wherein the common source plate (18,218,240,440,640) does not overlap the cell contact (86) and the input/output contact (8p) in a first direction that is perpendicular to the front surface of the cell substrate.
Mizutani does not teach a second interlayer insulating layer on the rear surface of the cell substrate in this embodiment.
Mizutani teaches a second interlayer insulating film (250) on the rear surface of the cell substrate (fig 26H) (paragraph 249); an input/output pad (16) on the second interlayer insulating film (250) in the pad region (fig 27a) (paragraph 265); an input/output contact (8p) extending through the first interlayer insulating film (65) in the pad region (fig 27a) (paragraph 260); and an input/output via that includes portions respectively in the second interlayer insulating film (250).
PNG
media_image3.png
445
726
media_image3.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a second interlayer insulating layer in order to provide more dielectric separation and protection between the die surface and associated pads and the cell structure and associated metallization.
Mizutano does not teach the cell contact extends through the mold structure.
Lu teaches a cell contact (576) that extends through the mold structure and is connected to at least one of the plurality of gate electrodes (142) (fig 10a) (paragraph 138).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the cell contact to extend through the mold structure in order to enhance power distribution without excessively increasing the footprint of a semiconductor chip is also desired (Lu paragraph 3).
Regarding claim 2.
Mizutano in view of Lu teaches the structure of claim 1.
Mizutano teaches the common source plate (18,218,240,440,640) is not in the extension region (fig 27a).
Regarding claim 5
Mizutano in view of Lu teaches the structure of claim 1.
Mizutano teaches the channel structure (58) includes an information storage film (50) and a semiconductor pattern (60) (paragraph 260); and an upper surface of the semiconductor pattern is connected to the common source plate (18,218,240,440,640) (fig 22c,27a).
Regarding claim 6.
Mizutano in view of Lu teaches the structure of claim 5.
Mizutano teaches an upper surface of the information storage film (50) is coplanar with the front surface of the cell substrate (18,218,240,440,640,230) (fig 22c) (paragraph 260)
Regarding claim 7.
Mizutano in view of Lu teaches the structure of claim 5.
Mizutano teaches the upper surface of the semiconductor pattern (60) is between the front surface of the cell substrate and the rear surface of the cell substrate (18,218,240,440,640,230) (fig 22c) (paragraph 260).
PNG
media_image4.png
256
567
media_image4.png
Greyscale
Regarding claim 9.
Mizutano in view of Lu teaches the structure of claim 1.
Mizutano teaches a cell pad in the cell array region; and a cell via that extends through on the common source plate in the cell array region and connects the common source plate and the cell pad to each other, wherein a bottom surface of the cell via is coplanar with the rear surface of the cell substrate (fig 27a).
PNG
media_image5.png
483
635
media_image5.png
Greyscale
Mizutano further teaches a pad on the second interlayer insulating film (250); and a via that extends through the second interlayer insulating film on the common source plate (640) and connects the common source plate and the cell pad to each other, wherein a bottom surface of the cell via is coplanar with the rear surface of the cell substrate.
PNG
media_image6.png
593
661
media_image6.png
Greyscale
Regarding claim 10.
Mizutano in view of Lu teaches the structure of claim 9.
Mizutani teaches a length of the cell via (316v) in the first direction is shorter than a length of the input/output via (16v) in the first direction (fig 27a).
PNG
media_image7.png
256
828
media_image7.png
Greyscale
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mizutani (US 2021/0035965) in view of Lu (US 2017/0352678) as applied to claim 1 and further in view of Kim (US 2021/0066277)
Regarding claim 8.
Mizutani in view of Lu teaches the structure of claim 1 above.
Mizutani in view of Lu does not teach a source contact that penetrates the first interlayer insulating layer.
Kim teaches a source contact (CSCP) that extends through the first interlayer insulating film (IDP) in the pad region and is connected to the common source plate (CSP2) (fig 14) (paragraph 94),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to for the source contact that penetrates the first interlayer insulating layer to improve operational characteristics of three-dimensional semiconductor memory devices, and it may be possible to reduce a chip size, because a passive device is disposed on a region that has not been used so far (Kim paragraph 95).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mizutani (US 2021/0035965) in view of Lu (US 2017/0352678) in view of Chhor (US 2002/0116668)
Regarding claim 20.
Mizutani teaches an electronic system comprising: a nonvolatile memory device, wherein the nonvolatile memory device includes: a cell substrate including portions respectively included in a cell array region, an extension region, and a pad region of the nonvolatile memory device, the cell substrate (18,218,240,440,640,230) including a front surface and a rear surface opposite to each other and including a common source plate (18,218,240,440,640) and an insulating pattern (230) (fig 27a) (paragraph 260); a mold structure on the front surface of the cell substrate and including a plurality of gate electrodes (46) and a plurality of mold insulating films (32) (paragraph 260), wherein the plurality of gate electrodes (46) and the plurality of mold insulating films (32) include respective first portions, and the first portions of the plurality of gate electrodes (46) and the first portions of the plurality of mold insulating films (32) are alternately stacked in the cell array region (fig 27a), and wherein the plurality of gate electrodes (46) and the plurality of mold insulating films (32) further include respective second portions, and the second portions of the plurality of gate electrodes (46) and the second portions of the plurality of mold insulating films (32) are alternately stacked in a stair shape in the extension region (fig 27a); a channel structure (58) that extends through the mold structure in the cell array region and is connected to the common source plate (fig 27a) (paragraph 260); a cell contact (86) in the extension region and is connected to at least one of the plurality of gate electrodes (46) (paragraph 111); a first interlayer insulating film (65) that is on the front surface of the cell substrate and extends on the mold structure (fig 27a) (paragraph 260); an input/output pad (16) in the pad region (fig 27a); an input/output contact (8p) extending through the first interlayer insulating film (65) in the pad region (fig 27a); and an input/output via (16v) that includes portions in the cell substrate in the pad region and connects the input/output contact (16) and the input/output pad (8p) to each other, wherein the insulating pattern (230) does not overlap the input/output contact (8p) in a vertical direction (fig 27a) (paragraph 260).
PNG
media_image8.png
597
1086
media_image8.png
Greyscale
Mizutani does not teach a second insulating film on the cell substrate.
Mizutani teaches a second embodiment comprising, a second interlayer insulating film (250) on the rear surface of the cell substrate (218,230) (fig 26h); an input/output pad (16) on the second interlayer insulating film (250); an input/output contact (8p) extending through the first interlayer insulating film (65) in the pad region (26h,27a); and an input/output via (16v) that includes portions respectively in the second interlayer insulating film and the cell substrate in the pad region and connects the input/output contact (8p) and the input/output pad (16) to each other,
PNG
media_image3.png
445
726
media_image3.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a second interlayer insulating layer in order to provide more dielectric separation and protection between the die surface and associated pads and the cell structure and associated metallization.
Mizutano does not teach the cell contact extends through the mold structure.
Lu teaches a cell contact (576) that extends through the mold structure and is connected to at least one of the plurality of gate electrodes (142) (fig 10a) (paragraph 138).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the cell contact to extend through the mold structure in order to enhance power distribution without excessively increasing the footprint of a semiconductor chip is also desired (Lu paragraph 3).
Mizutani does not teach a main board
Chhor teaches a nonvolatile memory device (200) comprising:
a main board (109) (paragraph 36); a nonvolatile memory device (112) on the main board (100); and a controller (111) electrically connected to the nonvolatile (paragraph 33) memory device (112) on the main board (100) (fig 2) (paragraph 36)
It would have been obvious to one of ordinary skill in the art to place the device on a board in order provide a substrate for packaging and electrical connection.
Allowable Subject Matter
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 12 through 19 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 11, the prior art does not teach in combination with all other elements of the claim, a nonvolatile memory device comprising: an extension pad on the second interlayer insulating film in the extension region; and an extension via that extends through the second interlayer insulating film in the extension region, includes a portion in the insulating pattern of the cell substrate, and connects the cell contact and the extension pad to each other, wherein a bottom surface of the extension via is coplanar with a bottom surface of the input/output via.
Regarding claim 12, the prior art does not teach in combination with all other elements of the claim; a nonvolatile memory device comprising: an extension pad on the second interlayer insulating film in the extension region; an input/output pad on the second interlayer insulating film in the pad region; a cell via that extends through the second interlayer insulating film on the common source plate in the cell array region and connects the common source plate and the cell pad to each other; an extension via that includes portions respectively in the second interlayer insulating film and the insulating pattern in the extension region and connects the cell contact and the extension pad to each other; and an input/output via that includes portions respectively in the second interlayer insulating film and the cell substrate in the pad region and connects the input/output contact and the input/output pad to each other, wherein: a bottom surface of the extension via and a bottom surface of the input/output via are between the front surface of the cell substrate and the rear surface of the cell substrate; the insulating pattern overlaps the cell contact and the input/output contact in a first direction that is perpendicular to the front surface of the cell substrate; and the common source plate does not overlap the cell contact and the input/output contact in the first direction.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.J.G/ Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 March 2, 2026