DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendments dated 01/20/2026 has been entered. Claim 15 & 16 has been amended. Claims 16-26 has been previously withdrawn. Claims 1-26 remain pending in application.
Response to Arguments
Applicant’s arguments dated 01/20/2026 with respect to rejection of claim 1 have been fully considered but are moot, since a new ground of rejection is made in view of same primary reference (Baliga) and none of the argument apply to current rejections. Specifically, redefining “drift region” including 202 & 230 which are both N type (see annotated FIG. 9K below), Baliga still reads the limitation “wherein a drift region that has the first conductivity type is adjacent to and under the well region, and the drift region is in contact with a second sidewall and a bottom surface of the well region” (see claim 1 rejection below).
Amendment overcomes rejection under 35 USC § 112 as indicated in previous office action. Accordingly, 112(b) rejection of claim 15 is hereby withdrawn.
Since a new ground of rejection is made, hence this action is made non-final.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baliga (US 6,800,897 B2).
Regarding claim 1, Baliga teaches,
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A semiconductor device (see Fig. 9K as annotated above), comprising:
a substrate (200, Col. 15, l. 60) that has a first conductivity type (n type, Fig. 9K);
an epitaxial layer (layer of 202 epitaxially grown on 200, Col. 15, ll. 58-59) on the substrate, wherein the epitaxial layer has the first conductivity type (n type, Fig. 9K);
a trench structure (as marked including 210a & 206/208) extending downward from a top surface of the epitaxial layer into the epitaxial layer (as seen),
wherein the trench structure comprises a conductive portion (doped polysilicon 210a, Col. 16, ll. 49-50) and an insulating layer (206/208, Col. 18, l. 20) that covers sidewalls and a bottom portion of the conductive portion (as seen);
a well region (228 as marked, Col. 17, l. 51) extending downward from the top surface of the epitaxial layer into the epitaxial layer (as seen),
wherein the well region has a second conductivity type (P type, Fig. 9K) and a first sidewall (left sidewall of 228 as marked ) of the well region is in contact with the trench structure (as seen),
and wherein a drift region (including 202 & 230, Col. 15, ll. 58-60, Col. 17, l. 52) that has the first conductivity type (both 202 & 230 are n type) is adjacent to and under the well region (portion 202 of the drift region as defined above is adjacent to and under well region 228),
and the drift region (portion 230 of the drift region as defined) is in contact with a second sidewall (right sidewall of 228 as marked above) and a bottom surface (portion 202 of the drift region in in contact with a bottom surface of 228) of the well region (228);
and a gate structure (234 as marked, Col. 18, l. 17) on the top surface of the epitaxial layer and over the well region (as seen).
Regarding claim 2, Baliga teaches the semiconductor device of claim 1 and further teaches, wherein a first side (right side) of the trench structure extends into the epitaxial layer along the first sidewall of the well region (as seen).
Regarding claim 3, Baliga teaches the semiconductor device of claim 2 and further teaches, wherein the first sidewall of the well region is in contact with an upper portion of the first side of the trench structure (as seen) , and the drift region is in contact with a lower portion of the first side of the trench structure (as seen).
Regarding claim 4, Baliga teaches the semiconductor device of claim 1 and further teaches , wherein a bottom surface of the conductive portion (210a) of the trench structure is lower than the bottom surface of the well region (228).
Regarding claim 5, Baliga teaches the semiconductor device of claim 1 and further teaches, wherein the well region (228) and the drift region (portion 202 of the drift region) are in direct contact with the insulating layer (206/208) of the trench structure (as seen above).
Regarding claim 6, Baliga teaches the semiconductor device of claim 1 and further teaches, further comprising: a first heavily doped portion (portion of N+ 233, FIG. 9K, Col. 18, l. 9) formed in the well region and extending from the top surface of the epitaxial layer into the epitaxial layer (as seen), wherein the first heavily doped portion has the first conductivity type (N+ type, FIG. 9K) , and the first heavily doped portion functions as a source region (233 is a source region , Col. 18, l. 9); and a second heavily doped portion (a top portion of P+ 228) formed in the well region (228) and adjacent to the trench structure, wherein the second heavily doped portion has the second conductivity type (P+ type).
Regarding claim 7, Baliga teaches the semiconductor device of claim 6 and further teaches, further comprising: a contact plug (portion of 238 as marked), disposed between the gate structure and the trench structure, wherein a bottom portion of the contact plug is in contact with the second heavily doped portion (in contact with the top portion of P+ 228) , wherein the drift region (202) is not disposed between the contact plug and the trench structure (as seen).
Regarding claim 8, Baliga teaches the semiconductor device of claim 1 and further teaches, wherein the conductive portion (210a) of the trench structure is electrically connected (via source contact 238 ) to a source terminal (source region 233, Col. 18, l. 9) of the semiconductor device.
Regarding claim 9, Baliga teaches the semiconductor device of claim 1 and further teaches, wherein the conductive portion (210a) of the trench structure is electrically connected to the gate structure (234).
Regarding claim 10, Baliga teaches the semiconductor device of claim 1 and further teaches, wherein the well region (228) is a first well region adjacent to a first side (right side) of the trench structure, and the semiconductor device further comprises: a second well region (P+ type 228 on left side of the trench structure as marked) extending downward from the top surface of the epitaxial layer into the epitaxial layer as seen), wherein the second well region is adjacent to a second side (left side) of the trench structure, the second side is opposite the first side, and the second well region has the second conductivity type (P type as seen).
Regarding claim 11, Baliga teaches the semiconductor device of claim 10 and further teaches , wherein the second side (left side) of the trench structure extends into the epitaxial layer along a first sidewall of the second well region (right side wall of 228 on left of the trench as seen) .
Regarding claim 12, Baliga teaches the semiconductor device of claim 11 and further teaches, wherein the first sidewall of the second well region (right side wall of 228 on left of the trench as per claim 11) is in contact with an upper portion of the second side of the trench structure (upper portion of the left side of the trench structure), and the drift region (202) is in contact with a lower portion of the second side of the trench structure (lower portion of the left side of the trench structure as seen).
Regarding claim 13, Baliga teaches the semiconductor device of claim 10 and further teaches , further comprising: a third heavily doped portion (233 on left as marked) formed in the second well region and adjacent to the second side (left side) of the trench structure , wherein the third heavily doped portion extends downward from the top surface of the epitaxial layer into the epitaxial layer (as seen), and the third heavily doped portion has the first conductivity type ( N type) ; and a fourth heavily doped portion (a top portion of second well region 228 on the left of the trench) formed in the second well region and adjacent to the second side (left side) of the trench structure (as seen) , wherein the fourth heavily doped portion has the second conductivity type (P type) .
Regarding claim 14, Baliga teaches the semiconductor device of claim 13 and further teaches, wherein the gate structure is a first gate structure (as marked) , and the semiconductor device further comprises: a second gate structure(234 on left as marked) formed on the top surface of the epitaxial layer and corresponding to the second well region (as seen); and a second contact plug (portion of 238 as marked) disposed between the second gate structure and the trench structure (as seen), wherein a bottom portion of the second contact plug is in contact with the fourth heavily doped portion (the top portion of second well region 228 as defined in claim 13 rejection above) , and no portion of the drift region is disposed between the second contact plug and the trench structure (as seen).
Regarding claim 15, Baliga teaches,
A semiconductor structure (see FIG. 9K as annotated below) comprising a plurality of the semiconductor devices as claimed in claim 1 (see as highlighted below),
wherein one or more of the trench structures (leftmost trench structure including 206/208) of the plurality of the semiconductor devices as claimed in claim 1 are electrically connected to one or more source terminals (233) of one or more of the plurality of the semiconductor devices as claimed in claim 1, and
wherein one or more remaining trench structures (rightmost trench structure including 206/208) of the plurality of the semiconductor devices as claimed in claim 1 are electrically connected to one or more gate structures (234) of the plurality of the semiconductor devices as claimed in claim 1.
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHATIB A RAHMAN whose telephone number is (571)270-0494. The examiner can normally be reached on MON-FRI 8:00 am- 5:00 pm (Arizona).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Steven Loke, can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.A.R/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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