Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Acknowledgment is made of the amendment filed 11/29/2025, in which: claim 1 is amended; claims 13-20 are withdrawn; claim 3 is cancelled; no new claims are added; and the rejection of the claims are traversed. Claims 1-12 are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant’s arguments with respect to claims 1, 6, 9, 10, and 12 have been fully considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 9, 10, and 12 is/are rejected under 35 U.S.C. 103 as being anticipated over Wei et al, US 20200212058, hereafter ‘Wei’ in view of Yu et al, US 20180144977, hereafter ‘Yu’, in further view of Shimomura, US 20230069307, hereafter ‘Shimomura’.
Regarding claim 1, Wei discloses : A semiconductor structure(#100), having a device region and a periphery region adjacent to the device region(#100 includes a memory array and peripheral devices for controlling signals[0004], the periphery region comprising an array contact defining region and a periphery contact defining region, the semiconductor structure comprising: a substrate(#102); a staircase structure(Fig. 1, #142) disposed on the (#110) and dielectric layers(#112) disposed alternately ; and a plurality of periphery contacts through the staircase structure in the periphery contact defining region(#136 through stair contact disposed in staircase region #142).
Wei does not disclose : an etch stop layer disposed on the staircase structure in the array contact defining region; and a plurality of array contacts disposed on the staircase structure and through the etch stop layer in the array contact defining region, wherein each of the array contacts has a first portion and a second portion under the first portion, a bottom surface of the first portion contacts a top surface of the second portion, and a cross- sectional area of the top surface of the second portion is smaller than a cross-sectional area of the bottom surface of the first portion.
However, in the same field of endeavor, Yu teaches : etch stop layer(#1180 acts as an etch stop layer[0085]) disposed on the staircase structure(Fig. 11, #1180 disposed on staircase) in the array contact defining region; and a plurality of array contacts disposed on the staircase structure and through the etch stop layer in the array contact defining region(Fig. 17, #1173 shown to be through #1180 on the staircase structure).
Shimomura teaches : wherein each of the array contacts has a first portion and a second portion under the first portion(Fig. 24b, #148v and #148p), a bottom surface of the first portion contacts a top surface of the second portion(Bottom of #148P contacts top of #148V), and a cross- sectional area of the top surface of the second portion is smaller than a cross-sectional area of the bottom surface of the first portion(#148v has a top surface smaller than a bottom surface of #148p [0196]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Yu to Wei to have an etch stop layer on a staircase structure of a 3D memory device to prevent short circuit during formation of contact structure(Yu, [0085]) and the contacts of Shimomura to Wei to enhance reliability of layer contact(Shimomura [0208]).
Regarding claim 6, Wei as modified by Yu and Shimomura discloses : The semiconductor structure according to claim 1.
Wei teaches : wherein top surfaces of the array contacts(Fig. 4D, #344) and top surfaces of the periphery contacts(#336) are flush(#344 and #336 may be formed by electrochemical depositions[0065-0066] and are shown to be flushed to the top surface of #305).
Regarding claim 9, Wei as modified by Yu and Shimomura discloses : The semiconductor structure according to claim 1.
Wei teaches : wherein the conductive layers form treads of the staircase structure(Fig. 3C, #309 is the exposed layer on the staircase structure).
Regarding claim 10, Wei as modified by Yu and Shimomura discloses : The semiconductor structure according to claim 1.
Wei teaches: further comprising: a stack(Fig. 1, #104) disposed on the substrate(#102) in the device region, the stack comprising conductive layers(#110) and dielectric layers(#112) disposed alternately, wherein the staircase structure(#142) disposed in the periphery region is an extension of the stack; and a plurality of active structures(#106) through the stack, each of the active structures comprising: a memory layer(#108) formed as an outermost layer of the active structure; a channel layer disposed along the memory layer; a dielectric material disposed in a space defined by the channel layer(#106 may include #108 channel structure which may include tunneling layer, storage layer, and blocking layer [0036-0037]; and a contact(#119) disposed on the dielectric material(#119 in contact with end of #108 [0038-0039]); wherein a plurality of memory cells are defined by cross points of the conductive layers in the stack and the active structures(memory cells provided at intersection of #106 and #110 [0031]).
Regarding claim 12, Wei as modified by Yu and Shimomura discloses : The semiconductor structure according to claim 1.
Wei teaches : a circuit layer(#111) disposed on the substrate(#102), wherein the staircase structure is disposed on the circuit layer(Fig. 1, #111 may be formed below #106 [0034], and the periphery contacts(#152) are connected to connectors and further connected to the circuit layer through the connectors(#148 provides electrical connection to #111 [0044]).
Claim 2 is/are rejected under 35 U.S.C. 103 as being anticipated over Wei et al, US 20200212058, hereafter ‘Wei’ in view of Yu et al, US 20180144977, hereafter ‘Yu’, in further view of Shimomura, US 20230069307, hereafter ‘Shimomura’, in further view of Fan et al, US 20190067306, hereafter ‘Fang’.
Regarding claim 2, Wei as modified by Yu and Shimomura discloses : The semiconductor structure according to claim 1.
Wei as modified by Yu and Shimomura do not disclose : wherein the etch stop layer is formed of carbon doped silicon nitride.
However, in the same field of endeavor, Fang discloses : wherein the etch stop layer is formed of carbon doped silicon nitride(etch stop is a carbon-doped silicon nitride material [0008]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Fang to Wei, Yu and Shimomura to have an etch stop layer over a staircase structure of a 3D memory device to have an etch stop composed of carbon doped silicon nitride to provide electrical connections to shallower conductive structures or deeper conductive structure (Fang, [0004])
Claim 4 is/are rejected under 35 U.S.C. 103 as being anticipated over Wei et al, US 20200212058, hereafter ‘Wei’ in view of Yu et al, US 20180144977, hereafter ‘Yu’, in further view of Shimomura, US 20230069307, hereafter ‘Shimomura’, in further view of Kim et al, US 20190333923, hereafter ‘Kim’.
Regarding claim 4, Wei as modified by Yu and Shimomura discloses : The semiconductor structure according to claim 1.
Wei as modified by Yu and Shimomura does not disclose : wherein each of the periphery contacts has a first portion and a second portion under the first portion, and a cross- sectional area of the second portion is smaller than a cross-sectional area of the first portion.
However, in the same field of endeavor, Kim teaches : wherein each of the periphery contacts has a first portion and a second portion under the first portion, and a cross- sectional area of the second portion is smaller than a cross-sectional area of the first portion(Fig. 9, #VS1 to include a bottom portion that is smaller laterally than the structure [0096-0097]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Kim to Wei, Yu, and Shimomura to include a periphery contact that has a bottom portion smaller than a top portion of a three-dimension semiconductor.
Claim 5 is/are rejected under 35 U.S.C. 103 as being anticipated over Wei et al, US 20200212058, hereafter ‘Wei’ in view of Yu et al, US 20180144977, hereafter ‘Yu’, in further view of Shimomura, US 20230069307, hereafter ‘Shimomura’, in further view of Sel et al, US 10319680, hereafter ‘Sel’.
Regarding claim 5, Wei as modified by Yu and Shimomura discloses : The semiconductor structure according to claim 1.
Wei as modified by Yu and Shimomura does not disclose : further comprising: a plurality of first spacer layers surrounding the array contacts; and a plurality of second spacer layers surrounding the periphery contacts.
However, in the same field of endeavor, Sel teaches : further comprising: a plurality of first spacer layers surrounding the array contacts(Fig. 26b, #48a surrounds word line contact via structure); and a plurality of second spacer layers surrounding the periphery contacts(#48a also surrounds #486 peripheral contact via structure).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Sel to Wei, Yu and Shimomura to have both array and peripheral contacts to include spacers.
Claim 7 and 8 is/are rejected under 35 U.S.C. 103 as being anticipated over Wei et al, US 20200212058, hereafter ‘Wei’ in view of Yu et al, US 20180144977, hereafter ‘Yu’, in further view of Shimomura, US 20230069307, hereafter ‘Shimomura’, in further view of Xu et al, US 20220293627, hereafter ‘Xu’.
Regarding claim 7, Wei as modified by Yu and Shimomura discloses : The semiconductor structure according to claim 1.
Wei as modified by Yu and Shimomura does not discloses : wherein each of the array contacts is surrounded by four periphery contacts that are closest to the array contact among the periphery contacts.
However, in the same field of endeavor, Xu discloses : wherein each of the array contacts(Fig.2B, #202) is surrounded by four periphery contacts(#214) that are closest to the array contact among the periphery contacts.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Xu to Wei, Yu, and Shimomura to have four periphery contacts surround an array contact to improve structural support (Xu [0022-0024]).
Regarding claim 8, Wei as modified by Yu and Shimomura discloses : The semiconductor structure according to claim 1.
Wei as modified by Yu and Shimomura does not disclose : wherein the periphery contact defining region comprises two separated regions, and the array contact defining region is between the two separated regions.
However, in the same field of endeavor, Xu teaches : wherein the periphery contact defining region(Fig. 2b, #R1 and #R2) comprises two separated regions, and the array contact defining region(#R0) is between the two separated regions.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Xu to Wei, Yu, and Shimomura to have an array region between two periphery regions to improve structural support(Xu [0022-0024]).
Claim 11 is /are rejected under 35 U.S.C. 103 as being anticipated over Wei et al, US 20200212058, hereafter ‘Wei’ in view of Yu et al, US 20180144977, hereafter ‘Yu’, in further view of Shimomura, US 20230069307, hereafter ‘Shimomura’, in further view of Kong et al, US 20220130854, hereafter ‘Kong’.
Regarding claim 11, Wei as modified by Yu and Shimomura, discloses : The semiconductor structure according to claim 10.
Wei as modified by Yu and Shimomura does not discloses : further comprising: a bottom conductive layer disposed on the substrate, wherein the memory layers of the active structures have disconnections in the bottom conductive layer such that the channel layers of the active structures are connected by the bottom conductive layer; and a connecting structure through the stack and stop in the bottom conductive layer, the connecting structure electrically connected with the bottom conductive layer.
However, in the same field of endeavor, Kong teaches : further comprising: a bottom conductive layer(Fig. 4, #108) disposed on the substrate(substrate may be included on bottom of #104 [0035]), wherein the memory layers(#414) of the active structures(#412) have disconnections in the bottom conductive layer(#414 disconnected in the lower portion of #412 [0045]) such that the channel layers(#416) of the active structures are connected by the bottom conductive layer(#416 exposed to be in contact with #108-1 [0045]); and a connecting structure through the stack and stop in the bottom conductive layer(#412 flushed with upper surface of #124 [0043], the connecting structure electrically connected with the bottom conductive layer(#416 electrically connected to #108 [0045].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Kong to Wei, Yu, and Shimomura to form active structures electrically connected to a bottommost conductive layer to form source contact structures (Kong [0030]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.T./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897