DETAILED ACTION
This office action is in response to amendment filed 12/29/2025.
Claims 1 and 3-16 are pending. Claim 2 has been canceled. Claim 16 is new. Claims 1 and 3-8 have been withdrawn. Claims 1, 4, 6, 9, 11 and 12 have been amended.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kao US 2007/0128810 A1 in view of Yedinak et al. US 2012/0273884 A1 (Yedinak).
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In re claim 9, Kao discloses (e.g. FIGs. 2 & 10) a semiconductor device, comprising:
a semiconductor layer 10,70 having a first (bottom) surface and a second (top) surface opposite to the first surface;
a first insulating layer (including 46,142,82,76) formed on the second (top) surface of the semiconductor layer;
a gate electrode 50,74 formed on the first insulating layer 46,142,82,76;
a second insulating layer (e.g. lower portion of 56,80) formed on the gate electrode 50,74;
a third insulating layer (e.g. upper portion of 56,80) which covers the first insulating layer 46,142, 82,76 and the second insulating layer (lower portion of 56,80); and
wherein the first insulating layer 46,142, 82,76 includes a gate insulating portion 142,76 interposed between the gate electrode 50,74 and the semiconductor layer 10,70, and the gate insulating portion 142,76 includes a curved side surface (curved side surface contacting 10,70, see annotated in drawing above) located between the gate electrode 50,74 and the semiconductor layer 10,70, and
wherein a minimum distance between the curved side surface and the semiconductor layer (the curved side surface is in direct contact with the semiconductor layer, thus the distance is 0) is smaller than a minimum distance between the gate electrode 50,74 and the semiconductor layer 10,70 (corresponding to thickness of 46,82).
Kao discloses the inventive structure for a high voltage transistor can be applied to VDMOS (¶ 31). Kao does not explicitly discloses the semiconductor device have a super junction structure, and a source electrode which is formed on the third insulating layer and includes a source contact portion in contact with the semiconductor layer by passing through the first insulating layer and the third insulating layer.
However, Yedinak discloses a vertical DMOS (FIG. 2) a source electrode 310 which is formed on the third insulating layer 317 and includes a source contact portion (portion extending between gates 314) in contact with the semiconductor layer by passing through the first insulating layer 340 and the third insulating layer 317. Yedinak further teaches the power MOS (FIG. 3) comprises a super junction structure formed by P-pillars 337 for reducing breakdown voltage variation and reducing drain to source on-resistance Rds-on (¶ 65,66,102).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form source electrode over Kao’s third insulating layer 80 to contact the source region by passing through the first insulating layer 46,76 and the third insulating layer 80 as taught by Yedinak for establishing electrical contact. It is further obvious to provide super junction structure in Kao’s VDMOS to reduce breakdown voltage variation and reduce source on-resistance Rds-on as taught by Yedinak.
In re claim 10, Kao discloses (e.g. FIGs. 2 & 10) wherein the first insulating layer 46,142,82,76, the second insulating layer (lower portion of 56,80), and the third insulating layer (upper portion of 56,80) are formed of an oxide film (¶ 30,34).
The recitation to thermal oxide film and CVD film pertains to product by process limitation that does not render the insulating layers structurally distinguishable over Kao’s oxide layers. In regard to the product by process language, since a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao and Sato et al., 190 USPQ 15 at 17 (CCPA 1976) (footnote 3). “[T]he lack of physical description in a product-by-process claim makes determination of the patentability of the claim more difficult, since in spite of the fact that the claim may recite only process limitations, it is the patentability of the product claimed and not of the recited process steps which must be established. We are therefore of the opinion that when the prior art discloses a product which reasonably appears to be either identical with or only slightly different than a product claimed in a product-by-process claim, a rejection based alternatively on either section 102 or section 103 of the statute is eminently fair and acceptable. As a practical matter, the Patent Office is not equipped to manufacture products by the myriad of processes put before it and then obtain prior art products and make physical comparisons therewith.” In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972). See also In re Luck and Gainer, 177 USPQ 523 (CCPA 1973); In re Fessmann, 180 USPQ 324 (CCPA 1974); and In re Marosi et al., 218 USPQ 289 (CAFC 1983). It is the final product per se which must be determined for patentability in a "product by, all of" claim, and not the patentability of the process, and that an old or obvious product, whether claimed in "product by process" claims or not, is not patentable. Note that Applicant has the burden of proof in such cases, as the above case law makes clear. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based upon the product itself. The patentability of a product does not depend on its method of production. If the product in product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product is made by a different process. In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985).
In re claim 11, Kao discloses (e.g. FIGs. 2 & 10) wherein the semiconductor layer 10,70 includes a step located below the gate electrode (where 142,76 is located).
In re claim 12, no specific “second surface” has been claimed that would distinguish over the top recessed surface of the semiconductor layer 10,70 contacting insulating layer 142,76. As such, the step is at the “second surface” and is therefore less than 25 nm with respect to the “second surface” (recessed surface contacting 142,76) in a direction orthogonal to the second surface.
Alternatively, although Kao does not explicitly teach the step is less than 25 nm with respect to the topmost surface in a direction orthogonal to the top surface, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to optimize the step height to obtain desired isolation effect between the gate and the semiconductor layer (¶ 28,34). “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
In re claim 13, Kao discloses (e.g. FIGs. 2 & 10) wherein the first insulating layer 142,76 and the second insulating layer (lower portion of 56,80) form a cavity 54,78 at least partially surrounded by the curved side surface (curved side surface of 142,76 contacting 10,70), and
wherein at least a portion of the cavity 54,78 is located between the gate electrode 50,74 and the semiconductor layer 10,70.
In re claim 14, Kao discloses (e.g. FIGs. 2 & 10) wherein the first insulating layer 142,76 and the second insulating layer (lower portion of 56,80) form a cavity 54,78 at least partially surrounded by the curved side surface (curved side surface of 142,76 contacting 10,70), and
wherein at least a portion of the cavity 54,78 is located between the gate electrode 50,74 and the step (step where 142,76 is located).
In re claim 15, Yedinak discloses (e.g. FIG. 3) wherein the semiconductor layer includes:
a first-conductivity-type drain region 324 having the first (bottom) surface;
a first-conductivity-type drift region 327,333 formed on the drain region 324;
a second-conductivity-type channel region 338 formed on the second (top) surface; and
a second-conductivity-type pillar region 337 connected to the channel region 338 and extending toward the drain region 324.
Claims 9-13 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mase et al. JP-H1154746 (hereinafter Mase, cited in IDS filed 11/13/2025) in view of Yedinak et al. US 2012/0273884 A1 (Yedinak).
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In re claim 9, Mase discloses (e.g. FIGs. 1-2 & 10-11) a semiconductor device, comprising:
a semiconductor layer 80 having a first (bottom) surface and a second (top) surface opposite to the first surface;
a first insulating layer 15,85 formed on the second (top) surface of the semiconductor layer;
a gate electrode 14,84 formed on the first insulating layer 15,85;
a second insulating layer (e.g. lower portion of 17,87) formed on the gate electrode 14,84;
a third insulating layer (e.g. upper portion of 17,87) which covers the first insulating layer 15,85 and the second insulating layer (lower portion of 17,87); and
a source electrode 16,86 which is formed on the third insulating layer (upper portion of 17,87) and includes a source contact portion in contact with the semiconductor layer 80 by passing through the first insulating layer 15,85 and the third insulating layer (upper portion of 17,87),
wherein the first insulating layer 15,85 includes a gate insulating portion 15,85 interposed between the gate electrode 14,84 and the semiconductor layer 80, and the gate insulating portion 15,85 includes a curved side surface (e.g. curved side surface contacting semiconductor 80 in FIG. 2, or curved side surface of undercut 90 in FIG. 11) located between the gate electrode 14,84 and the semiconductor layer 80, and
wherein a minimum distance between the curved side surface and the semiconductor layer (FIG. 2, the curved side surface is in direct contact with the semiconductor layer, thus the distance is 0; FIG. 11, the curved side surface of undercut 90 merges with the semiconductor 80, thus minimum distance is 0) is smaller than a minimum distance between the gate electrode 14,84 and the semiconductor layer 80 (corresponding to thickness of 15,85).
Mase discloses the inventive structure can be applied to power transistor (¶ 24). Mase does not explicitly discloses the semiconductor device have a super junction structure.
However, Yedinak discloses a power MOS (FIG. 3) comprises a super junction structure formed by P-pillars 337 for reducing breakdown voltage variation and reducing drain to source on-resistance Rds-on (¶ 65,66,102).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide super junction structure in Mase’s power MOS to reduce breakdown voltage variation and reduce source on-resistance Rds-on as taught by Yedinak.
In re claim 10, Mase discloses (e.g. FIGs. 1-2 & 10-11) wherein the first insulating layer 15,85, the second insulating layer (lower portion of 17,87), and the third insulating layer (upper portion of 17,87) are formed of an oxide film (¶ 6,26).
The recitation to thermal oxide film and CVD film pertains to product by process limitation that does not render the insulating layers structurally distinguishable over Mase’s oxide layers. In regard to the product by process language, since a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao and Sato et al., 190 USPQ 15 at 17 (CCPA 1976) (footnote 3). “[T]he lack of physical description in a product-by-process claim makes determination of the patentability of the claim more difficult, since in spite of the fact that the claim may recite only process limitations, it is the patentability of the product claimed and not of the recited process steps which must be established. We are therefore of the opinion that when the prior art discloses a product which reasonably appears to be either identical with or only slightly different than a product claimed in a product-by-process claim, a rejection based alternatively on either section 102 or section 103 of the statute is eminently fair and acceptable. As a practical matter, the Patent Office is not equipped to manufacture products by the myriad of processes put before it and then obtain prior art products and make physical comparisons therewith.” In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972). See also In re Luck and Gainer, 177 USPQ 523 (CCPA 1973); In re Fessmann, 180 USPQ 324 (CCPA 1974); and In re Marosi et al., 218 USPQ 289 (CAFC 1983). It is the final product per se which must be determined for patentability in a "product by, all of" claim, and not the patentability of the process, and that an old or obvious product, whether claimed in "product by process" claims or not, is not patentable. Note that Applicant has the burden of proof in such cases, as the above case law makes clear. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based upon the product itself. The patentability of a product does not depend on its method of production. If the product in product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product is made by a different process. In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985).
In re claim 11, Mase discloses (e.g. FIG. 2) wherein the semiconductor layer 80 includes a step located below the gate electrode 14 (near end 14a of gate).
In re claim 12, no specific “second surface” has been claimed that would distinguish over the top recessed surface of the semiconductor layer 80 contacting insulating layer 15. As such, the step is at the “second surface” and is therefore less than 25 nm with respect to the “second surface” (recessed surface contacting 80) in a direction orthogonal to the second surface.
Alternatively, although Mase does not explicitly teach the step is less than 25 nm with respect to the topmost surface in a direction orthogonal to the top surface, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to optimize the step height to obtain desired isolation effect between the gate and the semiconductor layer to prevent breakdown (¶ 31,37). “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
In re claim 13, Mase discloses (e.g. FIGs. 10-11) wherein the first insulating layer 85 and the second insulating layer (lower portion of 87) form a cavity (undercut 90 is not completely filled forming a hole, ¶ 6) at least partially surrounded by the curved side surface (curved side surface of undercut 90), and
wherein at least a portion of the cavity (hole remaining under end of gate 84) is located between the gate electrode 84 and the semiconductor layer 80.
In re claim 15, Yedinak discloses (e.g. FIG. 3) wherein the semiconductor layer includes:
a first-conductivity-type drain region 324 having the first (bottom) surface;
a first-conductivity-type drift region 327,333 formed on the drain region 324;
a second-conductivity-type channel region 338 formed on the second (top) surface; and
a second-conductivity-type pillar region 337 connected to the channel region 338 and extending toward the drain region 324.
In re claim 16, Mase discloses (e.g. FIGs. 1-2 & 10-11) wherein the semiconductor layer 80 includes a source region 88, and
wherein the curved side surface (e.g. curved side surface contacting source region 88 in FIG. 2, or curved side surface of undercut 90 at the end of gate 84 above source region 88 in FIG. 11) is located to overlap the source region 88 in a plan view.
Response to Arguments
Applicant's arguments filed 12/29/2025 have been fully considered but they are not persuasive.
Regarding claims rejected over the combination of Kao and Yedinak, Applicant argues the minimum distance between the curved side surface of the voids 54,78 and the semiconductor layer is greater than the minimum distance between the gate electrode and the semiconductor layer (Remark, pages 9-12).
This is not persuasive. As shown in annotated FIG. 10 of Kao shown above, the curved side surface is taught by a side surface of the insulating layer 76,142 that is in direct contact with the semiconductor layer 10,70. Since the curved side surface is in direct contact with the semiconductor layer, the distance is zero. While the minimum distance the gate electrode 50,74 and the semiconductor layer 10,70 corresponds to the thickness of insulating portion 46,82. As such, the minimum distance between the curved side surface and the semiconductor layer (i.e. distance is 0) is smaller than a minimum distance between the gate electrode 50,74 and the semiconductor layer 10,70.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896